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This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
About the Author
I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard.
I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
Synopsys is hosting our annual user’s group meeting (SNUG) at the Santa Clara convention center this week. Within SNUG we feature an IP Summit which includes presentations and tutorials on many of the IPs that Synopsys offers. In this year’s SNUG, we have eight in-depth technical sessions on PCI Express, 10G SerDes, FinFETs, DDR4, embedded memories and standard logic libraries and more. If you haven’t already registered, you can register on-site and it’s free! To see what’s happening at the IP Summit, you can use the IP Summit at-a-glance here: http://www.synopsys.com/IP/Pages/ipsummit2013.aspx
The PCI Express, presentation “In the Cloud with PCI Express” we will be examining many of the changes in PCI Express to improve performance in the networking, storage and server products used to build the data center side of the Cloud. For the client side, it’s all about power. We will discuss changes in PCI Express to address lowering power, which is crucial to extend the battery life of our mobile devices.
I’ll be at the IP Summit for the Designer Community Expo on Monday night (4:00 to 8:00PM) and I’m the Moderator on Tuesday afternoon for the DDR4 and PCI Express presentations. Stop by and introduce yourself and let me know how PCI Express is used in your products.
For over nine years, our customers have successfully implemented Synopsys’ DesignWare® PCI Express IP into their SoCs. We just announced the new DesignWare Enterprise 10G PHY. The 28-nm PHY is multilingual, speaking PCI Express 3.0, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, CEI-6G-SR, SGMII and QSGMII and supports data rates from 1.25Gbps to 10.3Gbps per lane. With support for the IEEE Energy Efficient Ethernet (EEE) standard, the PHY’s low power consumption targets a wide range of green, high-end networking and computing applications
The PCI Express 3.0 specification completely changed the protocol definition and added multi-tap decision feedback equalization (DFE) to the continuous time linear equalization (CTLE) utilized in PCIe 1.x and PCIe 2.x. With PCI Express 3.0 using 8Gbps, the channel experiences significantly more loss over PCIe 2.0, so to compensate, enhanced equalization is necessary. DFE is complicated stuff and as people have been implementing this for PCIe 3.0, the industry has gone through some growing pains. Synopsys had a webinar on PCIe Equalization on Jan 24, 2013 if you want to learn more about this subject.
Why improved levels of equalization are necessary at higher data rates
Types of equalization enhancements required for optimal performance at 8Gbps
The difference between decision feedback equalization (DFE) and continuous time linear equalization (CTLE)
The need for equalization training and adaptability in PCIe 3.0
The importance of proven interoperability between the PHY and the controller
Using this new PCIe 3.0 PHY IP with the DesignWare PCI Express controller IP gives you the best PCI Express interface on the planet (no, I’m not biased). By utilizing the PCIe 3.0 controller and PHY from a single vendor you eliminate the need to navigate all of the nuances of the PIPE specification to ensure the DFE equalization works for your PCIe interface.
Click on the links below to find more information on:
Happy New Year everyone! I wish you and your loved ones the best for 2013.
Unfortunately, this post is coming out a bit late as our Blog site was hit by a sophisticated malware attack and it was shut done for a while. Too bad these people don’t focus their efforts on improving the world.
To start the New Year, I spent part of the day watching football (American) with my beloved Michigan Wolverines playing in their final game of the year in the Outback Bowl against South Carolina’s Gamecocks. Great game! Unfortunately, I had to endure another loss with a touchdown in the last 11 seconds to give the Gamecocks the win and a final score of 33-28. I guess I need to switch to Michigan Basketball as they are doing very well this year. A man can endure only so many losses in one year!
I look forward to a new year working on PCI Express. I’m seeing a lot of activity on PCI Express 3.0 and several companies expressing interest in PCI Express 4.0. I can’t wait for the PCIe 4.0 specification to be finalized by PCI-SIG!
As a final thought. My daughters visited me at work and wrote on my whiteboard “Be Happy Every Day”. Good words to live by.
Virtualization technology essentially componentizes a computer system into the following:
Physical System: The computer hardware, e.g. processors, disk drives, memory, etc.
Virtualization Intermediary (VI): The VI abstracts the details of the physical resources, isolates them and then maps them into virtual resources, while managing their allocation in the system. Since the VI is creating and managing the virtual resources, it can create multiple virtual resources for each of the physical resources, while providing isolation between them.
Virtual System: The set of virtual resources required to run a system image is referred to as a Virtual System.
System Image (SI): The software component consisting of the operating system and applications that are assigned to run on a specific virtual resource. The system image only needs to know the details of the Virtual System they are assigned to.
PCI Express with Single Root I/O Virtualization (SR-IOV) enables some of the virtualization to be done in hardware for the I/O devices instead of software, thereby streamlining the Virtualization Intermediary. Of course, hardware runs faster than software for the same function, so PCI Express with SR-IOV helps improve the overall system performance of a virtualized system.
To understand the benefits of PCI Express with SR-IOV, you can watch SolarFlare’s demo that was videotaped in the Synopsys booth at the Intel Developer’s Forum (IDF) conference in 2011 (shown below). The demo utilizes two servers running Citrix XenServer 6 to showcase the 3x in performance achieved when utilizing PCI Express 2.0 with SR-IOV virtualization technology. By incorporating DesignWare PCIe IP with SR-IOV, SolarFlare’s Dual Port SFP+ 10GbE Server Adapters were able to support hundreds of virtual PCIe functions and thousands of virtual NICs, thus reducing total hardware costs and power consumption, while increasing performance.
It’s tough to explain such complex technology in a blog posting, but in a nutshell, PCI Express with SR-IOV enables virtualization of a single physical I/O device to masquerade as multiple virtualized I/O devices, one for each virtual machine and with complete independence from each other. You can learn more about how virtualization benefits PCI Express by reading this whitepaper:
The PCI-SIG Compliance workshop #84 is taking place December 4-7 in Milpitas, California. At the workshop, you can test your PCIe 3.0 device as part of the “official FYI testing” to see if your product passes compliance. However, “FYI” testing is “For Your Information” and not “official testing”, so even if your product passes compliance you won’t be able to list it on the PCIe 3.0 Integrator’s list because this is only FYI testing. Based on the ramp for Gen1 and Gen2, I’d expect “official testing” for Gen 3 to begin by mid next year.
Prior to the “official FYI testing”, there was pre-FYI testing. PCI-SIG uses the pre-FYI sessions to debug the test platforms, test software, procedures, and to get some feedback on early interoperability. Synopsys and our ecosystem partners (e.g. test equipment providers, etc.) have been working together on PCIe 3.0 testing even before PCI-SIG had pre-FYI testing. For Synopsys, all this testing ensures that our IP is robust and interoperable with other PCIe 3.0 devices. Not only does Synopsys benefit from passing these tests, but our customers benefit as well. When our customers are spending millions to fab a chip, it’s all about reducing risks and getting their products to market fast.
Since you are all probably tired from the initial Christmas shopping on Black Friday and Cyber Monday, I thought you might want to sit back, relax and enjoy some videos. At the PCI-SIG conference in Santa Clara this year, we videotaped demos using our DesignWare PCIe 3.0 digital controllers implemented on Synopsys’ HAPS 51 FPGA-based prototyping system.
The following demo showcases the high-performance PCI Express 3.0 interface operation at 8.0 GT/s. We show the performance throughput of a PC using an endpoint application designed with DesignWare IP for PCI Express 3.0 and use a LeCroy Summit T3 Protocol Analyzer to verify compliance to the PCI Express 3.0 specification.
This second demo uses an endpoint application as the design-under-test (DUT) and we execute PCI-SIG’s gold compliance tests to demonstrate how the DesignWare IP for PCI Express 3.0 is compliant to the specification.
On a sad note, I watched “The Game” on the Saturday after Thanksgiving. “The Game” is one of the oldest rivalries in college football between The University of Michigan Wolverines and that team from down south (no, I cannot mention their name). Unfortunately, Michigan lost 26 to 21. For those who have not read my bio, I am a graduate of the University of Michigan. M Go Blue! Unfortunately, red wine didn’t help me overcome the loss!
Why 4? PCI-SIG announced last November the fourth generation of the PCI Express specification operating at 16GT/s providing twice the throughput of PCI Express (PCIe) 3.0. This is the fourth generation of a standard that has replaced PCI, PCI-X and AGP to become the de-facto interconnect in digital office, servers, networking, digital home, storage and is quickly improving its position in mobile as well. BTW: What’s a MIPI?
If you haven’t seen the PCI Express 4.0 announcement, you can view it here:
As you’ve probably read my bio by now, I’ve been working with PCIe since 2003. The sheer number of PCIe customer designs that I’ve dealt with (over 650 controller designs to-date) gives me an interesting perspective on how designers are using PCIe in products. There are very distinct uses of the PCI Express interface. Designers that are building wireless hubs using PCIe have very different requirements than those building high-end computers and storage systems.
I’m constantly amazed at the speed at which this protocol changes to service its many markets. PCIe 1.0 (Gen1) brought us a serial protocol that moved the industry away from the problems of using parallel interfaces of PCI, PCI-X to give us more performance. However, Gen1 @ 2.5GT/s wasn’t fast enough for the graphics and server folks. It didn’t take long. Discussions started to provide an increase in performance and shortly an announcement for the next generation (Gen2) @ 5.0 GT/s was announced. Almost immediately, seemingly even before the spec was started, I was asked when I could deliver Gen2. We delivered, and delivered it early. It was clear though that the different market segments were moving at different paces. Those customers using PCIe for connectivity were moving at a different pace than the high performance computing crowd. Now, it seems that Gen1 is used less and less and customers have moved to Gen2 in the connectivity space, while the high performance types are moving on to Gen3. Gen3 is taking a while to digest due to the addition of the new equalization and the changes to the protocol, but products are out there and Gen3 saw a boost with Intel’s Ivy Bridge μPrelease. Now, on to Gen4 @ 16GT/s. Although PCI-SIG doesn’t release schedules, the first version of the PCIe 4.0 specification (0.3) is expected towards the end of this year. The performance treadmill keeps going and going.
As the speed continues to increase, the last year has seen a lot of activity to reduce power. As companies with a PC heritage move to bring tablets and ultrabooks to the market, they need to reduce the power consumption to extend battery life. This is for both active power and standby power. The first few changes were within the specification. These new features included the Optimized Buffer Flush/Fill (OBFF), Latency Tolerance Reporting (LTR) and L1 substates. Now, PCI-SIG is looking at using the MIPI M-PHY along with PCI Express to reduce the power consumption further. If you didn’t know that the MIPI and PCI-SIG organizations were talking, you should read this:
Yes, I do know what MIPI is. I worked on that for a while too.
I hope you come back to read further posts and Explore the world of PCI Express and its path to world domination; at least for chip interconnects …. And don’t forget your red wine. The Doctors say it’s good for you. Why should you argue with that advice?
Dr. Evil, you didn’t have a chance.
(For those of you that don’t know who Dr. Evil is, check out this YouTube video)
I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard.
I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
By utilizing the PCIe 3.0 controller and PHY from a single vendor you eliminate the need to navigate all of the nuances of the PIPE specification to ensure the DFE equalization works for your PCIe interface.
