This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
About the Author
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard.
I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.
Now that my kids are back to school, things are calming down slightly. Well, ok, the chaos is shifting gears :) I’m still recovering from IDF last week, and I owe you all a blog post about that, but I’ve been remiss in advising you of how you too can get “back to school” … with an upcoming Webinar on challenges you’ll face in PCI Express 4.0 design.
This Tuesday (16-September) at 11am Pacific, I’ll be talking through some key things PCIe 4.0 designers will need to know. There’s been a lot of talk about the PHY and electrical side of the upcoming specification, so I’ll mostly be focused on the controller side.
Here’s a quick teaser on the topics:
How the specification recommends handling re-drivers and retimers
Design changes to consider to handle new specifications on link equalization and the PHY interface
How multiple packets per clock cycle will affect designs using PCIe 4.0
Questions to ask for effective implementation of 16GT/s
So if you’re not too busy tomorrow (yes, I know, short notice!) please signup and follow along:
Sorry for the short notice (and short posting) – I’ll make it up to you with another “contest” perhaps. Note that I only had 2 winners last time, so your odds are excellent. Of course, the prizes might leave a little to be desired
All right, no monkeying around this year, I promise (mostly) not to make any IDFvs IDF jokes – mainly because nobody even tried to answer last year’s quiz question. (On that note, Scott and I had a quiz internally this spring for our field folks to see if they’d been following the blog… Let’s just say the results were NOT gratifying!)
Once again, Scott and I will be manning the Synopsys PCIe booth (#655 – which doesn’t spell anything interesting in telephone code), showing off all the cool “Gen4″ PCIe IP we have. Very much like a carnival midway you’ll be able to come by and look at scary eye diagrams from the Synopsys 16G PHY, run your very own simulation of a PCI Express link at 16GT/s, and compete in contests of strength to win fabulous prizes. Ok, Ok, I made that last one up.
IDF actually is a neat show because you get to see a lot more of the end products that PCI Express is used in. From what Scott and I are seeing, there’s no real sign of this trend slowing down. In fact, we’ve really been inundated with PCI Express in mobile applications this year, with a lot of folks trying to do very low power implementations so I’ll be interested to see how that translates onto the show floor. Of course, I’d bet good money that there’ll be a processor company around showing a few new CPUs, probably some related to internet-connected household items, etc, etc, etc.
Oh geez, stop bawling, please, no really, stop it, you’re embarrassing yourself. Look, I’ll tell you what – drop me a note, or leave your email for me in comments and I’ll give you a free pass. Yes, I’m completely serious – Synopsys got a bunch of free passes (only good on Thursday and only for the Showcase from 11am to 2pm, but that’s where I’ll be) so you can go online and register with the code** I’ll give you and you get in for completely and absolutely free. I won’t even make you help me tear down the booth afterwards!
I hope to see lots of you out at IDF, be sure to come by booth 655 and tell us how much you like the blog – or at least go by booth 773 and tell them how much funnier the other Synopsys blog is. :) Please leave your code request or code guess in the comments below, and as always, please don’t neglect clicking here to subscribe to ExpressYourself.
**If you want to try and figure out the code for yourself, here’s a clue – it’s the concatenation of the initials of a religious school in my town whose mascot is the Lions and the mnemonic for the Z80 opcode 0×00. Even if you don’t want to use the code to register, leave a comment or email me if you figure it out on your own and you’ll win 2nd prize.
UPDATE 2014-08-28: Perhaps I made the clues too easy, or perhaps ExpressYourself readers just really are that much smarter than average, but Seki-san e-mailed me with the correct code 3.5 hours after this posted! I’m willing to give out more 2nd prizes though, so don’t give up :) -Richard
For those of you that didn’t get to see our demos at PCI-SIG DevCon, you can view these new summer blockbusters featuring the latest videos with your favorite Synopsys PCI Express Controller and PHY IP. These videos are rated two thumbs up by Scott and Richard!
If interested in the May 22nd launch of the Synopsys PCI Express solution for PCIe 4.0 before the PCI-SIG DevCon in June you can review the press release here.
On to our featured PCIe Gen4 videos, our first summer blockbuster “Industry First: PCI Express 4.0 Controller IP” features one of our PCIe Controller developers, Paul Cassidy, demoing the Synopsys PCIe 4.0 controllers. He is using coreConsultant, our GUI interface, to configure our PCIe 4.0 core to support Gen4 with 16 lanes, showing other configuration options and showing simulation results in conjunction with our PCIe 4.0 VIP. The PCIe 4.0 controllers are Rated G for Generally available!
Next in our summer blockbuster series on PCIe Gen4 is “DesignWare PHY IP for PCI Express at 16Gb/s” featuring Synopsys’ very own Rita Horner, the TMM for PCIe PHYs, showcasing our latest PHYs running at 16Gb/s in preparation for Gen4. Using a Teledyne LeCroy scope, she shows the eye diagram and other PHY related information.
If you looking for something more nostalgic like PCIe Gen3, the star of our next summer blockbuster is Synopsys’ Gen3 28nm PHY and market leading PCI Express controller in the action movie: “PCI PHY and Controller IP for PCI Express 3.0”. Our PCIe 3.0 controllers are used in over a 150 designs and presented by Torrey Lewis, R&D for PCIe Controllers and Rita Horner, the TMM for PHYs. This demo runs a lot of traffic between a PC’s system memory and our PCIe Endpoint to show the throughput of the PCIe interface. We are also using a Teledyne LeCroy logic analyzer to display the different packets going through the system. The movie went for a G rating for Generally available, but the performance of the IP pushed the rating to an R as the IP Raced through all the performance tests!
If you’re looking for power savings while maintaining the PCIe protocol, M-PCIe is showcased in “Synopsys M-PCIe Protocol Analysis with Teledyne LeCroy”. John Wiedemeier, from Teledyne LeCroy, is using their new M-PCIe Protocol Analyzer attached to the Synopsys M-PCIe Controller and Gear3 M-PHY demo. It is important as new technologies are launched to work within the ecosystem to make sure that you can talk to other products using the protocol. The Synopsys M-PCIe controllers and M-PHY IP are Rated G for Generally available!
Just in case you needed something else to go with your movies, how about some good ol’ FPGA prototyping? Mick’s Posner’s Blog “Breaking the Three Laws” had a recent posting showcasing my PCIe market data and showcasing the Synopsys PCIe 3.0 Controllers running in the Synopsys HAPS DX prototyping systems available with the new IP Prototyping Kits. If you’ve ever tried to prototype high speed device in and FPGA, then you know this can be challenging. Using the IP Prototyping Kits, this is made easy for you. If interested, you can read Mick’s Blog here.
I hope you enjoy our videos. I understand that red wine is a great accompaniment while watching
For more information on the Synopsys PCIe solutions, please visit our web site.
Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
Wow, the last weeks have been just crazy crazy! Luckily Scott’s been on top of the blog for the last month or so, or you might have thought we’d dropped off the face of the earth. Actually, May was very hectic for me – I don’t think I had more than 36 hours straight at home for the last few weeks of the month. Scott and I visited some customers out in Texas, then there was the semi-annual Synopsys FAE training, and finally (lo-and-behold) I took an actual vacation! Squeezing in a week in Europe between FAE training and Devcon seemed like a good idea when I scheduled it, but Murphy’s Law came into play on my return. My 12-hour layover at home turned into arriving the next morning, changing suitcases and catching a late afternoon flight 4hrs after I arrived! All for you dear readers, all so I could make it to the Developers Conference.
Yes, actually those ARE purple PCI-SIG M&Ms… This year we (and by “we” I actually mean “Ruth”) wanted to do something a bit different for the speaker gifts, so in addition to fame, fortune, and seeing your name in genuine electrons, all the speakers at the PCI-SIG Developers Conference 2014 got a collector’s edition bag of purple PCI-SIG M&Ms! (Take that, IDF!) I actually quite liked the sentiment and felt it was appropriate for you blog readers, so I snapped the picture above. (Sorry, no I won’t be sending you M&Ms because I ate them all. Well, I shared them with my family and WE ate them all. I’ll make you a deal though, leave a legitimate and insightful comment and I’ll put together a care package for the first qualifying* respondent.)
Turn out was again record-setting for the second year in a row! (We beat last year by something like 5 people, but hey, a record is a record.) I’m particularly grateful for all of you who came to listen to me talk about PCI Express Controller Design Challenges at 16GT/s. Not just for putting up with my quickly fading voice (day 2 folks know it was pretty much gone by then) but also for the literally standing-room only crowd! I think that room was set for 75-80 people and we had well over 100 in attendance.
As always, the days were chock-full of great information on PCI Express, tasty snacks, and good company (I mean “networking”). It’s impressive how many companies are hiring for PCI Express expertise, and I personally introduced more than a few folks on both sides of that table. The acquisition of my former employer has left a number of good PCIe people (in design, verification, and customer support) looking for new “homes”. So if your company happens to need people, drop me a note!
Synopsys had a cool new booth design this year, and I know many of you were attracted (not in a Bug’s Life way I hope) to the displays and demos – particularly the 16G PCIe PHY and controller demos!
Speaking of demos, I have to give a huge shout out to Paul from our Dublin R&D office, who not only made the trip out to help get the controller demo going, but improved it by about 300% while I was fighting airline problems on Monday – and then found himself dragooned into doing the demo video when my presentation schedule and voice didn’t cooperate with our video crew. (I noticed the ladies all liked Paul’s accent too, maybe that’s why they weren’t sad when he replaced me!)
I’m sure I’ve forgotten more important things from my blogging hiatus, but I’m back now and I’ll try and keep you both informed and entertained … next month.
Thanks again for reading ExpressYourself and if you only found this by googling “PCI-SIG Developers Conference 2014 M&Ms” then please, by all the candy-coated goodness in this world, click here to subscribe to this blog! Feel free (unless you’re a SPAMbot of course) to leave a comment on any PCI Express topic(s) you’d like to read about in a future blog posting.
*Synopsys employees and family members are not eligible for the care package! Decision of the judge(s) is final in matters of insight and legitimacy. Your mileage may vary. Professional driver, closed course, do not emulate.
Hmm, why is “pci-sig developers conference 2014″ not the same as “PCI-SIG Developers Conference 2014″ to google?
For those of you coming to the PCI-SIG DevCon, you should stop by and visit the Synopsys booth (Booth 8 ) to learn about our high-quality, silicon-proven DesignWare IP portfolio for PCI Express, which includes controllers, PHYs and verification IP. See how our robust IP development methodology, extensive investment in quality, IP prototyping, software development, and comprehensive technical support enables designers to accelerate time-to-market and reduce integration risk.
In the Synopsys booth, we will have demos specifically targeted for our new PCI Express 4.0 products. If you stop by a watch a few of them, we will be giving away an iPad Mini! You can choose from:
DesignWare Controller IP for PCI Express 4.0
DesignWare PHY & Controller IP for PCI Express 3.0
DesignWare PHY IP for PCI Express at 16 Gb/s
Synopsys Next Generation Verification IP for PCI Express
You can also talk to our resident experts that will be in the booth or see them present in the technical sessions.
Synopsys Technical Presentations
PCI Express Controller Design Challenges at 16GT/s
PCI-SIG announced that the next generation of the PCI Express specification will move the maximum data rate from 8GT/s to 16GT/s. While most attention is initially focused on the high-speed SERDES design to achieve 16GT/s, there are substantial implications and challenges for designing the PCIe controller and the application logic to support these data rates. This presentation will offer an in-depth review of the critical design changes and challenges to the controller and application logic design to support the new bandwidth and traffic flow, PHY interface, and clock frequency. Designers and architects considering incorporating 16GT/s PCI Express functionality in their upcoming designs will benefit from attending, particularly those moving from a previous generation of PCI Express.
Presenter: Richard Solomon, Technical Marketing Manager, Synopsys Date/Time: Wed., June 4, 3:30-4:30 p.m.
Challenges and Benefits of SRIS in PCI Express Systems
Separate Refclk Independent Spread (SRIS) is a new usage model that allows PCIe links to exist outside the box, especially for high data rate PCIe 3.0 (8 Gbps) and upcoming PCIe 4.0 (16 Gbps) systems. SRIS will be used in chassis-to-chassis interconnect in high-end networking systems. This presentation will cover the challenges and benefits of integrating SRIS, including penalties for not sending the Refclk, jitter and EMI implications, and how other standards have dealt with similar issues. Designers and architects of high-end networking systems, as well as anyone using 8 Gbps or 16 Gbps PCI Express in their systems, will benefit from attending this presentation.
Presenter: Michael Lynch, R&D Manager, Synopsys Date/Time: Thurs., June 5, 1:30-2:30 p.m.
For more information on Synopsys’ DesignWare IP for PCI Express, visithere.
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.
The new DesignWare IP Development Kits provide a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers.
The IP Prototyping Kits provide a reference design on the HAPS-DX that runs right out of the box and can be quickly modified to support your specific configuration allowing design exploration and tradeoffs for your target application.
The DesignWare IP Virtual Development Kits provide a software development platform using a processor subsystem reference design including the OS and drivers for the IP. The beauty of this is the ability to start by using a virtual model of the IP as your target or use the HW on the HAPS-DX board as the target. It’s always great to get an early start by using the virtual model of the device, but move to the specific configuration running on an FPGA to ensure your software is working correctly.
SoCs contain multiple protocols and interfaces and the IP Accelerated Initiative supports the protocols that Synopsys offers. The IP Accelerated Initiative will help the designer using our DesignWare PCI Express IP by providing a software development platform and reference design along with our PCI Express IP that all coordinates together enabling concurrent software and HW development.
The last part of the IP Accelerated Initiative is to enable rapid customization and integration of the IP into the design. When I first started working at Synopsys in the IP group, we were working to convince people that using IP was a good thing. In talking to our customers, they all knew how to design the blocks for the protocols we were producing, so they would look through your code and architecture to see if it was better than theirs and it wasn’t just a make verse buy decision. Those days are past and purchasing IP is standard practice. The interesting side effect today is that designers are losing the expertise to implement the whole interface protocol on their chip as they move on to other portions of the SoC where they add higher value for their company. This is forcing a rethinking in the industry and customers are no longer looking to buy a PCIe PHY and PCIe Controller and put them together themselves for their SoC. Companies are looking to buy the whole interface from their IP vendor, but since it’s far more complicated than just stitching the two blocks together, the last part of the IP Accelerated Initiative focuses on delivering the full interface (in this case PCIe) to the customer with the customization and specific configuration needed for the SoC. Of course, this is carried further providing additional customizations, integration and verification based on the customer’s needs in order to get their SoC out the door.
If you’re at PCI-SIG this week, stop by our booth and say hello, discuss the IP Accelerated Initiative and see some great demos for our PCI Express 4.0 solutions. If you missed any of the press announcements you can view them here:
This seems strange to ask you, but “are you ready to start designing with PCI Express 4.0?” Why does it seem strange to ask? It’s because PCI Express 4.0 was announced in November 2011and the 0.3 version of the specification isn’t out yet (although I hear that it could happen in a few days). My very first blog posting was about PCI Express 4.0 on November 4th, 2012 “World Domination: PCI Express (4), Dr. Evil (0)”. With so much time passing, why would I write about it today and ask if you’re ready to start designing with PCI Express 4.0? Here is why: Synopsys announced our PCI Express 4.0 solution today. You can read all about it via our press release “Synopsys Unveils Industry’s First Complete PCI Express 4.0 solution”. We are providing digital controllers, PHYs and Verification IP that all support the new 16GT/s speeds in the PCI Express 4.0 specification, so you can include PCI Express 4.0 into your latest designs. Here are the highlights from the press release:
Industry’s first complete PCI Express® 4.0 IP solution, supporting the latest PCI Express 4.0 standard, will be featured on June 4th at the PCI-SIG® Developers Conference 2014 in Santa Clara, Calif.
Synopsys DesignWare® Controller IP for PCI Express 4.0 architecture provides port logic for endpoints, root complex, dual mode (endpoint/root complex) and switch applications with minimized latency, gate count and power consumption
Verification IP for PCI Express 4.0 architecture will verify PCI Express endpoints, switch and root complex devices with software/firmware equivalent application layers that vastly simplify testbench development
DesignWare PHY IP for PCI Express 4.0 architecture, currently in development, will offer advanced equalization capabilities to increase signal integrity at high speed data rates across legacy channels while offering optimized active and standby power
Availability of high-quality IP with early support for the PCI Express 4.0 specification lowers integration risk and accelerates availability of devices incorporating the new 16 GT/s speed
PCI Express 4.0 doubles the throughput over the previous 8GT/s supported PCI Express 3.0. A comparison chart between the different speeds supported in the PCI Express specification is shown below:
PCI Express 4.0 is backwards compatible with prior generations. While the PCIe 4.0 specification is still in development, the expectation for transitioning from PCIe 3.0 to PCIe 4.0 should be fairly straight forward, much like the PCIe 1.0 to PCIe 2.0 transition verses the PCIe 2.0 to PCIe 3.0 transition.
For those of you that already use the DesignWare PCI Express solution, you will find this an easy upgrade as it is built on top of the same architecture and keeping the interfaces and such the same. For those of you not using the our controller, come join the family of PCI Express users that use the solution used by more than 880 users.
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
Sorry, I’ve been very delinquent in posting – it’s been a busy month! As you might guess from the title, one of the things keeping me busy was doing last year’s income taxes. (Non-USA folks might not know the dread with which Americans approach April 15th each year – the day our income taxes are due.) Changing employers of course complicated things a little (apparently I managed to overpay Social Security) and I was lucky enough to have some nice gains in the stock market. Unfortunately I had some nice gains in the stock market so I went from filling out the “send us most of your money” tax forms to the “send us allyour money” tax forms. A time-honored American tradition is finding legal ways to manipulate money so as to pay less in taxes – apparently I’m not very good at this!
Ok, Ok, I know you’re thinking “Stop your whining Richard, this has nothing to do with PCI Express!”
Ah, but it does! You see, one of the questions I get asked ALL THE TIME (especially by people new to or not familiar with PCI Express) is “Why are you PCI Express people having such a hard time with X Gb/s when <some other standard> is doing 2X or 10X Gb/s already?“ The answer has EVERYTHING to do with “taxes” albeit in a manner a little different than a Federal Form 1040.
In this case, the “tax” is really a question of who pays for the extra speed. In a PCI Express system we’ve got a chip providing the Root Complex, some interconnect (PCB, likely a connector, another PCB), and another chip serving as the Endpoint. (You can of course add switches, and soon “extension devices“, to your heart’s delight, but the same “taxation” equation applies between them.) The same general architecture applies in many of these other standards (Ethernet, SAS, etc) but what you will usually find is that the costs of higher speed in those standards get spread more evenly – specifically to the interconnect portion. Have you priced a 12G SAS cable lately? (Probably not, given the spec isn’t out – but have you priced a 6G SAS cable even?) If you “tax” everyone in the infrastructure “equally” then the “pain” of a new implementation is spread pretty evenly.
PCI Express doesn’t work this way. Maybe it’s more “American” in this sense :) One of the code-words you’ll hear from PCI Express folks is “High Volume Manufacturing (HVM)”. Here’s a hint, HVM means “cheap”! The thought process is somewhat tied to traditional PC type systems – where every system includes PCI Express slots, but not every slot in every sold unit gets used. In fact, most slots sold go empty. Regardless, for PCI Express, the focus is on reducing manufacturing cost for the entire system. The theory is that silicon costs are one-time (you pay mostly for the R&D, the actual additional silicon cost for a more capable SERDES is small) but interconnect manufacturing costs are every-time (more expensive PCBs cost you in every unit sold). In other words, PCI Express taxes the silicon more heavily than the interconnect in order to help the overall system pay less of a “speed tax”.
Are you with me so far? So what we get with PCI Express is largely the same interconnect as we had with PCIe 1.0 – a bunch of really cheap (oops, I mean “High Volume Manufacturable”) FR4 PCBs with no fancy impedance matching, no fancy layer-to-layer connections, nothing at all which isn’t “HVM”. In electrical terms that results in channels which are, to quote Synopsys Fellow John Stonick, “really ugly!“ This puts a tremendous burden on the silicon side – the transmitter and receiver, aka the PHY or SERDES in each and every PCI Express chip. Instead of getting to tax the interconnect like those other standards do, the PCI Express spec is forced to make its speed increase almost entirely in the transmitter and receiver.
So next time you’re around someone who’s bemoaning the delays in PCIe 4.0′s 16GT/s “Gen4″ signaling and they wonder aloud “Why can’t those PCI Express guys get that spec done…” feel free to tell them the same thing I do:
“It’s something to do with avoiding taxes!”
Once again, thank you for reading ExpressYourself and in order to avoid the wrath of the IRS, click here to subscribe to this blog! Any non-SPAMbots reading this are also encouraged to leave me a comment with advice on how to reduce one’s income tax, or I suppose a PCI Express topic you’d rather read about in a future blog posting.
DISCLAIMER: this blog does not provide tax advice. The information provided herein is of a general nature and may or may not apply to your specific tax situation. The authors of this blog specifically disclaim any and all responsibility for any actions you may take with regards to your particular tax situation based on your reading of this posting. You should always consult with an actual tax professional before making financial decisions which may result in a situation in which, to quote the movie Minority Report, “large men with guns will appear”.
Well, I should know better, but in my New Year’s Resolution post I said “Those of you who are PCI-SIG members should soon see what PCI-SIG calls the ’0.3 draft’ of PCIe 4.0…“ Sigh. Did I say “soon”? I meant, “eventually” – oh crud, no, let’s be honest, I meant “soon”. If truth be told, I really thought “soon” would be before the end of Q1 … yeah, I know, that’s today…thus this blog posting.
Partially that’s because ever since PCI-SIG started putting out these 0.X drafts, the 0.3 of any specification has been little more than “We’re thinking about doing some new stuff, like A, B, and maybe C, unless you like D – which we might do if enough of you want it”. The standard for releasing a 0.3 is pretty low, it needs to have:
a problem definition
an architectural framework to solve the problem(s)
MAYBE some methods for solving the problem(s)
MAYBE (though probably not if a new spec) contains all the normal specification sections
Historically 0.3s have looked kinda like this one – a previous spec with a few pages of changebar material thrown in. So given that, you can see why I and others would expect PCI Express 4.0 Draft 0.3 to be a pretty quick drop – “Take PCIe 3.0 and run it twice as fast”. Things didn’t quite work out that way. There were some miscommunications within the PCI-SIG workgroups as well – one group sent its part of the spec for cross-workgroup review labeled as if it were the complete 0.3, etc, etc… All the same kinds of things that go wrong with “real” projects in your own company go wrong with standards organizations. Add in a 100% volunteer “workforce” all of whom have “day jobs” – usually in design and development, and you’ve got a perfect recipe for schedule creep.
The good news is that this time around, the 0.3 draft is going to actually be a draft – as in the specification in early form, not just an old spec with some very small amount of new material stuffed in here and there. We’re building on top of the PCI Express 3.1 specification, so 4.0 in all its drafts will look like a logical progression – because it will *BE* a logical progression!
“Whoa, hold it right there Mister!” you’re probably thinking about now “PCI Express 3.1 isn’t even out yet!!!”
Ah, yeah, there’s that too. Since we’re building atop 3.1, we kinda have to get 3.1 perfect and released before we can get the first 4.0 draft out. Again, all goodness in terms of getting a really solid spec, but all the time you can just hear Marvin saying “Delays! Delays!” can’t you?
Did I mention PCI-SIG has a new team of tech writers, who were volunteered by their company? So add in a learning curve to all the above, and toss in a ton of legacy documentation in old formats which aren’t very friendly to large documents. (I’m not going to name any names but if you’re thinking of a common word processor whose name rhymes with “bird” you’re probably dead on.)
Sorry, I guess this has ended up a lot more like a “dog ate my homework” posting than I really planned on, but at least the PCI Express 4.0 Draft 0.3 should wow you when it finally comes out … soon. <Ducking>
If I’m wrong this time around, then Marvin will likely blast me with his ACME Disintegration Pistol in sheer frustration.
As always, thank you for reading ExpressYourself and please avoid being zapped by an Illudium PU-36 Explosive Space Modulator by simply clicking here to subscribe to this blog! If you’re not a SPAMbot, feel free to leave a comment with your favorite Looney Toons character – or maybe a PCI Express topic you’d rather read about.
Unless you are Rob Ford of course, if you live in North America, you probably spent your Sunday morning much like I did – going around to every clock in the house and setting it an hour forward. If not, or if you ARE Rob Ford, then I’m sorry I didn’t post this blog entry on Saturday…
As I went around turning dials, pressing buttons, and occasionally grumbling aloud at the different sequences of buttons required to change various electronic devices’ clocks, I thought how nice it would be to have clocks which kept themselves in sync. Now, I do have a number of clocks and watches which synchronize themselves to the atomic clock in Ft. Collins, but the majority of my timepieces do not. (As an aside, my children will happily tell you that “Dad has too many watches!” – hey, I’m a techno-geek, and there are so many cool technologies in watches! Which, as a second aside, reminds me to send a note to Pebble asking them why the heck their “Smartwatch” wasn’t smart enough to switch to DST when the phone it’s paired with did…)
All these ruminations on time got me to thinking this might be the perfect day on which to discuss one of the lesser-known PCI Express functions – Precision Time Measurement (PTM) - which came out as an ECN to PCIe 3.0 early in 2013. Unfortunately, you can’t (yet?) go out and buy a new oven (or mayor as far as I know) with PCI Express PTM in it and never have to touch the time setting again, but PTM provides some new functionality to PCI Express which helps in other ways.
To understand why PTM is useful, we have to first think about where time is important in a system. As a note, when PTM refers to the “clock” it means the “wall clock” or “system time” (as in X seconds have elapsed since January 1st, 1970, or some similar measurement) as opposed to the reference clock or any other “clock” which causes digital logic to change state at some regular interval.
Consider one case where we have several instruments collecting data and sending it to a host for storage. PCI Express doesn’t make any guarantees about the order of arrival for packets from different agents, and depending on the topology, those packets could have very different delays from sender to the ultimate receiver. This means that each packet needs a timestamp so the host can reassemble the data in order – and prior to PTM, it would be entirely device-specific how those timestamps were created.
Consider another case where there are two different video cameras capturing the same scene from different angles – and we’d like the frames to all arrive at the host at about the same time so they can be processed together. (Think automotive collision avoidance systems, robotic vision, etc…) Here we not just want to be aware of the absolute timestamp, but the path delay for each component – so that we can adjust the buffering on our cameras to align not when the packets are transmitted, but when they will be received!
In order to achieve these things, PTM provides a new Extended Capability in PCI Configuration space which tells software that the device supports PTM, offers various enables for PTM operation, and includes information about the device’s internal clock (if any) frequency and granularity. Three new PCIe Messages are part of PTM:
The PTM Request and PTM Response are Msg (no payload) types, and signal PTM devices to make note of their internal timestamps at the time of transmission/reception. PTM devices then can calculate the time delay between components based on these timestamps. The PTM ResponseD is a MsgD (message with data payload) that includes a 64-bit time value and a 32-bit time propagation delay.
allows coordination of “wall time” between different PCIe devices
allows calculation of precise propagation delays between PCIe components
does NOT keep Richard from having to change his clocks between DST and non-DST times
Thanks for reading ExpressYourself, please leave a comment below with your thoughts on places PTM could be useful, or what Toronto should do with their mayor, or really any other non-SPAM topic. As always, if you haven’t already done so, please click here to subscribe to this blog - and don’t forget to set your clocks!