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  • About

    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Solomon

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

IDF Wrapup (aka Thursday’s IOT)

Posted by Richard Solomon on August 22nd, 2015

Yes, yes, I noticed that it’s not Thursday any more, thus the title change.  I feel like the IDF wrapup is somewhat anticlimactic though, so I hope you all weren’t hovering over your keyboards waiting for a grand finale.

Free day went about as expected – with hordes of interesting characters wandering around scarfing up giveaways.  (The guy with the waving monkey doll on his shoulder wasn’t even the most interesting one.) 

IDF_StarWars_UFDs_Small

Norma ran intercept so we didn’t give away quite as many pens as I thought we would – the radius of retirement communities stocked with Synopsys pens might have decreased to 50 miles from last year’s 100 miles :)

With fewer “real” attendees on hand I actually had a chance to walk around the exhibit hall a bit.  PCI Express storage was definitely one of the dominant themes!  NVM Express (NVMe) SSDs, NVMe RAID controllers, NVMe fabric adapters, etc…  I didn’t see any NVMe toothbrushes, but that might only be because I didn’t get to every booth!  All the NVMe folks I talked to were eager to see PCIe 4.0 come out soon, but there was a lot of mention of “the elephant in the room” – namely that with no PCIe 4.0 “Gen4″ platforms, designers would have a tough time validating their designs.  Imagine my surprise then when I returned to the booth and found this guy getting a demo!  (I think his shirt might have said “Gen4″ there where it’s folded up, but maybe that’s just wishful thinking…)

Gen4DemoElephant_Small

Show hours were only 11-2 which was good because my voice was starting to give out from all the Gen4 demo spiels I gave this week.  (This should actually be the best indicator of how many attendees found the demo interesting, because I can just picture a good half of you exclaiming “What? They wore Richard down to silence?!?!?!?“)  Teardown was uneventful – I’m happy to say there was no emergency room visit this year!  Scott and I spent quite a while poring over the demo takedown and repacking trying to figure out how Torrey had gotten everything into one packing case.

We managed to cram both cases into Scott’s trunk and he kindly gave me a lift to the San Francisco airport – a good deed which apparently did NOT go unpunished :( as he got stuck in one of California’s famous traffic jams* on his way from there home. 

So our takeaways from IDF 2015 are:

  • PCI Express storage, and NVMe in particular, are clearly dominating the direct-attach storage market
  • Despite any elephants (whether in hotel rooms or board rooms), there is a steadily building demand for PCIe 4.0′s 16GT/s “Gen4″ data rate
  • Synopsys is able to deliver working 16GT/s “Gen4″ solutions right now, so you can join the ranks of designers building their PCIe 4.0 products as the spec works its way to completion
  • Richard’s voice really is finite, and he should take a taxi to the airport next year

Thanks for following us here at ExpressYourself and please feel free to leave us comments with any insights YOU had at IDF.  If you’re reading this forwarded from a friend (or enemy I suppose) or if your email swap to Outlook365 broke your subscription, or you just have been putting it off for too long, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future episodes.

Richard

*I wish I’d made that part up, hopefully Mrs. Scott will forgive us for messing up their plans!

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Wednesday’s IOT (IDF Of Today)

Posted by Richard Solomon on August 19th, 2015

All rightee then – I’m glad to say the Live Blog format got a reaction :D  Oddly enough it was a mixed reaction – with some folks being all over it, and others thinking it was over the top…  I know, who would have thought *I* would be over the top????

Today was a bit less hectic than yesterday, though I’m going to be honest and say that it started out a bit oddly.  I’d noticed this strange box in my room when I first checked in:HotelRoomNoiseMaker_Small

You might recall that I was a bit disoriented yesterday anyway, so I didn’t pay much attention to the box, and I didn’t want a train running through my room so I left the thing safely off.

Housekeeping must have changed the setting from “Train” to “Meadow” without my noticing though, because when I woke up this morning, things had changed!HotelRoomNoiseMakerAnimals_Small

Needless to say I fled my room, met Scott for breakfast and headed in to set up the demo again (we’ve been shutting it down each night to be safe).  After a bit of begging and pleading, and a few reboots, the demo came back up.  Show hours were reduced today – *only* 11-1 and 4-7, so we got a break. 

I was again surprised and pleased at how many folks came by to see the PCIe 4.0 demo!  Lots of interest from SSD developers, several more system manufacturers, and a few folks representing other market spaces.  It’s *VERY* clear that anyone discounting PCIe 16GT/s for I/O does so at their own peril!  These guys want the bandwidth and they’re not happy about waiting for it!  Luckily for them, Synopsys has a complete range of  PCI Express controllers already delivering to customers.  I keep pointing out that in most cases, the hardest part of a PCIe 4.0 migration isn’t our (Synopsys’) part, but the customer’s logic needing to expand its internal bandwidth.  For some folks that’s a wider datapath, for others a faster one, but it usually has implications throughout their SoC.   By beginning design work right NOW with Synopsys’ draft 0.5 controller logic, SoC designers can focus on their jobs while we worry about tracking the PCI Express 4.0 specification – and dealing with any wild animals which show up uninvited!

By the way, I want to give a HUGE shout out to the PCI-SIG folks who were holding press briefings today.  Several press representatives showed up at the booth saying they’d heard about us at the PCI-SIG briefing and wanted to see the demo!  (I shouldn’t have to say it, but anyone reading this who is interested in doing articles or other publications on PCI Express should certainly contact Scott and/or me if they need material!)

Food at the show was pretty disorganized again today – quantities seemed to be improved, but an informal survey showed booth staff across the board missing out on the hot hors d’oeuvres.  No amount of searching, begging, or pleading was able to net me a non-diet Dr. Pepper either.  Once the show closed though, Scott and I were able to snag a surprisingly excellent pizza over at Jersey pizza.  I say surprising only because I am a HUGE fan of Chicago-style pizza – but perhaps aided by hunger, we both thought this was very good pizza.

IDF has had some sort of concert the last few years – which I generally skip due to exhaustion, but Scott convinced me to go over for a few minutes.  I quickly learned that there’s a huge difference in audience participation between a technical presentation and a rock concert.  Isaac Slade got a *MUCH* different reaction from the crowd when he strolled through during his “presentation” than I have when I’ve done the same in mine!  This is particularly amusing and relevant as today I ran across Ajay Bhatt (dubbed the father of PCI Express by many back in the day) and subject of the world’s most embarrassing TV commercial (oh heck no, that’s not really Ajay in the commercial).

Tomorrow is free day and therefore I expect to go through MANY more pens, so I’d better sign off and get some sleep!

Stay tuned for the final installation of IOT coming tomorrow…

Richard

*Nope, no “I made that up” in this posting!

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Tuesday’s IOT (IDF Of Today)

Posted by Richard Solomon on August 18th, 2015

I swear “IoT” must be the most overused term of 2015, so I’m coopting it in protest – though I’ll change the capitalization out of sheer orneriness  ;)

At least for the next few days, I shall use “IOT” for my “IDF Of Today” report.  I’ll be honest, I a) couldn’t figure out HOW to “live blog” on this system and b) couldn’t keep a good internet connection so you’re spared from my play-by-play… which today would have gone something like this:

10:30 Showed PCIe 4.0 demo to folks from a big-name storage company.

11:00 Show opened

11:01 Gave away first Synopsys pen to a member of one of the local retirement communities.

11:15 Showed PCIe 4.0 demo to folks from a big-name server company.

11:30 Ate boxed lunch (“beef” – although it engaged in a spirited debate with me on whether it was from a cow or not)

11:35 Promised Synopsys pen to gentleman with “Media” badge if he’d come by the booth.

12:20 Showed PCIe 4.0 demo to folks from a big server company whose name doesn’t rhyme with much of anything.

13:30 Showed PCIe 4.0 demo to engineers from a high-performance SSD manufacturer.

13:45 Showed PCIe 4.0 demo to fellow from a controller company specializing in high-bandwidth storage fabrics. 

14:00 Showed PCIe 4.0 demo to marketing manager from a new startup SSD company.

14:45 Showed PCIe 4.0 demo to someone from a company which sells PCIe PHYs.  Managed to refrain from asking such rude questions as “How can you claim to make a PCIe PHY when you’re not even a member of PCI-SIG?” and “Can you even spell ‘compliance’?”  Inadvertently tripped young woman in stiletto heels (which would be classified by TSA as deadly weapons*) while patting self on the back for professionalism.

15:00 Roamed show floor in search of snacks while Scott manned the booth.  Returned to booth empty-handed and ate a Synopsys mint.

16:00 Beer bar setup about 8 feet away from Synopsys booth.  Barman deluged with attendees asking for beer – told to come back at 16:15.

16:15:01 Growing line of beer patrons told beer bar would open 16:30.

16:30 Beer line begins.  Attendees quickly tire of my offer to “Buy you a beer if you’ll listen to me talk about PCIe 4.0!”  (No takers for the record.)

16:35 Scott brings by a pretzel – shares half with me.  We bemoan lack of salt on pretzel and lack of mustard.  Spend several minutes sketching out new DesignWare IP for Pretzel Twisting, decide the TAM is too low and scrap the idea.

16:40 Scott kicks me out of the booth to quell my grumbling stomach - which is apparently disturbing the line of attendees for beer.

16:44 I’m informed by the hot food servers that hot food will be available at 17:00.

17:00 Hot food station opens

17:00:15 Hot food line is confirmed by a fainting-from-hunger Steven Hawking** to be “longer than the event horizon of a black hole”.

17:10 End of hot food line is finally visible with naked eye.  I get in line only to see the serving station being wheeled away.  My tears of frustration move a hot food server to suggest I get in line for the Risotto “before the milk curdles”*** 

17:20 Gentleman with “Media” badge comes by looking for promised pen – puts up with my PCIe 4.0 demo and asks reasonable questions.  I give him the secret “upgraded” pen *AND* a Synopsys “these are not the ‘droids you’re looking for” USB stick.  (You too can get one of these if you come by the booth and tell us you read the blog – of course you’ll have to listen to the demo spiel first.)

17:30 I go get in line for ice cream sundaes. One poor server is valiantly struggling to serve two lines of attendees.

17:40 I reach front of ice cream line just as ice cream scoop breaks.  Overworked server runs away to replace scoop, angry murmuring begins among attendees in line.  New server arrives with scoop, I choose ice cream flavors which are less likely to break scoop (after loudly calling for an engineer to repair same). 

17:45 I share ice cream with Scott and Norma – to the envy of staff of nearby booths (one of whom allegedly fainted from hunger while trying to reach front of Risotto line).

18:00 Show PCIe 4.0 demo to another media member, we talk about likely spec timelines and various factors affecting the spec adoption.

18:15 With all food apparently gone, attendance drops significantly.  Booth staff now appear to massively outnumber attendees – perhaps a dozen of whom now roam the show floor relentlessly bombarded with demo offers and freebies.

18:59 Gave away 87th Synopsys pen to a member of one of the local retirement communities.

19:00 Show closes.

19:10 Demo shutdown, booth closed up – I walk over to Super Duper Burgers for a Super Burger with cheese & bacon, fries, and a vanilla shake.

Stay tuned for tomorrow’s exciting episode of IOT…

:)

Richard

P.S. So the takeaways from today are: 1) a *LOT* of folks are excited to see that PCIe 4.0 is really truly alive and running, 2) Either IDF got a MUCH smaller food budget this year, or a LOT more attendees than they planned!

 

 

*Ok, I made up the part about tripping someone – but the stiletto heels *DEFINITELY* would have been ruled deadly weapons by TSA, and I’m willing to take bets on this bit!

**I made that up, no physicists were harmed in the making of this blog posting.

***Yeah, yeah, I made that up too – no milk was harmed in the making of this blog posting.  (I’m pretty sure I really did guilt-trip the server though.)

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It’s August???? Where am I?

Posted by Richard Solomon on August 18th, 2015

When did THAT happen? The last thing I remember clearly was PCI-SIG Developer’s Conference – and that was June…  Next I know Scott’s banging on the door of my hotel room and yelling something about IDF????? Apparently I’m in San Francisco (which is odd, because I’d swear that last week I was in Milpitas as some of you know), and there were gray Synopsys shirts hanging in my closet so I threw one on and ran over to Moscone to help set up our booth….

IDF_Booth_Cropped

What’s that you ask? 

“Isn’t that the ‘Gen4′ demo there on the left?”

Why yes, yes it is :D

Those of you who might have attended a certain large chip maker’s recent briefing might have heard some waffling that sounded suspiciously like FUD… so come by booth #651 (sorry, the lights washed it out in the photo) and get the straight scoop on PCI Express 4.0 and see actual PCIe hardware running the 4.0 Draft protocol at 16GT/s!

Feel free to harass me at the same time about not keeping up with the blog and how Scott managed to get in 3 postings before I got to 1 :( Sorry for the short post – it’s 10:45 Pacific and the floor opens in 15 minutes, so come on down…and stay tuned for updates….

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The Next Frontier: Enterprise Computing and PCIe 4.0

Posted by Scott Knowlton on June 22nd, 2015

There will be many demos at PCI-SIG 2015 this week declaring readiness for PCIe 4.0. Synopsys is one of them and will be showing PCIe 4.0 controllers, PHYs and verification IP. Of course, it’s great that the industry ecosystem is gearing up to support PCIe 4.0, but the specification is still under development and we have a way to go before PCIe 4.0 is finalized.

The PCIe 4.0 specification was announced on November 29th, 2011 and we are still only at the 0.5 revision of the specification. Of course, I have customers that are getting impatient on how long it is taking for the specification to move forward and I have customers that are happy with PCIe at 5.0GT/s. For those pushing the boundaries of speed into a new frontier using the latest, smallest geometries – It’s going to be fun and we look forward to our continued partnership!

If you’re pushing the reliability and/or speed of your next generation system, you may want to review the Synopsys PCI Express announcement that went out today. “Synopsys PCI Express IP Adds System-Level Data Protection Features for High-Performance Cloud Computing SoCs”. Some of the highlights:

  • DesignWare IP for PCI Express delivers critical reliability, availability and serviceability (RAS) features to increase data protection, system availability and issue diagnosis for high-performance, data-intensive cloud applications
  • Support for the new PCIe 4.0 v0.5 specification gives designers the ability to start incorporating the latest functionality while meeting high-performance 16 GT/s data transfer speeds

In the latest release of our PCIe controllers, we have beefed up our data protection mechanisms to support the demanding requirements of super-fast computing, networking and storage (systems and SSDs). We’ve always had data protection support in our controllers, but the faster speeds and the smaller geometries have customers pushing for increased functionality and options for data protection. Along with the increase in data protection features, we have added several new features to help our customers debug their systems when something goes wrong during silicon debug, testing error conditions for their software or while the system is running. We have also added ways to monitor system activity statistically and through event monitoring. All of these features are being used by our customers to improve the reliability, availability and serviceability (RAS) of their systems. We hope you find these features useful for your next designs.

Of course, not to forget Gen4 at 16GT/s, the Synopsys Controllers and PHYs also support the latest PCIe 4.0 v0.5 specification.

If you’d like more information on what types of RAS features are interesting in the PCIe interface, you may want to stop by and hear Richard’s presentation at PCI-SIG 2015. Below is the abstract and more information.

PCI Express 16GT/s Design for Reliability

PCI Express 4.0’s upcoming 16GT/s speed offers data rates well above the frequencies of the ubiquitous microwave oven! Today’s designers have a number of unique challenges to design, debug and test their SoC’s before the product can go into mass production. Some of these challenges include multiple passes of equalization, understanding and tracking link reliability, determining/proving system-level reliability, and on top of it all the reawakening of long-dormant concerns about on-die soft errors due to shrinking silicon geometries. This presentation will discuss several features and techniques that SoC designers can use to design for higher chip reliability and observability.

Presenter: Richard Solomon

Date/Time: Tuesday, June 23, 1:00-2:00 pm

I hope to see you at PCI-SIG 2015. Stop by the booth and say hi and/or see our latest PCIe 4.0 demos.

For more information on the Synopsys PCIe solutions, please visit our web site.

Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.

Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.

Regards,

Scott

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Posted in Architecture, General Protocol, Market Adoption, PCI Express, PCI-SIG | Comments Off

Synopsys at PCI-SIG 2015

Posted by Scott Knowlton on June 22nd, 2015

Richard and I will be at PCI-SIG. For any of you that go to PCI-SIG, you know Richard will be doing several presentations, some for PCI-SIG and some for Synopsys, so you can find him walking around. For me, you’ll be able to find me in the sessions or at the Synopsys booth during the exhibit times. Catch us or stop by the booth and tell us about your latest PCIe projects. Both of us love to hear about the latest ways you’re using PCI Express in your designs. We also like it when you tell us you read the blog.

Of course, you’d expect a leader in PCI Express to be showing some cool demos and we will. PCIe 4.0 will of course be the highlight as it was for us last year. We continue to make progress even while the PCIe 4.0 spec is slowly moving forward…

Stop by the Synopsys booth to see demonstrations for:

  • Complete DesignWare IP Solution for PCIe 4.0
  • Industry’s First PCIe 4.0 Interoperability Demonstration (with Mellanox)
  • Synopsys Verification IP for PCI Express 4.0
  • Industry’s First PCIe® 3.1 Compliant Root Port IP

In addition, Synopsys and Keysight Technologies will show the industry’s first PCIe 4.0 system level link simulation vs. measurement correlation demonstration at the Keysight Technology booth.

I know you come to the booth for the cool demos, right? Well, just in case you come to PCI-SIG just to hear Richard’s jokes and not our demos, we are also giving away cool Star Wars themed USB sticks if you watch the demos and you could ultimately win a Parrot AR Drone Quadricopter 2.0!

We have technical papers in the sessions that you don’t want to miss.

PCI Express 16GT/s Design for Reliability

PCI Express 4.0’s upcoming 16GT/s speed offers data rates well above the frequencies of the ubiquitous microwave oven! Today’s designers have a number of unique challenges to design, debug and test their SoC’s before the product can go into mass production. Some of these challenges include multiple passes of equalization, understanding and tracking link reliability, determining/proving system-level reliability, and on top of it all the reawakening of long-dormant concerns about on-die soft errors due to shrinking silicon geometries. This presentation will discuss several features and techniques that SoC designers can use to design for higher chip reliability and observability.

Presenter: Richard Solomon

Date/Time: Tuesday, June 23, 1:00-2:00 pm

Replay and Debug of Post Silicon Bugs in Simulation

 PCIe core designers have to balance verification completeness with time to market constraints. It is impossible to fully validate a PCIe core especially when one considers the possibility of real world issues that present themselves outside of the PCIe functional specification. Given certain issues will be uncovered post silicon whether in the lab or in a customer’s hands there is the need to easily replay the condition in simulation where the issue can quickly be debugged. This session will cover how through simulation with verification IP, error conditions can be replayed in simulation through both automated and user controlled techniques allowing for the possibility of replaying almost any scenario seen in silicon. The session will also address how source based compliance tests can be enhanced to prevent the future introduction of such bugs.

Presenter: Paul Graykowski

Date/Time: Wednesday, June 24, 1:30-2:30 pm

Enabling Complex PCI Express 4.0 Design Validation

Increasing pressure for faster time-to-market in complex designs using PCI Express 4.0 and other high data rate interfaces has spurred the need for quick and accurate link performance validation. IBIS Algorithmic Modeling Interface (IBIS-AMI) has become well known as a common and efficient validation methodology by both system developers and SerDes IP providers across different standards. In this presentation we will explain what an IBIS-AMI model is, how we incorporate circuit simulation results into the model, and demonstrate the accuracy of the approach by comparing IBIS-AMI simulation results to silicon measurements for a 16 Gbps PCIe 4.0 link.

Presenter: Pegah Alavi, Keysight

Date/Time: Tuesday, June 23, 10:30-11:30 am

On last thing before I go. Richard said he’d do a dance up on stage if there was 50% voter turnout in the recent PCI-SIG elections. I’m not sure if that happened, but I suggest that everyone chant DANCE, DANCE, DANCE at the end of his opening session on Tuesday. Let’s get him to dance up on stage and please make sure it ends up on YouTube!

For more information on the Synopsys PCIe solutions, please visit our web site.

Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.

Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.

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Posted in Applications, General Protocol, PCI Express, PCI-SIG, Specification, Uncategorized | Comments Off

Low Power, Phones, Tablets and PCIe, Oh My!

Posted by Scott Knowlton on May 21st, 2015

First, I’m sure there are some of you that look at this and think “what the heck”? PCIe being used in phones and tablet devices? How can that be? Rest assured PCIe has been used in mobile devices for a long time. Of course, laptops have been using it, but it’s also being used in phones and tablets for some time now. You may remember that PCIe with the MIPI M-PHY and say, that’s what Scott’s talking about, but no. This is the full blown PCI Express in these devices operating at 5.0GT/s and 8GT/s.

Who wants to put a PCIe PHY developed for driving backplanes and across multiple connectors into a phone? Good question! The ability to do this really comes down to managing the power in the PHY and controller in coordination with the rest of the chip design connected to a small channel. Of course, L1 substates was a huge stride to get you there, but the power needs to be reduced even further. Nobody wants their phone or tablet using up power when you are not using it, just to be dead when you need it. The interface needs to be completely off and this can be done when using L1 substates in conjunction with power gating techniques.

If you are developing applications, especially battery based applications that require low-power, you should take a look at our announcement today “Synopsys Announces Industry’s Lowest Power PCI Express 3.1 IP Solution”. Some highlights from the press release:

  • Power management features such as L1 sub-states and use of power gating, power islands and retention cells cut standby power to less than 10 uW/lane in the PHY and up to 95% reductioin in leakage current in the controller
  • Support for supply under drive, a novel transmitter design and equalization bypass schemes reduce active power consumption to less than 5 mW/Gb/lane
  • Offers small area, built-in at-speed production testing and optional wirebond packaging to lower overall BOM cost
  • Reduces active power while meeting the PCI Express 3.1 electrical specification

While any application can benefit from using a low power PCIe solution, battery powered mobile devices tend to gain the most with the Synopsys PCIe solution. Our customers are looking to lower the power in both active and standby modes enabling the prolonging the battery as much as possible.

For more information on the Synopsys PCIe solutions, please visit our web site.

Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.

Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.

Of course, Richard and I will be at PCI-SIG DevCon in Santa Clara, June 23, 24. Stop by and tells us how much you love the blog.

Scott

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Posted in Architecture, General Protocol, Low Power, M-PCIe, M-PHY, PCI Express, PCI-SIG, PHY, Uncategorized | Comments Off

Election Season – Re-elect Richard to PCI-SIG Board of Directors

Posted by Richard Solomon on May 7th, 2015

No, it’s not super-Tuesday, but yes, it is election season … for the PCI-SIG. 

Judging by how few companies bother to vote in the PCI-SIG Board elections, you’re forgiven if you don’t realize there even *IS* an election!  (Ok, so there are many years in which the incumbent board runs unopposed, so it’s even less obvious then.)  I talk a lot about which “hat” I’m wearing at various times, and this is the time of year I have to dust off my least-favorite hat of all:
Please Vote! Hat
Frankly I *HATE* the political side of standards work – and “campaigning” for votes is probably the worst part of that!  Here in the US, presidential elections run between 50 and 60% turnout of eligible voters and I would dance in the streets* if we got that many for the PCI-SIG board election!

Now here’s your quick-reference guide to PCI-SIG voting:

  • All member companies are eligible to vote
  • One representative from each company casts a single vote for up to 9 candidates from a slate of up to 12 people
  • Board members serve as *INDIVIDUALS* but must be employed by a member company
  • Board members’ companies are expected to be significant contributors to the work of PCI-SIG

You don’t have to figure out where your local polling place is, or drive across town to city hall, and you certainly don’t have to stand in line.  All you have to do is click over to the PCI-SIG Election page: https://www.pcisig.com/members/bod_vote_15.  There you will see links to the candidate presentations, and if you are the designated voting rep for your company, a link to the actual ballot.  Otherwise you will be directed to your company’s voting representative – *please* contact that person and ask them to vote for me, or at least to vote!  NOTE: The election closes at noon Pacific time on May 19th, so don’t dawdle.

Those of you who participate in the various PCI-SIG workgroups hear me often in the Protocol and Compliance Workgroups, along with John Stonick and other Synopsys folks in the Electrical and other Workgroups.  Please consider which of the candidates’ companies are actually active members!  I’m not sure why someone from a company that doesn’t participate in or even observe ANY workgroup would claim to be supporting the PCI-SIG, but I guess that’s politics :(

You can download my election presentation here, but the highlights won’t surprise anyone who reads this blog:

  • I have over 10 years experience on the Board of Directors and am currently the Vice-President of the PCI-SIG
  • I’m deeply involved in PCI Express development, participating actively in several workgroups and I’m a frequent presenter at PCI-SIG training events
  • I’ve been involved in PCI development for over 20 years (going back to pre-1.0 versions of the original parallel PCI)
  • I hold 26 US Patents, many of which relate to PCI technologies
  • Synopsys supports all PCI Express specifications
  • Synopsys has over 40 engineers committed to multiple workgroups
  • Synopsys sponsors PCI-SIG events around the world

Please do take a few minutes to click through to the election page, read the candidate presentations and make your own determination.  If you’re not the voting member for your company, please convince that person (listed when you click through) to spend a few minutes on this – BEFORE May 19th.  Especially if turnout remains low, one company’s vote can easily make a direct impact on the election outcome!

Thanks for reading this far, I’ll return you to our normally scheduled blogging.

Richard

*Ok, how’s this – if PCI-SIG gets over 50% voter turnout this election I will dance on the stage at the US Devcon – which will be a Youtube-era fate worse than death!

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“Soon” is finally “now!” – PCIe 4.0 draft 0.5 released today

Posted by Richard Solomon on April 10th, 2015

Yes, yes, I know that I’ve been saying for months that we’d see the next draft (0.5) of PCIe 4.0 “soon”.  Yes, I know that “soon” is not usually considered “3-4 months” – but in my defense, remember that we’re talking about standards here…. and hitting the same year as originally promised is often considered above-average performance :(

Because this is a public blog and open to non-PCI-SIG members I can’t go very deeply into the details of what’s in draft 0.5, but I can suggest that everyone download it.  Pay particular attention to the first page “Open Issues” and “Anticipated changes that reviewers should be aware of”.  None of these should be particularly surprising (and I’ve talked about some of them at PCI-SIG Devcon before) but they’re good heads-up items.  Of course most of the changes are in Chapter 4 (PHY Logical) and Chapter 9 (Electrical) – though I’ll note that the electrical chapter doesn’t yet include results from the two PHY test vehicles (here’s a hint as to their identities – they demonstrated interoperability at PCI-SIG Israel last month).  To save you some trouble finding the downloads (especially if you happen to be reading this after the review period closes), here are the links for the changebar and non-changebar versions.  Both the protocol and electrical workgroups would very much like your feedback, so please do take some time to go through this draft and return comments before May 11.  If you have opinions on those Open Issues (and here’s a hint – you should!) then I especially encourage you to provide feedback.

For those of you attending the upcoming PCI-SIG Compliance Workshop (#93) the week of April 21-24, I expect to be around the first couple of days so feel free to track me down and say “Hi”.  Hmmm, maybe I should come up with a special prize for the first ExpressYourself reader to find me onsite and tell me the altitude shown on my GPS picture from last month’s posting.

Speaking of upcoming events, I hope everyone here has the US Devcon dates marked on their calendar!  (That’s June 23-24, still at the Santa Clara convention center.)  I’ve heard from a few of the workgroup chairs that they have more new PCIe 4.0 information to present, so there should be a lot more than just electrical “stuff” on the PCIe 4.0 front this year.  Of course this is open only to employees of PCI-SIG member companies, but a) if you’re doing any kind of PCI Express development you really SHOULD be a PCI-SIG member and b) people have been known to join PCI-SIG just to hear my jokes during the presentations*.  While I recognize that not too many of our non-US readers get the opportunity to come to US Devcon, please keep an eye on the PCI-SIG Events page – I think folks in Asia will be very happy this October!  For those in Europe looking for a local event, especially if you missed the Israel Devcon, my best advice is to email PCI-SIG administration (yes there’s a real email address, yes you already have it, but NO I won’t post it here for joyful consumption by SPAMbots) and request one.  (I suggest offering to bring 100 of your closest friends.)

As always, thanks for following us here at ExpressYourself and please feel free to leave us comments on what you think of Draft 0.5 (of course send detail feedback to PCI-SIG, but tell us how you really feel).  If for some crazy reason you haven’t already done so, please click here to subscribe to ExpressYourself so you don’t miss anything.

Richard

*Ok, so that’s an obvious lie :)  On the other hand, I promise a very special gift to the first person who can prove their company newly joined PCI-SIG and put “We want to hear Richard’s jokes at Devcon” down on the application!

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PCI-SIG Israel: “Gen4″ 16GT/s Live Wires and the Dead Sea

Posted by Richard Solomon on March 12th, 2015

Well, we’re back from the PCI-SIG Developers Conference Israel 2015 and by now, between Scott and me we might make up one coherent person!  (I know, given the blog frequency lately, you probably thought Scott and I had been kidnapped by aliens.  I have no comment on that beyond “We’re back!“)  This was the third Israel DevCon and as always I was pleased with the fantastic turnout.  I mean, it’s a hardship going to Israel, but somehow we tough it out…

 HiltonWindowView

Oh wait, did I forget to mention that Tel Aviv is on the Mediterranean? :)

Unfortunately the weather was that gorgeous most of the time – that we were inside working.  Admittedly, most of the PCI-SIG presentations were from the US Devcon, but it’s always much more interesting and useful to hear and see the material presented than to just read the slides.  As usual it fell to me to try and wake up the early arrivals with PCI Express Basics & Background, as well as break the post-lunch lethargy with PCIe 3.1 Protocol.  Perhaps reinforcing my point about live presentations, one of the attendees commented (about the Basics) “I’ve seen you give this same presentation 2 or 3 times now, but I learn something new each time!”  On the second day I got to take off my PCI-SIG hat and put on my (metaphorical) Synopsys hat to talk about PCI Express Controller Design Challenges at 16GT/s.  In between sessions over breaks and mealtimes, we manned the booth.  Well, in truth, mostly our colleague Robert manned the booth as he got to show off our joint 16GT/s “Gen4″ demo with Mellanox!  Meanwhile Scott and I practiced looking pretty and showed our “Gen4″ controller demo to folks waiting to talk to Robert.  Yep, you read that right, Synopsys and Mellanox were both showing 16GT/s PCIe PHYs communicating with each other over some pretty nasty test channels!

Booth

Yeah, yeah, I know you can’t see much of the demo – I never claimed to be a photographer!  Scott did a little better, but it’s hard when you’re overrun with interested attendees – and I’m told it’s bad marketing to push your customers out of the way to take pictures.

Booth2

To answer a few question I know folks will be asking:

  • Yes, it’s real silicon: Synopsys fabs test chips for each of the PHYs we design, and Mellanox rolled theirs into another chip they were producing anyway.  You might have remembered that Synopsys demonstrated a 16GT/s PCIe PHY standalone last June.
  • Yes, they’re two completely independent designs.  Both companies participate actively in the PCI-SIG and we’ve both been pretty open about what we’re doing, so it was a pretty obvious partnership opportunity as we both looked to demonstrate our individual PHYs at the DevCon.  (Mellanox in fact submitted their complete characterization as part of the PCIe 4.0 specification development – see their presentation for more details.)
  • No, of course we can’t claim compliance to PCIe 4.0 as it’s not final yet.  Naturally, the spec numbers are based in part on the characterization results of test silicon, so…

“Ok then, what’s the bit about the Dead Sea?”

Well, I was looking for a catchy blog title (as I always do) and if truth be told, I thought of the Dead Sea first – then worked in the Live Wires… All that because Scott and I did end up with a little free time (Shhh, don’t tell management!) and took a tour out to Masada and down to the Dead Sea.  Being the data geek that I am, of course I had to bring along my GPS – well, ok, so I logged the entire trip on my GPS.  For your amusement I present this:

DeadSeaAltitude

Yep, that’s correct: 1281 feet *BELOW* sea level (some 400 meters for you metric folks).  I know, even I can’t come up with a way this relates to PCI Express, but I’m sorry – that’s just cool!  Especially for someone from Colorado who hangs out at around 6500 feet most of the time.  (Colorado’s unofficial motto is “Never trust anyone under 14,000 feet”)  I also have no excuse to work in any pictures from Masada – unless you leave a comment telling me of a way that connects to PCIe – so you’ll have to get those from me next time you see me in person.  Hey now, that I can connect to PCI-SIG  – make sure to mark June 23-24 on your calendars - at least the US folks and anyone else who can talk their management into a trip approval!

Well that’s it for now – I’ve got to go clean what’s either Dead Sea slime or some kind of alien excretion off my old tennis shoes.  Please do leave a comment with topic ideas so we can blog more often, and if you aren’t already, then click here to subscribe to ExpressYourself – quick before the aliens come back!

Richard

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Posted in Architecture, General Protocol, PCI Express, PCI-SIG, PHY, Specification, Uncategorized | Comments Off