This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
About the Author
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard.
I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.
Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am
Oh, you are but you’re just impatient! Ok, that I get! Plus I’ve never been accused of being patient. Here you go: buried inside today’s Synopsys Press Release on latency improvement is this
“Synopsys’ DesignWare PHY and Controller IP for PCI Express 4.0 technology has been tested for interoperability using the Teledyne LeCroy Summit Z416 Protocol Analyzer/Exerciser, which is targeted to test for PCIe 4.0 compliance in the near future,” said John Wiedemeier, product marketing manager at Teledyne LeCroy. “This is an important indicator to all designers and the ecosystem that the DesignWare IP works as expected and meets the latest PCI Express specification requirements, mitigating risk and accelerating time-to-market.”
Wait a minute Richard, do you mean to tell me you’ve now got FULL interoperability with someone else’s PCIe 4.0 implementation? And that someone is a test-equipment vendor dedicated to checking that you’re following the spec?!??!
Yep! It’s really better seen in action, so come run with the leader of the big dogs – because otherwise the view doesn’t change much! (Don’t worry, we’ll get a Youtube video out there soon so even those poor souls not making it next week will be able to see too.)
Full disclosure: this is NOT a posting about PCI Express ordering rules, though that’s a great topic which I’ll use for a future posting.
This began life as a SNUG China posting, but what actually struck me more was a small incident which happened on my trip to China last week. Knowing that I was going to spend a week eating Chinese food, I decided to have one last fling with American cuisine and grab a burger in the airport. Now airports aren’t known for the best quality food, but I walked past my favorite fast-food burger place in search of something a step up. What I encountered near my departure gate was quite a surprise – a small restaurant location claiming “custom built burgers” and providing clipboards with a long checklist. I started working my way through the 4 different burger patties, 4-5 different “bun” types, 8 types of cheese, 15 sauces, and another 20-30 different toppings.
As I sat munching on my burger, I was struck by the sharp contrast between the typical fast-food ordering process (“I’ll take a number 4 combo meal”) and being able to pick out exactly what I wanted. In the strange way that my brain makes connections, I thought almost immediately of Synopsys’ coreConsultant tool. I spend most of the time here on ExpressYourself talking about various things which are specific to PCI Express, but coreConsultant is one of the coolest things Synopsys has – and it works with almost all our Interface IP . Much like the burger checklist, coreConsultant lets our customers pick exactly what they want and then generate a customized PCI Express controller with those options.
Really it’s even better than the checklist, because coreConsultant lets you try different options out. Want to know how much memory and gate count area it would “cost” to go from 32 outstanding transactions to 64? Re-run coreConsultant and find out. Want to see what kind of performance improvement you’d get from going from 128-byte max_payload_size to 256? Generate both configurations and simulate them in your SoC with your workload to find out. When I came on board at Synopsys, I was very impressed to learn about coreConsultant and just how much control my customers have over their configuration. So don’t get stuck ordering that “number 4 PCIe combo” when you could be getting exactly what you want! (…as long as it’s not a burger, because I’ve yet to find that option in coreConsultant, sadly enough)
With that thought still rattling around in my head, I took off for Shanghai to present at SNUG China.
This was my first non-USA SNUG and it was very interesting to see. Most presentations were done in Mandarin, so I confess I didn’t sit in on too many. The keynotes and a few international presentations (like mine) were in English, but they still seemed well attended and my audiences were attentive. It’s always a challenge to present in non-English-native locations, and I very much appreciate the audiences’ willingness to listen in MY language, not theirs! I had several post-presentation discussions with attendees, so it seemed like they appreciated the material. I enjoyed the keynotes as well, especially the one by Ian Ferguson from ARM – I think he even managed to make his analogies and humor fit the local setting. Anyone who left that session NOT concerned about security in IoT devices has clearly never seen a toilet in Japan!
Anyway, I’m back in the US for a little while, so chime in quickly with any future topic ideas (or just let me know if you DO want to hear about ordering rules), and as we ask in every posting, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future episodes.
I’ve been thinking for a while (yes, that explains the burning smell) that we should be covering some of the basics of PCI Express here at ExpressYourself in addition to “just” the new stuff. After reading today’s posting, please let me know in the comments whether this is a good idea or not…
One of the questions I’ve been getting a lot recently is along the lines of “How many lanes and of what ‘generation’ of PCI Express do I need?”
This is a fairly straightforward question, and while coming up with a good first-order estimation is also fairly straightforward, it’s not necessarily obvious in the PCI Express specification. Let’s start with the “raw” data rate, which is fairly easy:
PCI Express Data Rates
Folks who are new to PCIe may be scratching their heads right about now and thinking “Richard said before that each generation of PCIe has doubled the bandwidth…. so what happened between Gen2 and Gen3??!?!” That leads us to the second piece of the puzzle – the encoding scheme. The original PCI Express specification used “8b10b” encoding – which means every 8 bits of data was expanded to 10 bits when sent on the wire. I won’t go into the details here of why this was done, but it was a common technique for limiting “runs” of 0s and 1s in the data stream. When the 5Gb/s “Gen2″ data rate was developed, it kept the same encoding scheme. However, when “Gen3″ was being developed, it was hoped that by limiting the actual signaling rate to something below 10Gb/s simpler receivers could be defined (this ultimately didn’t happen, but that’s a story for another Flashback I suppose). To do that, and still keep a “doubling”, the encoding scheme for “Gen3″ was changed to 128/130 – meaning every 128 bits of data get expanded only to 130 bits (instead of to 160 as 8b10b would have).
So 5 Gigabits multiplied by 8/10 gives 4 Gigabits/second of effective data transfer, while 8 Gigabits multiplied by 128/130 gives 7.88 Gigabits/second which is close enough to double
“Ok Richard, I’ve got it – so I take the data rate, multiply by the encoding factor and I’ve got my real per-lane data rate, right?”
PCI Express Data Rates
That’s the first step, yes, but I’m afraid there’s one more piece of the puzzle – the packet efficiency. This is just a reflection of the fact that there is overhead to every packet sent on PCI Express. Firstly, every data packet includes a header which is either 3 or 4 DWORDs (32-bit or 4-byte chunks), so we add 12 or 16 bytes of overhead for that. Every data packet also includes a 1 DWORD LCRC, so add 4 more bytes for that. Then there is a sequence number and some start/stop information – for simplicity we’ll pretend that’s always another 4 bytes total. (While true for “Gen1″ and “Gen2″ the 128/130 encoding scheme makes this not exactly accurate for “Gen3″ and “Gen4″, but it will do for our purposes at the moment.) Lastly, there is an optional End-to-End CRC called the ECRC which can be included in packets as well, at a cost of another 4 bytes.
Since ECRC isn’t commonly used, let’s just look at 3 DWORD and 4 DWORD header packets and add those 20 or 24 bytes of overhead to our PCI Express packet sizes. So for 128 byte packets, we actually have to send 128+20=148 or 128+24=152 bytes, which means our packet efficiency is 128/148=0.865 or 128/152=0.842. Doing that math for the rest of the packet sizes and expressing efficiency as a percentage gives:
Efficiency (%) for Various Packet Sizes (Bytes)
So *NOW* you’ve got the calculation down! Take the “raw” data rate, multiply by the encoding factor, then by the packet efficiency to get the effective data rate per lane. Of course if you’re using a multi-lane implementation, you get to multiply that by the number of lanes.
I should also mention that generally the use of 3-DWORD vs 4-DWORD headers is tied to whether your system is addressing 32-bit or 64-bit memory. So a small client system with less than 4GB of main memory might well use 100% 3-DWORD header packets, while a huge server running I/O Virtualization might come close to 100% 4-DWORD header packets. You could just be pessimistic and assume 100% 4-DWORD headers or you could make your own assumptions. (Averaging the 3-DWORD and 4-DWORD efficiencies isn’t uncommon – which is probably where the “85%” number commonly batted around as the “PCIe efficiency” comes from: 128-byte packets with an even mix of 3-DWORD and 4-DWORD headers.)
So for an 8 lane (aka “x8″) ”Gen3″ implementation running 256-byte packets and using the more pessimistic 4-DWORD efficiency, we get: 8Gb/s * (128/130) * (0.914) * 8 = 57.6Gb/s or 7.2GB/s.
Clear as mud?
Probably needless to say, but I’ll say it anyway – if this estimation is very close to your actual bandwidth needs and if it’s critical you never fall short, then do a more detailed analysis! In real-world systems we’ve used logic analyzers on actual hardware and measured the Synopsys controller IP hitting better than 98% of these numbers but there are obviously many factors which can come into play. Contact your friendly local Synopsys Application Engineer or drop a note to me if you need help digging deeper into your own PCI Express application.
“What’s this?!?!? A blog posting from Richard? Wasn’t he killed in a fiery camel-riding crash at the last PCI-SIG Israel event or something?”
Sigh. I know, I know, I’m waaaaaaaaaaaaaaaay overdue for paying attention to the blog. Even the Synopsys folks who maintain our blog infrastructure thought I’d fallen off the face of the earth. Luckily the rumors of my demise are greatly exaggerated…
…as all of you who came out to my presentation at SNUG Silicon Valley would have realized! I was a little worried at first when one of the event organizers told me that we were set up in “the ballroom”. As soon as I got onsite I realized the room is a ballroom in name only – it’s probably only capable of holding a hundred people or so. Nonetheless, I was encouraged to see all the ExpressYourself readers had turned out in force. Ok, well, maybe not ALL of the attendees were ExpressYourself readers – but hopefully they will be by now
In any case, I went through a quick update on PCI Express 4.0 (more on that later here) and talked about some of the challenges design teams will face implementing the new 16GT/s (aka “Gen4″) signaling rate. I also spent a good bit of time talking about what we’re calling “Design For Reliability” – which is an approach to building RAS (Reliability, Availability, Serviceability) features into controllers. Enterprise-class devices have long insisted on RAS Data Protection features like memory and datapath error detection and correction. Especially with “Gen4″ rolling out to early adopters, and the industry gearing up for a new PCIe data rate, I think it’s going to be super-critical to have good debug features built in as well. I’m not sure when or if we’ll have the SNUG slides online, but those of you who are PCI-SIG members can also check out my past presentations (such as this one from Devcon 2015) for some details on the topic.
Naturally, the easiest way to get all these great RAS features *TODAY* is in a PCI Express solution from Synopsys. We know that you’re going to have to interoperate with lots of different components though, some of which might even be from other PCIe IP providers, so we think it’s worthwhile to get this information out to the whole industry. Now that we’ve educated them, look for our competitors to start touting similar features soon! Hey, aside from imitation being the sincerest form of flattery, it will be good if you have a way to definitively prove to your PCIe link partner that IT’S NOT YOUR FAULT!
Of course no discussion of PCI Express 4.0 is complete without at least one person asking “When is the spec going to be out?“ Well, that’s it, I’ve gotta run…. Sigh, no seriously, Scott is always giving me grief about this topic too. I point out that PCIe 4.0 is going to have a whole bunch of material incorporated which readers used to have to go find in things like the “Classic” PCI specification. I point out that we’ve added a few new features, and that the 0.7 draft is likely to be the most complete such revision in the history of PCI-SIG. Nobody cares, they just want a date. If I’m really unlucky, they point out that I might have said something about March in the past. Because this is a public blog, I really can’t even speculate out loud – but I can point out that the next PCI-SIG Developers Conference is coming up at the end of June.
“Surely,” I might say, “the PCI-SIG would have a new spec draft in its members’ hands for a month or two before their premiere training event!”
Oops, did I say that out loud?
Thanks again for following us here at ExpressYourself, I promise (again) to be better about blogging from here on out. Don’t forget that Scott and I are always looking for comments with any insights YOU have or topics you’d like to hear about and as always, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future episodes. Be careful on those camel rides!
P.S. No animals were harmed in the making of this blog post!
The video at ARM TechCon of our 2nd PCIe Gen4 system got kind of lost in our end of the year, Thanksgiving, Christmas, New Years, End of the 1st Quarter rush. I know that my videos of PCIe won’t win any Oscars, but one wonders if someone is just hiding this masterpiece from the public eye. Ok, ok, it’s not a masterpiece, but I’m sure folks would like to see PCIe 4.0 in action. Just for fun, see if you can find my mistakes! There are at least 5!
Of course, we have a real picture of the hardware to go with the block diagram:
The lost video you’ve been waiting for, ok maybe not waiting, but turn the lights down and have a view:
The PCIe 4.0 specification was announced on November 29th, 2011 and we are still only at the 0.5 revision of the specification. Of course, we have PCIe4.0 customers that are already designing their next generation systems using our DesignWare PCIe 4.0 controllers and PHYs. Why don’t you join us?
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
If you do try to find all my mess-ups, leave me a message and I’ll come up with a prize for the winner! Synopsys employees – go ahead and try, but no prizes for you.
Ok, Ok, I confess to a bit of a sensationalist streak [Who, me??] In truth, the world’s second PCIe Gen4 system is brought to you by the very same people who brought you the world’s first – us, Synopsys that is.
The whole “ARM beats Intel!” is true – in one particular sense very near and dear to my own heart, but you’ll have to read on for the details…
I know that when you last heard from me, I was gallivanting around Asia on the PCI-SIG Asia Pacific Developers Conference tour, but I’m back in the US. This week I’ve been at ARM TechCon 2015 with the latest iteration of Synopsys’ DesignWare IP for PCI Express 4.0 demo system.
As you may recall, the world’s first PCIe Gen4 system is comprised of a Synopsys PCIe Gen4 Root Complex talking to a Synopsys PCIe Gen4 Endpoint (both of which have passed PCI-SIG compliance testing at Gen3 by the way). I may have mentioned that our root complex uses an ARC microprocessor … which would probably NOT be very popular at an ARM conference even if we promised to leave all the squirrels at home. In order to be good guests, and because Scott and I have been wanting a demo with more future interoperability testing potential (shhhhh!), we asked (ok, more like pleaded with, badgered, and begged) the Synopsys prototyping team to accelerate the second generation Gen4 demo for us. The result is something like this:
Which turns into this when realized in hardware:
Hopefully you can tell from those pictures that the new demo uses Synopsys’ switch port IP, along with an internally-developed PCIe switch to connect a Gen4 x1 link to a Gen2 x4 host. (We used Gen2 largely to avoid the timing hassles arising from carrying Gen3 over that meter-plus cable you can see snaking around the table.) Our friends over at Teledyne LeCroy (yep, you can look and find them here too) were kind enough to loan us a PCIe Gen3 analyzer which we put on the upstream side of the switch to show that traffic was going all the way up to the host. We also showed that the Synopsys Endpoint and Switches were visible to Windows (including in Device Manager) just like any other PCIe device – because, well, they *ARE* PCIe devices.
Since this new demo was fresh from lab development, the Synopsys prototyping folks didn’t exactly trust me to put it together myself – and rightly so! Adachi-san was kind enough to come over from Synopsys Japan for the sole purpose of helping Scott and me set up and show the new demo. That’s real dedication, but you can see from the grins that it paid off - though you can probably guess which one of us is the more jet-lagged
This was my first time at ARM TechCon, so I wasn’t quite sure what to expect. One of the first things I noticed was a very large number of “EXPO PASS” badges in use, and I soon realized those were the free passes…which means in some ways EVERY day at ARM TechCon is a lot like free day at IDF so I was both guarding the giveaways, and expecting long lines for food. On the other hand, and this is where I finally confess to the true meaning of my headline “ARM beats Intel!”, the food tables at ARM TechCon were actually refreshed (several times) during the “happy hour”. So while neither ARM nor Intel has yet announced a PCIe Gen4 system, as far as I’m concerned, ARM is beating Intel in the critical “feeding show attendees” category!
Wow, it’s been QUITE the busy week here! I’m actually out at the PCI-SIG Developers Conference Asia-Pacific Tour 2015 and it’s been very much a whirlwind. It’s been 10 years since the PCI-SIG was in China, and while that trip might have been memorable for my 2.2 seconds of “fame” on Chinese TV, the China event was held in Beijing and not Shanghai, so the PCI-SIG team didn’t have any experience with this venue. That translated to my flying out Sunday morning to get to China Monday night so we’d have Tuesday to prepare for Wednesday’s show. I had a direct flight from LAX to Shanghai’s PVG on Boeing’s 787 Dreamliner. While ExpressYourself readers may recall that I’ve griped about some details on that aircraft (which seem to have been improved by this trip) I will say this – it’s a VERY quiet plane! Landing after 13 1/2 hours or so I realized “Hey, I never put my noise cancelling headphones on!” so here’s an official ExpressYourself attaboy (sorry, no cash value) to the team at Boeing!
Setup for Devcon Shanghai went fairly smoothly, with the hotel letting us start in the afternoon rather than at 10pm as we expected. Watching the banner hanger scramble up a 20-something foot high truss tower with just a couple of buddies holding the foot-square thing steady was just one of numerous “we’re not in Kansas any more“ moments!
For this Devcon, Synopsys is partnered with Teledyne LeCroy to show off PCI Express Gen4 solutions. We had “video Scott” with us in Shanghai showing off the world’s first PCI Express Gen4 system (the same demo we showed back in June at the US Devcon).
The Synopsys Verification IP (VIP) team had a field engineer onsite giving live demos of our PCI Express Gen4 VIP, and Teledyne LeCroy (they’re everywhere I look!) was showing information on their upcoming Gen4 analyzers and exercisers.
Sadly, turnout wasn’t super high (50-60 folks) for the show, but that made Nikki happy as she was able to win the drawing for a brand new iPad mini courtesy of Teledyne LeCroy and Synopsys:
With the last presentation done for the day, it was off for a quick dinner and a walk along the Bund riverwalk. My only “tourist” time in Shanghai and my camera parked safely in the hotel room where it did exactly no one any good Lots of nicely lit buildings and light displays which you’ll just have to imagine.
Thursday morning brought a cab ride to the airport and joining the line of approximately 1.2 million people heading out due to China’s “moon week” holiday. So long Shanghai! An easy few hours in a 777 over to Tokyo where it was time to do it all over again!
The Synopsys Gen4 demo hardware had been waiting in Tokyo after being shown at the recent Japan SNUG. Friday morning my Synopsys engineering-wizard Yagi-san (who’d worked miracles a couple years ago with the M-PCIe demo in the US) showed up bright and early (7am!) with the demo hardware – disassembled for travel of course. With the help of Iwasaki-san and Hasegawa-san, two of my awesome field application engineers, the demo went from a pile of parts to fully running.
As it has been in EVERY location we’ve shown it, the Gen4 demo was a big hit! Numerous attendees remarked on how impressed they were to see Gen4 running in real hardware already!
Japan has always been good to the PCI-SIG Developers Conferences – with attendees braving Tsunamis, power shortages, and occasionally flooding to show up en masse whenever we come. This trip was no different, with over 100 attendees despite some post-Tsunami flooding which disrupted the train system. Here again Synopsys and Teledyne LeCroy held a random drawing to give away an iPad mini - this time to Yoshikawa-san (who may be familiar to you from his presentations at US Devcon 2014 and 2015).
I should mention that the Synopsys guys – after re-assembling the demo in record time – came to sit in with Seki-san (of previous ExpressYourself contest fame) and some other Synopsys folks listening to my presentation. This might not sound like a big deal, until you consider that I’m somewhat famous (well infamous) for incorporating my friends into my presentations! One of the examples I use in the PCI Express overview is a telephone analogy and I think it works much better with people’s names (“I call Seki-san and ask him for 100 bytes of data from address 1000…”). They were all good sports about it - though I think Seki-san might just have enjoyed hearing the female translator calling his name over and over again
After all that, the Synopsys engineers still managed to tear down the demo and get it all packed away in under an hour! Yagi-san emphasized to me several times how important it was that I keep track of the Carnet shipping paperwork – so even after this crazy day he was trying to keep me out of trouble with customs. (It even mostly worked…) After thanking the Synopsys folks for all their help it was time to grab a night’s rest and get up Saturday morning to bid Toodle-oo to Tokyo!
Saturday’s flight was another 777, but when I walked in, I realized that there was something just a tad bit … different … about THIS airplane:
Yes, that *IS* what you think it is – at least if you think it’s a “Hello Kitty” pillow, and a “Hello Kitty” remote control, and a “Hello Kitty” safety video … and the meal was served with “Hello Kitty” wrappers on the chopsticks, and “Hello Kitty” dental flosser. There were “Hello Kitty” menus, and mints, and air-distress bags, and pretty much everything you could imagine* – including the boarding passes, luggage tags, etc!
Sorry this got to be such a long posting! I’ll save Taiwan and the explanation of “(It even mostly worked…)” for the next one! Make sure you’re subscribed to ExpressYourself and if not, click here for RSS or here for email so you don’t miss any future episodes!
Richard (from Taipei)
*In what might be an ExpressYourself first, I didn’t make up *ANY* of that!
Yes, yes, I noticed that it’s not Thursday any more, thus the title change. I feel like the IDF wrapup is somewhat anticlimactic though, so I hope you all weren’t hovering over your keyboards waiting for a grand finale.
Free day went about as expected – with hordes of interesting characters wandering around scarfing up giveaways. (The guy with the waving monkey doll on his shoulder wasn’t even the most interesting one.)
Norma ran intercept so we didn’t give away quite as many pens as I thought we would – the radius of retirement communities stocked with Synopsys pens might have decreased to 50 miles from last year’s 100 miles
With fewer “real” attendees on hand I actually had a chance to walk around the exhibit hall a bit. PCI Express storage was definitely one of the dominant themes! NVM Express (NVMe) SSDs, NVMe RAID controllers, NVMe fabric adapters, etc… I didn’t see any NVMe toothbrushes, but that might only be because I didn’t get to every booth! All the NVMe folks I talked to were eager to see PCIe 4.0 come out soon, but there was a lot of mention of “the elephant in the room” – namely that with no PCIe 4.0 “Gen4″ platforms, designers would have a tough time validating their designs. Imagine my surprise then when I returned to the booth and found this guy getting a demo! (I think his shirt might have said “Gen4″ there where it’s folded up, but maybe that’s just wishful thinking…)
Show hours were only 11-2 which was good because my voice was starting to give out from all the Gen4 demo spiels I gave this week. (This should actually be the best indicator of how many attendees found the demo interesting, because I can just picture a good half of you exclaiming “What? They wore Richard down to silence?!?!?!?“) Teardown was uneventful – I’m happy to say there was no emergency room visit this year! Scott and I spent quite a while poring over the demo takedown and repacking trying to figure out how Torrey had gotten everything into one packing case.
We managed to cram both cases into Scott’s trunk and he kindly gave me a lift to the San Francisco airport – a good deed which apparently did NOT go unpunished as he got stuck in one of California’s famous traffic jams* on his way from there home.
So our takeaways from IDF 2015 are:
PCI Express storage, and NVMe in particular, are clearly dominating the direct-attach storage market
Despite any elephants (whether in hotel rooms or board rooms), there is a steadily building demand for PCIe 4.0′s 16GT/s “Gen4″ data rate
Synopsys is able to deliver working 16GT/s “Gen4″ solutions right now, so you can join the ranks of designers building their PCIe 4.0 products as the spec works its way to completion
Richard’s voice really is finite, and he should take a taxi to the airport next year
Thanks for following us here at ExpressYourself and please feel free to leave us comments with any insights YOU had at IDF. If you’re reading this forwarded from a friend (or enemy I suppose) or if your email swap to Outlook365 broke your subscription, or you just have been putting it off for too long, please subscribe to ExpressYourself by clicking here for RSS or here for email so you don’t miss any future episodes.
*I wish I’d made that part up, hopefully Mrs. Scott will forgive us for messing up their plans!
All rightee then – I’m glad to say the Live Blog format got a reaction :D Oddly enough it was a mixed reaction – with some folks being all over it, and others thinking it was over the top… I know, who would have thought *I* would be over the top????
Today was a bit less hectic than yesterday, though I’m going to be honest and say that it started out a bit oddly. I’d noticed this strange box in my room when I first checked in:
You might recall that I was a bit disoriented yesterday anyway, so I didn’t pay much attention to the box, and I didn’t want a train running through my room so I left the thing safely off.
Housekeeping must have changed the setting from “Train” to “Meadow” without my noticing though, because when I woke up this morning, things had changed!
Needless to say I fled my room, met Scott for breakfast and headed in to set up the demo again (we’ve been shutting it down each night to be safe). After a bit of begging and pleading, and a few reboots, the demo came back up. Show hours were reduced today – *only* 11-1 and 4-7, so we got a break.
I was again surprised and pleased at how many folks came by to see the PCIe 4.0 demo! Lots of interest from SSD developers, several more system manufacturers, and a few folks representing other market spaces. It’s *VERY* clear that anyone discounting PCIe 16GT/s for I/O does so at their own peril! These guys want the bandwidth and they’re not happy about waiting for it! Luckily for them, Synopsys has a complete range of PCI Express controllers already delivering to customers. I keep pointing out that in most cases, the hardest part of a PCIe 4.0 migration isn’t our (Synopsys’) part, but the customer’s logic needing to expand its internal bandwidth. For some folks that’s a wider datapath, for others a faster one, but it usually has implications throughout their SoC. By beginning design work right NOW with Synopsys’ draft 0.5 controller logic, SoC designers can focus on their jobs while we worry about tracking the PCI Express 4.0 specification – and dealing with any wild animals which show up uninvited!
By the way, I want to give a HUGE shout out to the PCI-SIG folks who were holding press briefings today. Several press representatives showed up at the booth saying they’d heard about us at the PCI-SIG briefing and wanted to see the demo! (I shouldn’t have to say it, but anyone reading this who is interested in doing articles or other publications on PCI Express should certainly contact Scott and/or me if they need material!)
Food at the show was pretty disorganized again today – quantities seemed to be improved, but an informal survey showed booth staff across the board missing out on the hot hors d’oeuvres. No amount of searching, begging, or pleading was able to net me a non-diet Dr. Pepper either. Once the show closed though, Scott and I were able to snag a surprisingly excellent pizza over at Jersey pizza. I say surprising only because I am a HUGE fan of Chicago-style pizza – but perhaps aided by hunger, we both thought this was very good pizza.
IDF has had some sort of concert the last few years – which I generally skip due to exhaustion, but Scott convinced me to go over for a few minutes. I quickly learned that there’s a huge difference in audience participation between a technical presentation and a rock concert. Isaac Slade got a *MUCH* different reaction from the crowd when he strolled through during his “presentation” than I have when I’ve done the same in mine! This is particularly amusing and relevant as today I ran across Ajay Bhatt (dubbed the father of PCI Express by many back in the day) and subject of the world’s most embarrassing TV commercial (oh heck no, that’s not really Ajay in the commercial).
Tomorrow is free day and therefore I expect to go through MANY more pens, so I’d better sign off and get some sleep!
Stay tuned for the final installation of IOT coming tomorrow…
I swear “IoT” must be the most overused term of 2015, so I’m coopting it in protest – though I’ll change the capitalization out of sheer orneriness
At least for the next few days, I shall use “IOT” for my “IDF Of Today” report. I’ll be honest, I a) couldn’t figure out HOW to “live blog” on this system and b) couldn’t keep a good internet connection so you’re spared from my play-by-play… which today would have gone something like this:
10:30 Showed PCIe 4.0 demo to folks from a big-name storage company.
11:00 Show opened
11:01 Gave away first Synopsys pen to a member of one of the local retirement communities.
11:15 Showed PCIe 4.0 demo to folks from a big-name server company.
11:30 Ate boxed lunch (“beef” – although it engaged in a spirited debate with me on whether it was from a cow or not)
11:35 Promised Synopsys pen to gentleman with “Media” badge if he’d come by the booth.
12:20 Showed PCIe 4.0 demo to folks from a big server company whose name doesn’t rhyme with much of anything.
13:30 Showed PCIe 4.0 demo to engineers from a high-performance SSD manufacturer.
13:45 Showed PCIe 4.0 demo to fellow from a controller company specializing in high-bandwidth storage fabrics.
14:00 Showed PCIe 4.0 demo to marketing manager from a new startup SSD company.
14:45 Showed PCIe 4.0 demo to someone from a company which sells PCIe PHYs. Managed to refrain from asking such rude questions as “How can you claim to make a PCIe PHY when you’re not even a member of PCI-SIG?” and “Can you even spell ‘compliance’?” Inadvertently tripped young woman in stiletto heels (which would be classified by TSA as deadly weapons*) while patting self on the back for professionalism.
15:00 Roamed show floor in search of snacks while Scott manned the booth. Returned to booth empty-handed and ate a Synopsys mint.
16:00 Beer bar setup about 8 feet away from Synopsys booth. Barman deluged with attendees asking for beer – told to come back at 16:15.
16:15:01 Growing line of beer patrons told beer bar would open 16:30.
16:30 Beer line begins. Attendees quickly tire of my offer to “Buy you a beer if you’ll listen to me talk about PCIe 4.0!” (No takers for the record.)
16:35 Scott brings by a pretzel – shares half with me. We bemoan lack of salt on pretzel and lack of mustard. Spend several minutes sketching out new DesignWare IP for Pretzel Twisting, decide the TAM is too low and scrap the idea.
16:40 Scott kicks me out of the booth to quell my grumbling stomach - which is apparently disturbing the line of attendees for beer.
16:44 I’m informed by the hot food servers that hot food will be available at 17:00.
17:00 Hot food station opens
17:00:15 Hot food line is confirmed by a fainting-from-hunger Steven Hawking** to be “longer than the event horizon of a black hole”.
17:10 End of hot food line is finally visible with naked eye. I get in line only to see the serving station being wheeled away. My tears of frustration move a hot food server to suggest I get in line for the Risotto “before the milk curdles”***
17:20 Gentleman with “Media” badge comes by looking for promised pen – puts up with my PCIe 4.0 demo and asks reasonable questions. I give him the secret “upgraded” pen *AND* a Synopsys “these are not the ‘droids you’re looking for” USB stick. (You too can get one of these if you come by the booth and tell us you read the blog – of course you’ll have to listen to the demo spiel first.)
17:30 I go get in line for ice cream sundaes. One poor server is valiantly struggling to serve two lines of attendees.
17:40 I reach front of ice cream line just as ice cream scoop breaks. Overworked server runs away to replace scoop, angry murmuring begins among attendees in line. New server arrives with scoop, I choose ice cream flavors which are less likely to break scoop (after loudly calling for an engineer to repair same).
17:45 I share ice cream with Scott and Norma – to the envy of staff of nearby booths (one of whom allegedly fainted from hunger while trying to reach front of Risotto line).
18:00 Show PCIe 4.0 demo to another media member, we talk about likely spec timelines and various factors affecting the spec adoption.
18:15 With all food apparently gone, attendance drops significantly. Booth staff now appear to massively outnumber attendees – perhaps a dozen of whom now roam the show floor relentlessly bombarded with demo offers and freebies.
18:59 Gave away 87th Synopsys pen to a member of one of the local retirement communities.
19:00 Show closes.
19:10 Demo shutdown, booth closed up – I walk over to Super Duper Burgers for a Super Burger with cheese & bacon, fries, and a vanilla shake.
Stay tuned for tomorrow’s exciting episode of IOT…
P.S. So the takeaways from today are: 1) a *LOT* of folks are excited to see that PCIe 4.0 is really truly alive and running, 2) Either IDF got a MUCH smaller food budget this year, or a LOT more attendees than they planned!
*Ok, I made up the part about tripping someone – but the stiletto heels *DEFINITELY* would have been ruled deadly weapons by TSA, and I’m willing to take bets on this bit!
**I made that up, no physicists were harmed in the making of this blog posting.
***Yeah, yeah, I made that up too – no milk was harmed in the making of this blog posting. (I’m pretty sure I really did guilt-trip the server though.)