This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
About the Author
Scott KnowltonI started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard.
I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.
Yes, yes, I know that I’ve been saying for months that we’d see the next draft (0.5) of PCIe 4.0 “soon”. Yes, I know that “soon” is not usually considered “3-4 months” – but in my defense, remember that we’re talking about standards here…. and hitting the same year as originally promised is often considered above-average performance
Because this is a public blog and open to non-PCI-SIG members I can’t go very deeply into the details of what’s in draft 0.5, but I can suggest that everyone download it. Pay particular attention to the first page “Open Issues” and “Anticipated changes that reviewers should be aware of”. None of these should be particularly surprising (and I’ve talked about some of them at PCI-SIG Devcon before) but they’re good heads-up items. Of course most of the changes are in Chapter 4 (PHY Logical) and Chapter 9 (Electrical) – though I’ll note that the electrical chapter doesn’t yet include results from the two PHY test vehicles (here’s a hint as to their identities – they demonstrated interoperability at PCI-SIG Israel last month). To save you some trouble finding the downloads (especially if you happen to be reading this after the review period closes), here are the links for the changebar and non-changebar versions. Both the protocol and electrical workgroups would very much like your feedback, so please do take some time to go through this draft and return comments before May 11. If you have opinions on those Open Issues (and here’s a hint – you should!) then I especially encourage you to provide feedback.
For those of you attending the upcoming PCI-SIG Compliance Workshop (#93) the week of April 21-24, I expect to be around the first couple of days so feel free to track me down and say “Hi”. Hmmm, maybe I should come up with a special prize for the first ExpressYourself reader to find me onsite and tell me the altitude shown on my GPS picture from last month’s posting.
Speaking of upcoming events, I hope everyone here has the US Devcon dates marked on their calendar! (That’s June 23-24, still at the Santa Clara convention center.) I’ve heard from a few of the workgroup chairs that they have more new PCIe 4.0 information to present, so there should be a lot more than just electrical “stuff” on the PCIe 4.0 front this year. Of course this is open only to employees of PCI-SIG member companies, but a) if you’re doing any kind of PCI Express development you really SHOULD be a PCI-SIG member and b) people have been known to join PCI-SIG just to hear my jokes during the presentations*. While I recognize that not too many of our non-US readers get the opportunity to come to US Devcon, please keep an eye on the PCI-SIG Events page – I think folks in Asia will be very happy this October! For those in Europe looking for a local event, especially if you missed the Israel Devcon, my best advice is to email PCI-SIG administration (yes there’s a real email address, yes you already have it, but NO I won’t post it here for joyful consumption by SPAMbots) and request one. (I suggest offering to bring 100 of your closest friends.)
As always, thanks for following us here at ExpressYourself and please feel free to leave us comments on what you think of Draft 0.5 (of course send detail feedback to PCI-SIG, but tell us how you really feel). If for some crazy reason you haven’t already done so, please click here to subscribe to ExpressYourself so you don’t miss anything.
*Ok, so that’s an obvious lie :) On the other hand, I promise a very special gift to the first person who can prove their company newly joined PCI-SIG and put “We want to hear Richard’s jokes at Devcon” down on the application!
Well, we’re back from the PCI-SIG Developers Conference Israel 2015 and by now, between Scott and me we might make up one coherent person! (I know, given the blog frequency lately, you probably thought Scott and I had been kidnapped by aliens. I have no comment on that beyond “We’re back!“) This was the third Israel DevCon and as always I was pleased with the fantastic turnout. I mean, it’s a hardship going to Israel, but somehow we tough it out…
Oh wait, did I forget to mention that Tel Aviv is on the Mediterranean?
Unfortunately the weather was that gorgeous most of the time – that we were inside working. Admittedly, most of the PCI-SIG presentations were from the US Devcon, but it’s always much more interesting and useful to hear and see the material presented than to just read the slides. As usual it fell to me to try and wake up the early arrivals with PCI Express Basics & Background, as well as break the post-lunch lethargy with PCIe 3.1 Protocol. Perhaps reinforcing my point about live presentations, one of the attendees commented (about the Basics) “I’ve seen you give this same presentation 2 or 3 times now, but I learn something new each time!” On the second day I got to take off my PCI-SIG hat and put on my (metaphorical) Synopsys hat to talk about PCI Express Controller Design Challenges at 16GT/s. In between sessions over breaks and mealtimes, we manned the booth. Well, in truth, mostly our colleague Robert manned the booth as he got to show off our joint 16GT/s “Gen4″ demo with Mellanox! Meanwhile Scott and I practiced looking pretty and showed our “Gen4″ controller demo to folks waiting to talk to Robert. Yep, you read that right, Synopsys and Mellanox were both showing 16GT/s PCIe PHYs communicating with each other over some pretty nasty test channels!
Yeah, yeah, I know you can’t see much of the demo – I never claimed to be a photographer! Scott did a little better, but it’s hard when you’re overrun with interested attendees – and I’m told it’s bad marketing to push your customers out of the way to take pictures.
To answer a few question I know folks will be asking:
Yes, they’re two completely independent designs. Both companies participate actively in the PCI-SIG and we’ve both been pretty open about what we’re doing, so it was a pretty obvious partnership opportunity as we both looked to demonstrate our individual PHYs at the DevCon. (Mellanox in fact submitted their complete characterization as part of the PCIe 4.0 specification development – see their presentation for more details.)
No, of course we can’t claim compliance to PCIe 4.0 as it’s not final yet. Naturally, the spec numbers are based in part on the characterization results of test silicon, so…
“Ok then, what’s the bit about the Dead Sea?”
Well, I was looking for a catchy blog title (as I always do) and if truth be told, I thought of the Dead Sea first – then worked in the Live Wires… All that because Scott and I did end up with a little free time (Shhh, don’t tell management!) and took a tour out to Masada and down to the Dead Sea. Being the data geek that I am, of course I had to bring along my GPS – well, ok, so I logged the entire trip on my GPS. For your amusement I present this:
Yep, that’s correct: 1281 feet *BELOW* sea level (some 400 meters for you metric folks). I know, even I can’t come up with a way this relates to PCI Express, but I’m sorry – that’s just cool! Especially for someone from Colorado who hangs out at around 6500 feet most of the time. (Colorado’s unofficial motto is “Never trust anyone under 14,000 feet”) I also have no excuse to work in any pictures from Masada – unless you leave a comment telling me of a way that connects to PCIe – so you’ll have to get those from me next time you see me in person. Hey now, that I can connect to PCI-SIG – make sure to mark June 23-24 on your calendars- at least the US folks and anyone else who can talk their management into a trip approval!
Well that’s it for now – I’ve got to go clean what’s either Dead Sea slime or some kind of alien excretion off my old tennis shoes. Please do leave a comment with topic ideas so we can blog more often, and if you aren’t already, then click here to subscribe to ExpressYourself – quick before the aliens come back!
When all through the house, not a creature was stirring, not even a…
Ok, so that’s probably NOT the kind of mouse Mr. Moore intended (well, sure, in 1822 it couldn’t have been – unless you buy into Erich von Däniken’s theories) but it seemed appropriate both for the date and for my finally getting around to addressing the cabling comments posted by user Porthem. S/he posted quite a lot, so I’ll exercise a little editorial license and copy in just pieces of the key questions.
“Will USB-C be viable to become the standard INTERNAL storage connector?
Currently, a big special SATA Express connector is used to connect internal disks to motherboards, and USB is used to connect consumer-level external disks to systems.
The new USB-C Alt Mode feature is going to enable using PCIe directly (via simple multiplexer, not via protocol encapsulation as in Thunderbolt) through the USB-C port as an alternative to using the USB protocol, via 4 signaling pairs each capable of 10Gbps. In other words, it will be like OCuLink, but unlike the latter, USB-C will soon be ubiquitous.“
Let me address those in pretty much reverse order…
Ouch, I can’t completely argue with the OCuLink statement as it rarely pays to bet against USB ubiquity, but I think OCuLink still offers some advantages (which I’ll try and bring out as we go).
Yes, the USB Type-C spec does offer “Alternate Modes” but with a few caveats. First, there are indeed 4 high-speed signaling pairs, but they are currently defined as two TX pairs and two RX pairs – so this is the functional equivalent of a PCIe x2 link. Even if one hypothesized an asymmetric setup, it would be at most 3 TX + 1 RX or vice-versa, which is still shy of the PCIe x4 link (4 TX + 4 RX) offered in the M.2 form-factor. Today’s NAND-flash SSDs can easily exceed the 2GB/s/direction that a PCIe 3.0 8GT/s x2 link provides, so most of them are designing their controllers to support x4 links. OCuLink as currently specified (still in draft form admittedly) supports a x4 link with some possibility of extension to x8 by the time the spec is final. OCuLink is also forward-looking to the 16GT/s “Gen4″ PCIe spec, and I fear USB cables are primarily selected for their cost, so I don’t expect a lot of headroom atop that 10Gb support!
The USB Type-C spec also requires implementation of USB (at least 2.0) in anything with a Type-C connection. Entering Alternate Mode requires exchanging USB power delivery messages, so one needs at least some chunk of a USB controller to even get the Type-C into an alternate mode and really a full one to comply with the USB requirement. Porthem also said:
“Since even consumer-level external disks will soon use USB-C (with the USB protocol), it seems feasible that for a marginal increase in cost, they could add support for PCIe, since no change of connector or cabling will be required.“
To Porthem‘s points, yes, today you get the SATA or SATA Express connectors which certainly are larger and bulkier due to their legacy compatibility. The thing is though that most consumer-level disks are still round – by which I mean they’re rotating magnetic media. The magnetic disk manufacturers Scott & I talk to are pretty happy with 6G SATA today and not looking to change to PCIe (or anything else) any time soon. Furthermore, USB-SATA bridges are so cheap these days that every USB external drive I’ve ever cracked open had one connected right up to a SATA drive – even when the end-user price of the external drive was less than the internal one! I don’t think the Type-C overhead will add much cost beyond the connector (which would of course be the same adder to a native solution) so I don’t see these bridges becoming a stumbling block any more than they were in the USB 2.0 to 3.0 transition. In fact, they serve to isolate the drive manufacturer from the 3.0 to 3.0/Type-C transition.
The consumer (magnetic) disk drive market is so price-sensitive that changing connectors and adding the extra logic for USB may not make sense. Perhaps it would if the manufacturer would actually implement both their USB and SATA controllers in the same silicon and build a single PCB with both legacy and Type-C connectors on it. Anything short of that though seems like extra cost that market just doesn’t want. If the volumes of external drives don’t justify “dedicated” USB versions, it’s hard to see how they would justify these “unified” USB/SATA/PCIe versions – when change itself costs money.
I don’t claim to have the world’s best crystal ball, but in summary, to me it seems that USB Type-C doesn’t offer enough bandwidth to support “square” (solid-state) drives and adds cost for little concrete benefit to “round” (rotating magnetic) drives, therefore…
What’s that you say?
“Richard, your crystal ball is really a Magic 8 Ball!”
Yes, but I’d argue it beats Wall Street on most days
As I mentioned last time, I believe Synopsys IT now has commenting fixed, so you too have nothing to dread as you read this blog post all snug in your bed with visions of sugar-PCIe dancing in your head… Ok, Ok, I’ll stop. Please do chime in with your thoughts and/or future column topic requests and make sure to click here to subscribe to ExpressYourself.
Yes, yes, I *know* that Halloween was weeks ago… Would you believe that I’ve been planning this post since *BEFORE* Halloween? You should, since I said way back in March that we were expecting PCI Express 3.1 to release “soon”.
Don’t worry, it’s not April Fool’s Day - so yes, in case you were wondering, the PCI Express 3.1 release is the “treat” part – PCI-SIG members can download it right now:
(that’s the “normal” version without changebars – if you really want the changebar version it’s here.) There shouldn’t be anything really surprising in this release as it’s mostly a rollup of ECNs which have been released since 3.0 came out. Here’s a short list of the major ECNs which got included:
Downstream Port containment (DPC) and Enhanced (eDPC) version
Separate Refclk Independent SSC (SRIS) Architecture including a later change to JTOL and SSC Profiles
Process Address Space ID (PASID)
Lightweight Notification (LN)
Precision Time Measurement (PTM)
Readiness Notifications (RN)
L1 PM Substates with CLKREQ (L1SS)
(In case you were wondering, yes, Synopsys PCI Express Controller and PHY IP is compatible with the new PCIe 3.1 spec – check out http://www.synopsys.com/pcie for full details.)
Scott and I have talked about a number of these ECNs before, and I’ve presented on a lot of them at various PCI-SIG Training Days and Developers Conferences. Which reminds me that I’m terribly remiss in reporting on several events
That segues rather well into the “trick” part of this posting. As long as we’ve been blogging, Scott and I have been asking folks to comment on our postings and saying we would respond. Almost all we ever got were SPAMbot replies – offering us a wide range of personal care or enhancement products, get-rich-quick-schemes, or links to the bot’s website with only the very occasional real comment mixed in among the chaff. Like most blogs, ours emails us when a comment is received so we can moderate it and either approve it for publication or not. Synopsys moved the blog platform over to a new system in June 2014 and our SPAM level went way down – in fact down to zero. (You can probably guess where this is going…)
Last week I happened to log into the portion of our blog dashboard which lists comments waiting for moderation and to my great surprise I found it chock full of them. 99% of those were SPAMbots, but I found *TWO* real comments! After getting over my shock, my next reaction was “September?!?!? October?!?!?!? Why didn’t I get emailed about these?” I checked with Scott and he confirmed that he hadn’t gotten email either. To make a long story short, as a result of this, Synopsys IT fixed a problem on the new blog platform which was preventing email from leaving the servers.
Now in the interest of full disclosure, I must confess that one of those comments (from September) was from our co-worker Mick of Breaking the Three Laws fame inquiring about a “cyborg display panel attack”* which I’ll address in a postscript. The other was actually a very detailed question about PCI Express cabling and how it might play out in the market, posted by a user going by Porthem. Given that I’ve only just now gotten that comment, I’d like to respond in a later posting, but I wanted to assure Mr/Ms Porthem that s/he was NOT ignored … just hidden behind some technical difficulties.
So now that comments should ACTUALLY be working, feel free to test us by responding in the comment field below, and as always, please don’t neglect clicking here to subscribe to ExpressYourself.
*Mick’s actual comment was “I’m told you have an amazing story from IDF which includes a cyborg display panel jumping out and attacking and you bravely fighting it off.“ Mick reminds me I didn’t report much on IDF this year, and truth be told there wasn’t as much PCIe “stuff” to talk about, but I did actually manage to injure myself there :( While tearing down the booth, I “helped” disassemble a literature stand and in doing so, smacked myself in the face with what is essentially the edge of a large metal object. Some possibly-not-very-nice-language ensued along with some surprisingly profuse bleeding and a short cab ride to an urgent care facility not far from the Moscone Center. In the end, no real harm done, and my face STILL won’t be on the cover of Vogue any time soon :)
Frankly, I like Mick’s version of the event much better, so let’s just agree to go with the cyborg display panel attack shall we? Great, thanks!
Now that my kids are back to school, things are calming down slightly. Well, ok, the chaos is shifting gears :) I’m still recovering from IDF last week, and I owe you all a blog post about that, but I’ve been remiss in advising you of how you too can get “back to school” … with an upcoming Webinar on challenges you’ll face in PCI Express 4.0 design.
This Tuesday (16-September) at 11am Pacific, I’ll be talking through some key things PCIe 4.0 designers will need to know. There’s been a lot of talk about the PHY and electrical side of the upcoming specification, so I’ll mostly be focused on the controller side.
Here’s a quick teaser on the topics:
How the specification recommends handling re-drivers and retimers
Design changes to consider to handle new specifications on link equalization and the PHY interface
How multiple packets per clock cycle will affect designs using PCIe 4.0
Questions to ask for effective implementation of 16GT/s
So if you’re not too busy tomorrow (yes, I know, short notice!) please signup and follow along:
Sorry for the short notice (and short posting) – I’ll make it up to you with another “contest” perhaps. Note that I only had 2 winners last time, so your odds are excellent. Of course, the prizes might leave a little to be desired
All right, no monkeying around this year, I promise (mostly) not to make any IDFvs IDF jokes – mainly because nobody even tried to answer last year’s quiz question. (On that note, Scott and I had a quiz internally this spring for our field folks to see if they’d been following the blog… Let’s just say the results were NOT gratifying!)
Once again, Scott and I will be manning the Synopsys PCIe booth (#655 – which doesn’t spell anything interesting in telephone code), showing off all the cool “Gen4″ PCIe IP we have. Very much like a carnival midway you’ll be able to come by and look at scary eye diagrams from the Synopsys 16G PHY, run your very own simulation of a PCI Express link at 16GT/s, and compete in contests of strength to win fabulous prizes. Ok, Ok, I made that last one up.
IDF actually is a neat show because you get to see a lot more of the end products that PCI Express is used in. From what Scott and I are seeing, there’s no real sign of this trend slowing down. In fact, we’ve really been inundated with PCI Express in mobile applications this year, with a lot of folks trying to do very low power implementations so I’ll be interested to see how that translates onto the show floor. Of course, I’d bet good money that there’ll be a processor company around showing a few new CPUs, probably some related to internet-connected household items, etc, etc, etc.
Oh geez, stop bawling, please, no really, stop it, you’re embarrassing yourself. Look, I’ll tell you what – drop me a note, or leave your email for me in comments and I’ll give you a free pass. Yes, I’m completely serious – Synopsys got a bunch of free passes (only good on Thursday and only for the Showcase from 11am to 2pm, but that’s where I’ll be) so you can go online and register with the code** I’ll give you and you get in for completely and absolutely free. I won’t even make you help me tear down the booth afterwards!
I hope to see lots of you out at IDF, be sure to come by booth 655 and tell us how much you like the blog – or at least go by booth 773 and tell them how much funnier the other Synopsys blog is. :) Please leave your code request or code guess in the comments below, and as always, please don’t neglect clicking here to subscribe to ExpressYourself.
**If you want to try and figure out the code for yourself, here’s a clue – it’s the concatenation of the initials of a religious school in my town whose mascot is the Lions and the mnemonic for the Z80 opcode 0×00. Even if you don’t want to use the code to register, leave a comment or email me if you figure it out on your own and you’ll win 2nd prize.
UPDATE 2014-08-28: Perhaps I made the clues too easy, or perhaps ExpressYourself readers just really are that much smarter than average, but Seki-san e-mailed me with the correct code 3.5 hours after this posted! I’m willing to give out more 2nd prizes though, so don’t give up :) -Richard
For those of you that didn’t get to see our demos at PCI-SIG DevCon, you can view these new summer blockbusters featuring the latest videos with your favorite Synopsys PCI Express Controller and PHY IP. These videos are rated two thumbs up by Scott and Richard!
If interested in the May 22nd launch of the Synopsys PCI Express solution for PCIe 4.0 before the PCI-SIG DevCon in June you can review the press release here.
On to our featured PCIe Gen4 videos, our first summer blockbuster “Industry First: PCI Express 4.0 Controller IP” features one of our PCIe Controller developers, Paul Cassidy, demoing the Synopsys PCIe 4.0 controllers. He is using coreConsultant, our GUI interface, to configure our PCIe 4.0 core to support Gen4 with 16 lanes, showing other configuration options and showing simulation results in conjunction with our PCIe 4.0 VIP. The PCIe 4.0 controllers are Rated G for Generally available!
Next in our summer blockbuster series on PCIe Gen4 is “DesignWare PHY IP for PCI Express at 16Gb/s” featuring Synopsys’ very own Rita Horner, the TMM for PCIe PHYs, showcasing our latest PHYs running at 16Gb/s in preparation for Gen4. Using a Teledyne LeCroy scope, she shows the eye diagram and other PHY related information.
If you looking for something more nostalgic like PCIe Gen3, the star of our next summer blockbuster is Synopsys’ Gen3 28nm PHY and market leading PCI Express controller in the action movie: “PCI PHY and Controller IP for PCI Express 3.0”. Our PCIe 3.0 controllers are used in over a 150 designs and presented by Torrey Lewis, R&D for PCIe Controllers and Rita Horner, the TMM for PHYs. This demo runs a lot of traffic between a PC’s system memory and our PCIe Endpoint to show the throughput of the PCIe interface. We are also using a Teledyne LeCroy logic analyzer to display the different packets going through the system. The movie went for a G rating for Generally available, but the performance of the IP pushed the rating to an R as the IP Raced through all the performance tests!
If you’re looking for power savings while maintaining the PCIe protocol, M-PCIe is showcased in “Synopsys M-PCIe Protocol Analysis with Teledyne LeCroy”. John Wiedemeier, from Teledyne LeCroy, is using their new M-PCIe Protocol Analyzer attached to the Synopsys M-PCIe Controller and Gear3 M-PHY demo. It is important as new technologies are launched to work within the ecosystem to make sure that you can talk to other products using the protocol. The Synopsys M-PCIe controllers and M-PHY IP are Rated G for Generally available!
Just in case you needed something else to go with your movies, how about some good ol’ FPGA prototyping? Mick’s Posner’s Blog “Breaking the Three Laws” had a recent posting showcasing my PCIe market data and showcasing the Synopsys PCIe 3.0 Controllers running in the Synopsys HAPS DX prototyping systems available with the new IP Prototyping Kits. If you’ve ever tried to prototype high speed device in and FPGA, then you know this can be challenging. Using the IP Prototyping Kits, this is made easy for you. If interested, you can read Mick’s Blog here.
I hope you enjoy our videos. I understand that red wine is a great accompaniment while watching
For more information on the Synopsys PCIe solutions, please visit our web site.
Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.
Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.
Wow, the last weeks have been just crazy crazy! Luckily Scott’s been on top of the blog for the last month or so, or you might have thought we’d dropped off the face of the earth. Actually, May was very hectic for me – I don’t think I had more than 36 hours straight at home for the last few weeks of the month. Scott and I visited some customers out in Texas, then there was the semi-annual Synopsys FAE training, and finally (lo-and-behold) I took an actual vacation! Squeezing in a week in Europe between FAE training and Devcon seemed like a good idea when I scheduled it, but Murphy’s Law came into play on my return. My 12-hour layover at home turned into arriving the next morning, changing suitcases and catching a late afternoon flight 4hrs after I arrived! All for you dear readers, all so I could make it to the Developers Conference.
Yes, actually those ARE purple PCI-SIG M&Ms… This year we (and by “we” I actually mean “Ruth”) wanted to do something a bit different for the speaker gifts, so in addition to fame, fortune, and seeing your name in genuine electrons, all the speakers at the PCI-SIG Developers Conference 2014 got a collector’s edition bag of purple PCI-SIG M&Ms! (Take that, IDF!) I actually quite liked the sentiment and felt it was appropriate for you blog readers, so I snapped the picture above. (Sorry, no I won’t be sending you M&Ms because I ate them all. Well, I shared them with my family and WE ate them all. I’ll make you a deal though, leave a legitimate and insightful comment and I’ll put together a care package for the first qualifying* respondent.)
Turn out was again record-setting for the second year in a row! (We beat last year by something like 5 people, but hey, a record is a record.) I’m particularly grateful for all of you who came to listen to me talk about PCI Express Controller Design Challenges at 16GT/s. Not just for putting up with my quickly fading voice (day 2 folks know it was pretty much gone by then) but also for the literally standing-room only crowd! I think that room was set for 75-80 people and we had well over 100 in attendance.
As always, the days were chock-full of great information on PCI Express, tasty snacks, and good company (I mean “networking”). It’s impressive how many companies are hiring for PCI Express expertise, and I personally introduced more than a few folks on both sides of that table. The acquisition of my former employer has left a number of good PCIe people (in design, verification, and customer support) looking for new “homes”. So if your company happens to need people, drop me a note!
Synopsys had a cool new booth design this year, and I know many of you were attracted (not in a Bug’s Life way I hope) to the displays and demos – particularly the 16G PCIe PHY and controller demos!
Speaking of demos, I have to give a huge shout out to Paul from our Dublin R&D office, who not only made the trip out to help get the controller demo going, but improved it by about 300% while I was fighting airline problems on Monday – and then found himself dragooned into doing the demo video when my presentation schedule and voice didn’t cooperate with our video crew. (I noticed the ladies all liked Paul’s accent too, maybe that’s why they weren’t sad when he replaced me!)
I’m sure I’ve forgotten more important things from my blogging hiatus, but I’m back now and I’ll try and keep you both informed and entertained … next month.
Thanks again for reading ExpressYourself and if you only found this by googling “PCI-SIG Developers Conference 2014 M&Ms” then please, by all the candy-coated goodness in this world, click here to subscribe to this blog! Feel free (unless you’re a SPAMbot of course) to leave a comment on any PCI Express topic(s) you’d like to read about in a future blog posting.
*Synopsys employees and family members are not eligible for the care package! Decision of the judge(s) is final in matters of insight and legitimacy. Your mileage may vary. Professional driver, closed course, do not emulate.
Hmm, why is “pci-sig developers conference 2014″ not the same as “PCI-SIG Developers Conference 2014″ to google?
For those of you coming to the PCI-SIG DevCon, you should stop by and visit the Synopsys booth (Booth 8 ) to learn about our high-quality, silicon-proven DesignWare IP portfolio for PCI Express, which includes controllers, PHYs and verification IP. See how our robust IP development methodology, extensive investment in quality, IP prototyping, software development, and comprehensive technical support enables designers to accelerate time-to-market and reduce integration risk.
In the Synopsys booth, we will have demos specifically targeted for our new PCI Express 4.0 products. If you stop by a watch a few of them, we will be giving away an iPad Mini! You can choose from:
DesignWare Controller IP for PCI Express 4.0
DesignWare PHY & Controller IP for PCI Express 3.0
DesignWare PHY IP for PCI Express at 16 Gb/s
Synopsys Next Generation Verification IP for PCI Express
You can also talk to our resident experts that will be in the booth or see them present in the technical sessions.
Synopsys Technical Presentations
PCI Express Controller Design Challenges at 16GT/s
PCI-SIG announced that the next generation of the PCI Express specification will move the maximum data rate from 8GT/s to 16GT/s. While most attention is initially focused on the high-speed SERDES design to achieve 16GT/s, there are substantial implications and challenges for designing the PCIe controller and the application logic to support these data rates. This presentation will offer an in-depth review of the critical design changes and challenges to the controller and application logic design to support the new bandwidth and traffic flow, PHY interface, and clock frequency. Designers and architects considering incorporating 16GT/s PCI Express functionality in their upcoming designs will benefit from attending, particularly those moving from a previous generation of PCI Express.
Presenter: Richard Solomon, Technical Marketing Manager, Synopsys Date/Time: Wed., June 4, 3:30-4:30 p.m.
Challenges and Benefits of SRIS in PCI Express Systems
Separate Refclk Independent Spread (SRIS) is a new usage model that allows PCIe links to exist outside the box, especially for high data rate PCIe 3.0 (8 Gbps) and upcoming PCIe 4.0 (16 Gbps) systems. SRIS will be used in chassis-to-chassis interconnect in high-end networking systems. This presentation will cover the challenges and benefits of integrating SRIS, including penalties for not sending the Refclk, jitter and EMI implications, and how other standards have dealt with similar issues. Designers and architects of high-end networking systems, as well as anyone using 8 Gbps or 16 Gbps PCI Express in their systems, will benefit from attending this presentation.
Presenter: Michael Lynch, R&D Manager, Synopsys Date/Time: Thurs., June 5, 1:30-2:30 p.m.
For more information on Synopsys’ DesignWare IP for PCI Express, visithere.
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As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.
The new DesignWare IP Development Kits provide a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers.
The IP Prototyping Kits provide a reference design on the HAPS-DX that runs right out of the box and can be quickly modified to support your specific configuration allowing design exploration and tradeoffs for your target application.
The DesignWare IP Virtual Development Kits provide a software development platform using a processor subsystem reference design including the OS and drivers for the IP. The beauty of this is the ability to start by using a virtual model of the IP as your target or use the HW on the HAPS-DX board as the target. It’s always great to get an early start by using the virtual model of the device, but move to the specific configuration running on an FPGA to ensure your software is working correctly.
SoCs contain multiple protocols and interfaces and the IP Accelerated Initiative supports the protocols that Synopsys offers. The IP Accelerated Initiative will help the designer using our DesignWare PCI Express IP by providing a software development platform and reference design along with our PCI Express IP that all coordinates together enabling concurrent software and HW development.
The last part of the IP Accelerated Initiative is to enable rapid customization and integration of the IP into the design. When I first started working at Synopsys in the IP group, we were working to convince people that using IP was a good thing. In talking to our customers, they all knew how to design the blocks for the protocols we were producing, so they would look through your code and architecture to see if it was better than theirs and it wasn’t just a make verse buy decision. Those days are past and purchasing IP is standard practice. The interesting side effect today is that designers are losing the expertise to implement the whole interface protocol on their chip as they move on to other portions of the SoC where they add higher value for their company. This is forcing a rethinking in the industry and customers are no longer looking to buy a PCIe PHY and PCIe Controller and put them together themselves for their SoC. Companies are looking to buy the whole interface from their IP vendor, but since it’s far more complicated than just stitching the two blocks together, the last part of the IP Accelerated Initiative focuses on delivering the full interface (in this case PCIe) to the customer with the customization and specific configuration needed for the SoC. Of course, this is carried further providing additional customizations, integration and verification based on the customer’s needs in order to get their SoC out the door.
If you’re at PCI-SIG this week, stop by our booth and say hello, discuss the IP Accelerated Initiative and see some great demos for our PCI Express 4.0 solutions. If you missed any of the press announcements you can view them here: