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Conversation Central Podcast

Is your SoC size just a little too big for your simulation britches?

Posted by Hannah Conrad on July 18th, 2013

Guest: Amol Bhinge, Senior Verification Manager, Freescale

Host:  Karen Bartleson, Director, Community Marketing, Synopsys Inc.

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As the size and complexity of SoC designs increase, a not-unexpected problem arises. Scaling the simulation environment to fit the demands of a state-of-the-art SoC requires skill, experience, creativity and collaborative innovations with EDA vendors. Amol Bhinge talks about how to overcome the never-ending obstacles facing SoC engineers today and tomorrow

Amol Bhinge: “It is really becoming monstrous. The challenges are becoming . . . crazy. Chips are getting so complex in terms of size itself that it’s getting very difficult for the simulation environment and the verification environment . . . to catch up with design size. . . .When the next project comes, it’s three times bigger than the previous project.”

During the show, Amol talks about:

  • why he is passionate about scaling the simulation environment
  • his most triumphant moment during the simulation of an SoC
  • what he knows that might surprise someone who is very experienced in SoC simulation
  • what he envisions verification of SoCs will look like 10 years from now

Links of interest:

Freescale


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