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Conversation Central Podcast

The Voices of DAC—Good, bad and useless verification

Posted by Hannah Conrad on June 23rd, 2011

Guest: Himanshu Bhatnagar, Executive Director, ASIC Design, Mindspeed Technologies

Host: Karen Bartleson, Sr. Director, Community Marketing, Synopsys

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Verification is often considered the bottleneck in chip design. Himanshu talks about how to alleviate this bottleneck and what new methods are available for System-on-Chip. Listen to why he thinks a disciplined approach to chip design is the most affective and how to ensure that engineers follow a laid out plan.

Karen also asks Himanshu to talk about verification challenges and how he envisions EDA solving verification problems for people like him. Himanshu’s answers, plus a discussion about the cloud, sparks a very lively and interesting dialog that closes the show.

Links of Interest:

Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and Primetime

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