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    This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
  • The Authors

    Graham Allan

    Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.

    Marc Greenberg

    Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.

Synopsys DDR3 PHY Now Available for Intel’s 22nm Tri-Gate Process

Posted by Graham Allan on June 3rd, 2014

It’s DAC time again and that means lots of EDA and IP related announcements.

Intel_DDR3-2133_eyeToday Synopsys and Intel issued a joint press release regarding our collaboration on IP for Intel 22nm and 14nm Tri-Gate technologies for use by customers of Intel Custom Foundry.  For me, this is an exciting press release.  When Synopsys first won the opportunity to design our DDR PHY into the Intel Tri-Gate technology, we were honored to be given that opportunity.  Keeping that under your hat is hard.  Working with one of the most advanced technologies on the face of the planet was exciting enough but it also laid a critical foundation for our Mixed Signal IP portfolio as semiconductors evolve from planar CMOS to three dimensional technologies such as Tri-Gate and FinFET.  The reduced leakage benefits offered by 3D transistors complemented by their faster switching capabilities enabled our DDR PHY designs to really shine in the lab.  The DDR3-2133 data eyes from our test and characterization platform show how well the PHY is performing.  Also note that our characterization platform and test chip do not cheat – we make every effort to keep the designs in line with typical cost effective packages and PCB stack-ups that our customers use today.

Synopsys is actively designing our DDR PHYs into many different 3D transistor technologies targeting DDR data rates up to 3200Mbps for both DDR4 and LPDDR4.  All of Synopsys’ DDR PHYs support multiple DDR standards to allow the end customer of the chip to choose which type of DDR SDRAM they use.

There’s a lot more I have to keep under my hat for now.  Stay tuned for future announcements and blog posts.

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