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    This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
  • The Authors

    Graham Allan

    Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.

    Marc Greenberg

    Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.

Qualcomm announces first application processor with LPDDR4 capability

Posted by Marc Greenberg on April 16th, 2014

This happened a little bit quietly last week – but Qualcomm has announced the first product that I’m aware of that will use LPDDR4 memory.

The processor is the Snapdragon 810 and you can read the press release here.

Naturally, these devices support the latest 64-bit mobile CPUs, native 4K video, image sensors up to 55MP, HDMI 1.4, Cat6 LTE, USB 3.0, Bluetooth 4.1, UFS Gear2, eMMC 5.0, SD 3.0 (UHS-1) and 802.11AC; all manufactured on 20nm process technology.

The memory performance is LPDDR4 1600MHz (assuming 3200Mbps data rate) with 2 64-bit channels giving an aggregate bandwidth of 25.6GByte/sec bandwidth according to the spec sheet here.

Qualcomm says that these products, the Snapdragon 810 and its sister product the Snapdragon 808, will “begin sampling in the second half of 2014 and expected to be available in commercial devices by the first half of 2015.”

Roll on, LPDDR4!

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4 Responses to “Qualcomm announces first application processor with LPDDR4 capability”

  1. Curious says:

    Hello Marc, good blog as always, one question though – For two channel, why is the aggregate bandwidth 25.6GBps? Shouldn’t it be 51.2? (3.2 x 64 / 8 = 25.6 PER channel)

    • Marc Greenberg says:

      That’s a great question @curious. I’ll admit I copied the number from the Qualcomm specification sheet (the link is in the original post). There are a few possibilities, and I will point out that this is speculation:
      – There could be two 64-bit channels and it’s 25.6GB/s per channel as you point out. This would actually require 4 LPDDR4 dies working in parallel to achieve this, and the PoP packages I’m aware of don’t have enough I/Os. So that’s unlikely to be a smartphone application (they usually use PoP packages) but it would still be possible to create a system like this in a tablet application with the application processor on one side of the PCB and 2 X64 or 4 X32 discrete LPDDR4 multidie packages on the other side of the PCB. We have seen this arrangement with LPDDR3 in some of the high-end tablets and in fact at Synopsys we build our LPDDRx characterization boards for our PHYs the same way.
      – 25.6GB/s could be the aggregate bandwidth for the chip and there are 2 32-bit channels totalling 64-bit width. It’s not exactly what the spec sheet says but it’s close. That would be a more normal high-end smartphone configuration – many of today’s smartphones do exactly that, and it is achievable with PoP packaging.

      I’ll ping some of my Qualcomm contacts and see if I can get a more definitive answer.


  2. curious says:

    I think the numbers will add up if it is 32 bits/channel in LPDDR. Many of us know that it is 64 bits/channel for regular DDR.

    Let us know! Thanks,

    • Marc Greenberg says:

      One of my contacts gave me a clue that it is 2X32-bit channels – total width 64 bits, total bandwidth 25.6GB/s.

      Thanks, Marc