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    This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
  • The Authors

    Graham Allan

    Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.

    Marc Greenberg

    Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.

“How Fast Can My DDR Go?”

Posted by Graham Allan on February 3rd, 2014

As a provider of DDR PHY and controller IP, the question we get asked the most goes something like this:  “Will your PHY support a {insert short description of system here} at {fill in the speed here} Mbps?  Lately, I am receiving a lot of questions around DDR4 such as “Will your DDR4 PHY support one dual rank UDIMM at 2667Mbps”?

Unfortunately, the answer is never what someone wants to hear.  The answer is usually “It depends”.  For example, DDR4 at 2667Mbps is a very high data rate for a parallel, single ended, 72-bit channel populated with 2 ranks of 4-bit wide SDRAMs.  That is a load of 2 SDRAMs per bit of data and 36 SDRAMs on the address/command bus!  That’s why RDIMMs and LRDIMMs were invented – to isolate the address/command (RDIMM) and data (LRDIMM) loading from the channel.

The maximum speed in such systems is not only a function of the PHY but rather the signal integrity of the entire system – PHY, SoC, package, PCB & DRAMs.  For example, in heavily loaded, multi-rank systems, the additional loading on both the address/command and data buses leads to a slower edge rate, which reduces the eye width, degrading the setup and/or hold time required by the SDRAM.  This impact must be taken into consideration during the signal integrity analysis of the timing for the interface as this reduction in eye width leads to a smaller data capture window.  Traffic dependent effects such as SSO (Synchronously Switching Outputs), crosstalk, and ISI (Inter-Symbol Interference) must also be taken into consideration.

Factors to take into consideration when analyzing a system for maximum speed include the package type (QFP?  BGA?  Wire bond?  Flip chip?), number of PCB layers, track spacing (in the package substrate and the PCB), amount of on-die decoupling, PHY power:signal ratios, package power:signal ratios, PHY deskew capability, operating conditions (PVT), etc.

An analogy I frequently use is one with cars and their maximum speed.  What if your friend asked you how fast can your car go?  How would you answer?  Even if you own the fastest production car in the world, something like the Bugatti Veyron Super Sport, you have to think about the answer.  How fast can it go if the road has sharp bends?  How about a dirt road?  Is it raining?  Is it snowing?  Is there other traffic on the road?  Are the tires inflated properly?  You get the idea.  Maximum car speed and DDR speed require similar qualification.

Once you have defined the entire DDR sub-system, only then can you proceed with a signal integrity analysis to verify if the target speed can be met with confidence.  That confidence comes from a series of timing budgets.  Each timing budget contains uncertainty contributions from the transmitter, the channel or interconnect, and the receiver.  For each timing budget, the SoC’s DDR PHY only contributes to the transmitter uncertainty or the receiver uncertainty depending on if you are writing or reading, respectively.  Everything else comes from the DRAM data sheet or the physics of the channel.  If, once you add up all the uncertainties, you have less than one bit period (e.g., half a clock period for the DDR data channel), then your timing budget passes.  Note that many timing budgets fail because they assume everything bad can happen at the same time which is virtually impossible in real life.  Typically, some of the dynamic uncertainties (those impacted by data pattern or operating frequency) need to be tamed in the analysis to avoid an overly pessimistic timing budget.

For more information on timing budgets for DDR interfaces, check out the Synopsys white paper at http://www.synopsys.com/dw/doc.php/wp/ddr_signal_integrity_wp.pdf.  This white paper may be from 2009 but the concepts are the same and apply more today than they ever have!  Then check out the ten tips to success for your SoC’s DDR Interface at https://www.synopsys.com/dw/doc.php/wp/ddr_top10_wp.pdf.

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