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    This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
  • The Authors

    Graham Allan

    Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.

    Marc Greenberg

    Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.

Happy 10th Birthday DDR4!

Posted by Graham Allan on January 13th, 2014

Believe it or not, work the DDR4 standard was first started back in 2004.  That’s now 10 years ago!  Happy 10th birthday DDR4.  10 years ago Facebook was started up, there was no Twitter (2006), no iPhone (2007), and Google went public for $85/share (it is now $1,123/share).  Even after those 10 years, you can’t go out a buy a computer with DDR4 in it.  The JEDEC standard for DDR4 was published in September 2012 so why isn’t everyone using it?  Why did it take so long?

That’s a long complicated story.  Fundamentally, it’s just plain hard to make a single ended, wide parallel interface operate at the data rates envisioned for DDR4.  Physics is getting in the way as the nanoseconds gave way to picoseconds and fewer and fewer of them.  The traditional wide DDR SDRAM interface is running out of headroom and the system design compromises to enable such high speeds are getting expensive.  It took a lot of bright engineers a long time to figure out what features are required in DDR4 to make it work in systems, and then agree on what was required, and then agree on how to tell other people what was required (e.g., write the standard).  In my opinion, DDR4 is the most complicated DRAM standard transition since asynchronous DRAM gave way to the SDRAM in the mid-1990s (and that took 5 years from first work on the standard to computers shipping with it).

Also, for most PCs, laptops and embedded applications – DDR3 has been good enough when you consider price, latency, performance, etc.  But, as it always is in the DRAM game, it’s mostly about price!  Only servers crave DDR4 for the lower power the SDRAM offers and only servers are willing to pay for it.  Higher data rates are nice but it’s the lower power that is most attractive.  DDR4 is the first DRAM standard that does not target PCs and laptops for the first application market.  Since DDR4 really targets servers first, that is a smaller segment of the DRAM market so the TAM for DDR4 is smaller than it was for DDR3 and will remain so until DDR4 ends up in laptops and PCs (both of which are declining markets themselves).  That is a chicken and egg problem.  Laptops and PCs will not embrace DDR4 until it becomes cheaper than DDR3 yet the shrinking TAM for DDR4 means the volume will not ramp very quickly and volume largely determines the price in the DRAM market.

So basically, there is nowhere for DDR4 to go yet and the future is only bright-ish.

Add to the complex equation that consumers are abandoning PCs and laptops for ultrabooks, tablets and smartphones which use lower power mobile SDRAMs such as LPDDR2 and LPDDR3.  The volume for LPDDR2/3 is ramping up while the volume for DDR3 is waning.  There is a lot more industry momentum around the mobile DRAMs (e.g., LPDDR2/3/4) than there is around the “PC” memories (e.g., DDR3/4) because the volumes are increasing and the prices are higher for mobile DRAMs.  More of anything at a higher price is attractive if you sell that thing!  However, nothing lasts forever and as the memory market volumes teeter towards mobile DRAMs and away from the PC DRAMs, I predict the prices of mobile DRAMs will fall, eventually to below the price per bit level of the PC DRAMs.  This will likely happen within the next 2 years.

Finally, back to that DDR4 standard…  For anyone who is familiar with the DDR4 standard, it does not define the 3200Mbps data rates that most articles about DDR4 talk about.  How many times have you read that DDR4 is twice as fast as DDR3?  That was true back when DDR3 was only standardized up to 1600Mbps.  DDR3 has since been enhanced to accommodate data rates of up to 2133Mbps.  The maximum speed for the current DDR4 standard is 2400Mbps (only 13% faster than the maximum speed for DDR3).  In fact, 3200Mbps, once we get there, is only 50% faster than DDR3.  There are also some other areas where the standard is not complete.  JEDEC has been working diligently to update the standard – that cat was let out of the bag in a recent EEtimes article: http://www.eetimes.com/author.asp?section_id=36&doc_id=1320534&itc=eetimes_sitedefault&cid=NL_EET_Daily_20140103&elq=10ac88effa334363983119d0e84ed904&elqCampaignId=3302.  One of those updates is likely to be for the speed grades above 2400Mbps.

DDR4 will have a future, but it will never be the DRAM “rock star” that DDR3 is.  DDR3 has already been the king of DRAMs for longer than DDR2 was and it still has a long runway ahead of it.  Long live the King!

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3 Responses to “Happy 10th Birthday DDR4!”

  1. Halwits says:

    A very good information you have shared about the DDR4.

    And I also agree with your point that DDR3 is the king of DRAMs.

    Thanks a lot for this impressive post.

  2. wideio says:

    put simply DDR4 is antiquated before it even exists as a commodity part

    just start using the memory barrier breaking Wide IO and HMC today

    as you well know that Wide IO was ratified long before JEDEC slipped in this so called DDR4 (to milk the markets)that’s in fact slower and has higher latency than the far better low power WIO2 and its sibling HMC at 7 to 15 times the data throughput of DDR4 right now.

    WIO is a 512bit 4xDDR3 at 266Mhz single module/IO channel.

    “Wide I/O 2 has a four-channel architecture, but the channels have a higher bandwidth of 6.4GBps and have 64 I/Os per channel, yielding an overall 25.6GBps data rate.

    Later Wide I/O 2 devices will have up to 128 I/Os per channel and a data rate of 51.2GBps . Wide I/O 2 also opens the possibility of a 1,024-bit interface to memory.”

    “The first Wide I/O 2 devices will probably be 2.5D interposer-based architectures. These take more space than 3D die stacks, but 2.5D chips also have fewer thermal problems, more flexibility to rework connections, and lower costs. Wide I/O 2 (3D)is expected to go into mass production in 2015.”

    “Hybrid Memory Cube – Low Power, Blazing Fast

    Want to go really, really fast – say, up to 320GBps ? And while we’re at it, how about with 70% less energy per bit than DDR3 and 90% less board space than today’s RDIMMs ? Then take a look at the Hybrid Memory Cube (HMC), which is expected to go into mass production in 2014 .”

    please explain exactly why the so called industrial server markets would pay for DDR4 at best 2x the speed of the very best DDR3 today, over the HMC at 7x DDR4 data throughput in 1 or 2 years.

    or for that matter why the masses of low power mobile markets or even desktop at that time would pay for DDR4 over the far better lower latency, lower power and far higher data throughput of WIO is beyond me…

    as for your MRAM coverage , its also interesting you didn’t mention that its already commercially here today from Everspin/Freescale

    https://www.youtube.com/watch?v=kTKivwuzvNs#t=125 in production for some 5 years already on 90nm with the same speeds and data throughput as DDR3…

    so i ask you where exactly is generic ddr4 today when these far better long term options exist, and the foundries and packagers are ready now, just design your
    existing IP around these new specs and be done with it.


    • Graham Allan says:

      Hi wideio,

      Thank you for your comments.

      WideIO is not targeting the same application space as DDR4. WideIO is a technology primarily aimed at mobile phones since the idea is that the WideIO memeory sits directly on top of the applications processor and connections to/from the memory are all made by TSVs. In the context of a server or Enterprise application, that is simply never going to deliver enough capacity (in GB) of DRAM. It is also not an upgradable format, once you install the memory, that’s all you get.

      WideIO is effectively competing with LPDDR for the smartphone design wins. At this point, I predict that LPDDR3/4 will dominate over WideIO2. Why? Because WideIO2 is revolutionary and LPDDR3/4 is evolutionary (the DRAM market always prefers evolution). Because LPDDR3/4 will be cheap and WideIO2 will be expensive (because of the TSVs and because volume drives price). Because WideIO2 requires those TSVs which are still not ready for prime time in high volume manufacturing. Because there are interesting infrastructure problems with the WideIO2 business model (for example, the complete SoC + WideIO2 structure has a fault – who is at fault?). And finally, because that is what we are seeing the bulk of our customers ask for in terms of memory controller and PHY IP. There is no doubt that WideIO2 is an interesting technology, I just think it is still ahead of its time. I would not want to be the SoC architect that tells my boss, “I’d stake my career on my choice that we should use WideIO2″.

      HMC is a very interesting technology. It is a self contained chip which means all the manufacturing problems lie with the HMC vendor. There is little doubt that memory interfaces (DRAM or whatever replaces DRAM in many years to come) will eventually have to go serial. The main issue is high volume adoption and price. DDR4 will still be a huge volume product and that will make it very cheap. HMC targets markets that lower volume so the price is likely to remain higher than DDR4 because the HMC volume will be much lower. HMC also uses more complex packaging, requires TSVs, and has the logic die on the bottom adding more cost to every device. I believe HMC or something similar will garner small to modest volume but will remain expensive so only high end products will be able to afford the cost of HMC.

      The memory industry is like a capacitor is to voltage, it resists change. The time constant in the memory industry is a long one. Nothing will ever be as cheap as the RAM that ships inside the highest volume end product. That is still DDR3 today in PCs, laptops and consumer electronics. DDR3 is also still used in servers and Enterprise systems. DDR4 will eventually replace DDR3 in all of those areas but will mobile applications and LPDDR2/3/4 soon outpace DDR3/4? I predict yes. That may make LPDDR2/3/4 cheaper than DDR3/4 but LPDDR2/3/4 is specifically defined for very short connections (ideally PoP) and is not directly applicable for other applications. That means there will still be aplace for DDR3/4 for years, if not well over decade, to come.