BLOGS & FORUMS
Committed to Memory
|Committed to Memory|
This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.
Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.
Posted by Marc Greenberg on September 5th, 2014
Samsung has posted their DDR4 product guide on their website, and it gives us excellent insight into the direction that Samsung plans to go with DDR4 in the next few months with a lot of data that wasn’t previously publicly available.
The product guide shows us some things we have not seen in a while, like SoDIMMs with ECC, and also some new things like the first mention I have seen of commercially available TSV stacks of DDR4 devices (presumably using the 3DS extension to the DDR4 standard). This product guide would seem to indicate that the TSV 3DS DDR4 parts could have engineering samples available in Q3’14
The first page, the part numbering guide, shows us what dies have been incorporated into the part numbering scheme, which include:
– 4Gb and 8Gb dies
– X4 and X8 width (no mention of X16 width parts)
– Flip Chip and DDP (Dual Die Package) packages
– Commercial temperature range (0-85c) & normal power
– DDR4-2133 speed grade with 15-15-15 timing
– DDR4-2400 speed grade with 17-17-17 timing
No mention was made of:
– X16 width (although page 6 hints at the availability of an X16 device)
– Extended temperature range
– Reduced power
– Speeds above DDR4-2400
The second page, the component product guide, shows 4Gb dies in X4 and X8 width as available now, and 8Gb dies in X4 and X8 width with engineering samples in 3Q’14
The third page, the module ordering information, shows us what modules have been incorporated into the module numbering scheme, which include:
– RDIMMs, LRDIMMs, and SoDIMMs
– 288-pin format RDIMM and LRDIMM; 260-pin format SoDIMM
– 72-bit width DIMMs (these are typically used as 64 bits data with 8 ECC check bits in servers and other devices with enterprise-class reliability requirements)
– Memory Buffer chips from IDT and Montage
It appears that the module ordering information may not be fully up to date with the information in the module product guide that follows.
Pages 5-6, the module product guide, describes in total 22 different DIMMs (of which 14 have part numbers and 8 have TBD part numbers). Highlights are:
– ECC RDIMMs in 8GB and 16GB using 4Gb X4 devices, 1 and 2 ranks respectively, MP availability
– ECC RDIMM in 8GB using 4Gb X8 device, 1 rank, MP availability
– ECC RDIMMs in 16GB and 32Gb using 8Gb x4 devices, 1 and 2 ranks respectively, ES in 4Q’14 and 3Q’14 respectively
– ECC RDIMMs in 64Gb and 128Gb using 4H TSV packaging, 8 ranks, 4Gb and 8Gb per die respectively, ES 3Q’14 and 1Q’15 respectively.
– VLP ECC LRDIMM of 32GB and 64GB, DDP (Dual Die Packages), X4 organization, 4 ranks, 4Gb and 8Gb dies respectively, MP availability and ES 4Q’14 respectively
– VLP ECC RDIMM of 16GB, DDP (Dual Die Packages), X4 organization, 2 ranks, 4Gb dies, MP availability
– ECC SoDIMMs of 8GB and 16GB, dual-rank X8 parts, using 4Gb and 8Gb dies respectively, with MP and ES 4Q’14 availability respectively
– non-ECC SoDIMMs and uDIMMs of 4GB and 8GB using 4Gb X8 dies, 1 and 2 ranks respectively, on CS availability
– non-ECC SoDIMM and uDIMM of 4GB using one rank of X16 8Gb die, ES 3Q’15 and ES2Q’15 respectively
– non-ECC SoDIMM and uDIMM of 8Gb using one rank of X8 8Gb die, ES 3Q’15 and ES2Q’15 respectively
That’s quite a list!
You can read the whole product guide here.
DDR4 is coming. Be ready! Talk to us about how we can help with your SoC designs supporting DDR4.
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | No Comments »
Posted by Marc Greenberg on September 2nd, 2014
Since last week’s announcement of Intel CPUs supporting DDR4, the first almost-announcement of a DDR4 machine by a major PC manufacturer that I have found is the Alienware Area-51 (Alienware is a Dell subsidiary). I say almost-announcement because at the time of writing this blog, Alienware’s website didn’t include any details of when it will be available for sale, or how much it would cost, or anything like a press release on it. The machine will be capable of running up to three 4K monitors simultaneously and support up to 32GB of DDR4 memory running DDR4-2133.
One could argue that ASUS is first to market, being a major PC manufacturer, and having announced three motherboards with the Intel X99 Chipset and capable of using DDR4 - in fact, these motherboards are designed to be DDR4-only because of incompatibility between the DDR3 DIMM socket and the DDR4 DIMM socket. However, I don’t see an Asus machine using these motherboards on their website yet, so it appears that the motherboards will be sold to enthusiasts and system integrators until the market builds for a machine capable of using the new Intel CPUs and DDR4.
Of course ASUS aren’t the only game in town… this excellent article over at Tweaktown compares 26 different X99-based motherboards capable of DDR4.
Now that we’ve discussed the first things first, we can discuss what’s the fastest. Remember that Intel presently validates DDR4 devices up to DDR4-2133 data rate (2133MT/s). However, if something is worth doing, it’s worth overdoing, and the folks over at G.SKILL announced they overclocked an Intel CPU on an ASUS motherboard with their new Ripjaws 4 DDR4 DIMMs to achieve a data rate of DDR4-4004 (4004MT/s)… with a little help from some liquid nitrogen to cool it down! I wonder how long it ran for…?
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | No Comments »
Posted by Marc Greenberg on August 29th, 2014
As predicted in my earlier blog entry, today is the official launch of Intel’s products supporting DDR4.
The press release is here: Intel Press Release and it seems to match earlier predictions on the release of the new eight-core desktop processor, the Intel® Core™ i7-5960X processor Extreme Edition, formerly code-named “Haswell-E”. Other than DDR4, Intel reports that this CPU and its associated X99 chipset will support 10 SATA 6Gb ports and 40 lanes of PCIe.
Along with the announcement, Intel have posted their DDR4 memory validation results here, showing compatibility with DDR4 UDIMMs from Micron, Crucial, Samsung, SK Hynix and Kingston, in 4GB single-rank and 8GB dual-rank capacities, all using 4Gb X8 DDR4 devices running at DDR4-2133 data rate, 1 DIMM per channel, and running all 4 channels.
Although Intel says the will be available next week, at the time of writing at least one online retailer claims to have them available now at $1085.54 and with 170 available.
Let the DDR4 begin!
Posted in DDR Controller, DDR4, DIMM, DRAM Industry | No Comments »
Posted by Graham Allan on August 25th, 2014
JEDEC officially published the LPDDR4 standard today. It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication. That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market. The JEDEC committees responsible for this latest publication should be very proud of their achievement. Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.
The new standard can be found at the bottom of the page here
LPDDR4 is an interesting DRAM product. As soon as you get to page 2 of the standard (page 6 of the PDF file), you will notice a “pad order” figure. What may not be so obvious from the diagram is that LPDDR4 is designed to be a single 32-bit wide die with two independent 16-bit wide channels. This is the first traditional “DDR” SDRAM that defines more than one channel for the die. There are also 64-bit versions of the packages which include two die inside for a total of 4 independent 16-bit wide channels. Each channel has its own address/command lane. Since LPDDR4 is a 16n prefetch device (every read/write access 16 words of data), one read or write operate accesses 16 words x 16-bits or 256bits or 32Bytes of data. That is the same as LPDDR3 which is a 32-bit channel with an 8n prefetch (8 words x 32-bits). LPDDR4 is designed to operate with independent 16-bit channels which means is it not directly compatible with LPDDR3 which uses 32-bit channels in the 64-bit device or DDR4 which only ever has one channel per device. SoCs that need to interface to multiple types of DRAMs including LPDDR4 will need to incorporate the flexibility to be optimized for the type of DRAM being used.
Some of the other new features of LPDDR4 include:
- Support for data rates up to 4266Mbps
- A 1.1V operating supply (LPDDR3 and DDR4 are 1.2V)
- The address command lane is very narrow (6 bits for address/command plus clock, chip select, CKE and ODT) and it is single data rate. Multiple clock cycles are required to transfer commands (4 clock cycles for a read or write)
- Ground terminated signaling (DDR4 & LPDDR3 use VDDQ termination, DDR3 uses midpoint termination)
- A new DMI function which combines data bus inversion and data mask functionality giving you the best of both worlds (with DDR4, only one or the other function can be supported as programmed into the device)
- Two “Frequency Set Points” that support switching between two frequencies without ever being in an untrained state
The DRAM vendors are working diligently to make LPDDR4 SDRAM available. Keep your eyes out for their press releases announcing their products.
Synopsys has LPDDR4 IP available for the host devices needing to interface to LPDDR4 and other types of SDRAMs. Contact us for more information.
Posted in DDR Controller, DDR PHY, LPDDR4 | No Comments »
Posted by Marc Greenberg on August 20th, 2014
Following today’s event in Seoul, there are still two more JEDEC LPDDR4 Workshops and Mobile Forums coming up in the next few weeks.
This Friday (August 22nd) there will be an event in Hsinchu, Taiwan, followed by the Santa Clara CA event on Sept 22-23. More details here
Synopsys will be presenting “Using LPDDR4 Multi-Channel Architecture for Performance and Power” at the LPDDR4 workshops, being presented today (August 20) by HB Choi in Seoul, Friday by Tom Liu in Hsinchu, and on Sept 23 by me (Marc Greenberg) in Santa Clara.
Graham and I both plan to attend the Santa Clara event – please be sure to come by and say “Hi” and ask us any DDR questions you may have.
Posted in DDR Controller, DDR PHY, DRAM Industry, Low Power, LPDDR4 | No Comments »
Posted by Marc Greenberg on August 15th, 2014
There is a ton of internet speculation today – mostly based on a report on a Japanese website - that Intel will make it’s first DDR4-compatible products available on August 29th and that internet retailers may make those products available for sale the same day. Earlier speculation was that Intel would release the DDR4-compatible products in time for the Intel Developer Forum in mid-September.
There is precious little pre-launch information from official Intel sources, but this link on Intel’s website indicates that three CPUs will be available – the Haswell-E based Core(TM) i7-5960X, the i7-5930K and the i7-5820K, all supporting DDR4 at up to 2133MT/s with up to 8 CPU cores and 20MB of cache in the case of the i7-5960X.
Other vendors seem to be gearing up for the event – online vendors ramexperts.com report having stock of Corsair’s Dominator Platinum 16GB (4x4GB) DDR4 DIMM kit running at 2800MT/s at a hair under Corsair’s RRP of $539.99. That is a hefty premium of about 2-3X over street price for equivalently sized but slower 16GB (4x4GB) DDR3-1600, but actually less than some of the highly overclocked DDR3 DIMMs that are available from some vendors.
What will happen? We’ll see… stay tuned!
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | Comments Off
Posted by Graham Allan on June 3rd, 2014
It’s DAC time again and that means lots of EDA and IP related announcements.
Today Synopsys and Intel issued a joint press release regarding our collaboration on IP for Intel 22nm and 14nm Tri-Gate technologies for use by customers of Intel Custom Foundry. For me, this is an exciting press release. When Synopsys first won the opportunity to design our DDR PHY into the Intel Tri-Gate technology, we were honored to be given that opportunity. Keeping that under your hat is hard. Working with one of the most advanced technologies on the face of the planet was exciting enough but it also laid a critical foundation for our Mixed Signal IP portfolio as semiconductors evolve from planar CMOS to three dimensional technologies such as Tri-Gate and FinFET. The reduced leakage benefits offered by 3D transistors complemented by their faster switching capabilities enabled our DDR PHY designs to really shine in the lab. The DDR3-2133 data eyes from our test and characterization platform show how well the PHY is performing. Also note that our characterization platform and test chip do not cheat – we make every effort to keep the designs in line with typical cost effective packages and PCB stack-ups that our customers use today.
Synopsys is actively designing our DDR PHYs into many different 3D transistor technologies targeting DDR data rates up to 3200Mbps for both DDR4 and LPDDR4. All of Synopsys’ DDR PHYs support multiple DDR standards to allow the end customer of the chip to choose which type of DDR SDRAM they use.
There’s a lot more I have to keep under my hat for now. Stay tuned for future announcements and blog posts.
Posted in DDR PHY, DDR3, DDR4, IP, Low Power, LPDDR4, Signal Integrity | Comments Off
Posted by Graham Allan on June 2nd, 2014
Synopsys made an exciting announcement today launching our new IP accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their SoCs. This initiative augments Synopsys’ broad portfolio of DesignWare® IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With the IP Accelerated initiative, Synopsys goes beyond the traditional IP supplier paradigm, redefining what customers can expect from their IP providers to help them successfully integrate IP with less effort, lower risk and faster time-to-market.
The full press release can be found here
Posted in IP | Comments Off
Posted by Graham Allan on May 28th, 2014
A lot has been written about DDR SDRAMs, both the compute variety (DDR3/4) and the mobile variety (LPDDR3/4) and what may come after these technologies run their course. One thing is certain; the future will not be an easy path for DRAMs. The DDR protocol based on a wide parallel bus with single ended signaling and a source synchronous data strobe and non-embedded clock is not scalable beyond the data rates currently specified for these technologies. After DDR4, the world will need something else as the DDR interface cannot realistically be expected to run at data rates higher than 3200Mbps in a traditional computer main memory environment. Unfortunately, that something else will likely be “somethings” else. Likewise, the smartphone’s insatiable need for higher bandwidth from main memory DRAM will also lead to a deviation from the wide parallel bus based DRAM.
Once DDR4 has run its course in computers (which, in my opinion, is really quite a long way off), the most likely candidate to replace it is a SerDes based DRAM such as the Hybrid Memory Cube (HMC), certainly at the higher end of computing such as servers. There is a ton of information available on HMC and the best jumping off point is the HMC consortium page at www.hybridmemorycube.org. Some computing solutions may also seek out the incredibly wide bus (bandwidth = # bits x speed so to get higher bandwidth, you can go wider or go faster) High Bandwidth Memory (HBM) as specified by JEDEC. The complete standard for HBM is available from the JEDEC web site at http://www.jedec.org/standards-documents/docs/jesd235. HBM may also become the eventual successor to the GDDR5 SDRAMs that are used today in high end graphics applications and gaming systems such as the Sony PlayStation 4 (http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-sony-ps4/).
In mobile applications, the ultimate successor to LPDDR4 may very well be the Wide IO3 SDRAM. I say Wide IO3 because Wide IO (the first version) gained little market adoption and Wide IO2 will likely lose the vast majority of sockets to LPDDR4. By the time Wide IO3 is fighting it out with LPDDR5 (if such a thing is ever discussed), it may just be time for something new. The WideIO standards are also developed and available from the JEDEC web site (www.jedec.org).
One common element to HMC, HBM and WideIO is the Through Silicon Via (TSV). TSV technology essentially relies on holes being formed through the DRAMs and/or SoC with the connections between them made by hundreds or thousands of short electrical traces connecting the stacked die (http://en.wikipedia.org/wiki/Through-silicon_via). What differentiates the HMC product here is that the TSVs are all internal and become the responsibility of the memory vendor. You purchase the HMC DRAM and put it on a PCB like you do with DDR today so the infrastructure to use it is very simple. When the TSV will be ready for high volume, economical manufacturing is a subject of some other blog. But it is a hurdle, the question is how high is it?
Below is a comparison table of the current DDR3/4 and LPDDR3/4 technologies with Wide IO, HMC and HBM. You can click on it to get an enlarged version. I have tried to ensure the table is correct and some of it is open to interpretation. If you feel that the table is incorrect, incomplete or you have a different opinion, please leave us a comment!
Posted in DDR3, DDR4, DRAM Industry, HBM, High Bandwidth Memory, HMC, Hybrid Memory Cube, IP, LPDDR3, LPDDR4, Signal Integrity, Wide I/O, Wide I/O2 | Comments Off
Posted by Marc Greenberg on April 23rd, 2014
We are thrilled about today’s blog topic: the announcement of Synopsys’s complete LPDDR4 IP solution!
IP for LPDDR4 allows more chip designers to have access to LPDDR4 technology more quickly – even before the standard has been released. We’re big fans of LPDDR4 for it’s high bandwidth and low power features, and we see it as a technology that will make a huge difference to the performance and energy usage of mobile and consumer products of the next few years.
There has been a huge effort from the whole team here to develop all the pieces of the solution. There’s a formal press release here: http://news.synopsys.com/2014-04-23-Synopsys-Announces-Industrys-First-Complete-LPDDR4-IP-Solution-for-High-Performance-Low-Power-Mobile-SoC-Designs
Over the next little while we’ll go into details about what each part of this announcement means, but for this post let’s stick to the high points:
– An LPDDR4 multiPHY and I/Os with low power consumption
– An Enhanced Universal DDR Memory Controller (uMCTL2) with high bandwidth and low-power features
– LPDDR4 Verification IP
– Hardening and Signal Integrity services
All the parts of the solution will support speeds up to 3200Mbps per pin (25.6GBytes/s peak bandwidth for a typical 2-die LPDDR4 solution with 64 data pins) with low-power features, PoP or memory-down on PCB support, backwards compatibility with LPDDR3, DDR4, and DDR3/3L/3U memorie. All the parts of the solution are backed by Synopsys’s global team with 15 years of experience and more than 800 DDR Design IP wins to date.
We know you’ll have questions – please feel free to ask!
Marc Greenberg and Graham Allan
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DRAM Industry, IP, Low Power, LPDDR3, LPDDR4, Signal Integrity | Comments Off
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