BLOGS & FORUMS
Committed to Memory
|Committed to Memory|
This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.
Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.
Posted by Marc Greenberg on March 9th, 2015
I have written on the topic of Row Hammering in a White Paper I published last year (link here) but since it is in the spotlight recently I thought I’d dedicate a blog entry to it. I had never considered this to be a security hole until this morning.
This morning Google Project Zero – the same team that discovered the Heartbleed bug – published this blog entry, “Exploiting the DRAM rowhammer bug to gain kernel privileges”
The blog entry is very detailed so here’s a short summary:
- Some DDR devices have a property called “row hammer” that can cause some bits in DRAM to flip under certain conditions
- The conditions that cause row hammering are so rare in normal operation that nobody even knew it could happen until relatively recently
- Some researchers discovered ways of making row hammering bit flips happen more often
- Google Project Zero reported that user code that has access to unprotected regions of the operating system that link to protected regions of memory may be row hammered to get unprotected access to the whole memory
- Once a hacker has unprotected access to the whole memory, they can do pretty much anything they want with your system
Google has tried their technique on 29 machines and found that they could initiate bit flips on 15 of them with some software utilities they wrote to exploit row hammering.
Google may have already patched the Chrome browser to help prevent this issue
What happens next? Well, at a minimum, we’ll probably all need browser and operating system patches to prevent row hammering exploits. It may be possible to program the BIOS in your system to refresh the DRAM more often which could help to reduce the probability that row hammering would work on your system (at the cost of more power usage and lower performance though).
Looking forward to DDR4, Row Hammering may be a thing of the past. Samsung announced in May 2014 that their DDR4 memory would not be susceptible to Row Hammering because they implement Targeted Row Refresh (TRR) – the cure to Row Hammering – inside of their devices: and Micron’s datasheets say, “Micron’s DDR4 devices automatically perform TRR mode in the background.” There’s some evidence that next-generation CPUs will either not be capable of issuing row hammering data patterns, or may mitigate them with TRR, or both.
As always, browse safely and keep your software up to date!
Some updates since I wrote this post:
– It appears that this may affect primarily consumer machines – those without ECC DRAM. It would be much harder to make this exploit workable with ECC DRAM used in servers and enterprise-class machines. It would be harder still to induce the error in machines supporting ECC patrol scrub. (Note: Synopsys’s uMCTL2 memory controller supports both ECC and ECC patrol scrub)
– Cisco published some useful information on how to mitigate the Row Hammer issue. In that blog entry, Cisco reports that Intel’s Ivy Bridge, Haswell, and Broadwell server chipsets support Target Row Refresh capability.
– IBM has published a list of their machines that are not affected by the issue
– TechTarget quoted my blog in their report on the issue – an excellent article by Michael Heller
Posted in DDR3, DDR4, DIMM, DRAM Industry, Signal Integrity, Uncategorized | No Comments »
Posted by Marc Greenberg on November 19th, 2014
I’m thrilled to blog about our latest IP prototyping kits that allow much faster FPGA prototyping of your DDR designs. In the last few years I’ve seen our HAPS prototyping boxes at more and more of our customers, and people I’ve talked to really like the ability to do their software prototyping for their DDR IP on their desktops long before their SoCs are manufactured.
If you’ve ever prototyped anything – whether it was a breadboard full of discrete devices, a piece of software, a demo board, or the first engineering sample chips to come out of the fab – it seems like the biggest problem is always making it work the very first time. A lot of the demo boards I’ve worked on have been equipped with a green LED that indicates the status and health of the board, and so the first objective is always “making the green light go on”.
It’s no different with FPGA prototyping; the very first goal is making the first test work – and this is something that is addressed very well with the IP prototyping kits.
Here is the problem that existed before IP prototyping kits: when prototyping a DDR subsystem, there are an almost infinite number of ways to configure it, and an almost infinite number of ways to do it wrong. Even if you take exactly what you have working in your ASIC RTL verification environment and port it over to an FPGA environment, you can still get it wrong, for lots of reasons that you might not even have thought of. The ASIC environment may have some “cheats” to make verification faster. The DDR memory device may be operating at a different frequency. You may have a different DDR memory device connected to your FPGA compared to what’s in the verification environment. There could be differences in how the memory controller and PHY in the FPGA are being programmed compared to the ASIC verification environment. Analog components may initialize differently ‘in real life” than they do in simulation. The design may not have been mapped from ASIC to FPGA correctly, for example, the signal pins you thought you connected to might not be the ones you actually connected to. There could be physical factors at work – are all the connectors seated correctly and is the power supply set up with the correct voltage?
If you get any one of these things wrong, you’ll likely be eyeballs-deep in user manuals, schematics, and helpdesk tickets. All of these factors and many more can conspire against you to prevent you from getting that first test working and “making the green light go on”.
Once you know that the whole setup works, that’s when you can start really working with it. You can run more tests, and you can make changes to the environment. You can start running your real software on it, and you can start finding the real issues that could affect the final design. Did you change something and the green light doesn’t go on anymore? Take a step back to the last known good point and debug your changes from there.
So this is where the new IP prototyping kit for DDR comes in. A full setup of the IP Prototyping kit for DDR would include:
– a pre-configured Synopsys uMCTL2 memory controller for use with the prototyping kit,
– a pre-configured FPGA emulation model of Synopsys’s Gen2 DDR multiPHY or DDR4 multiPHY that behaves similarly to the ASIC version while using FPGA resources,
– a HAPS DDR daughtercard,
– a reference design that includes an interface to an ARC Software Development Platform running software that is pre-installed with Linux drivers that can configure the controller and PHY registers and run DDR tests, and
– a windows-based GUI to allow easy manipulation of register settings in the IP Prototyping kit.
With all this equipment, we expect that you can unpack the box and get the first test running within minutes. Green light!!
Our customers have told us that without an IP prototyping kit, it can take as much as six weeks to get an FPGA prototype working (and you can bet it’s not a fun six weeks). Reducing the time taken to getting the first test running in a few minutes is a huge benefit to everyone on the project. Once you have the first test running, every other test you do is so much easier, because you have the confidence that the setup is correct and the results you are seeing – good or bad – are a result of what’s happening in your prototype and your software.
You can find out more about all the Synopsys IP prototyping kits at: http://news.synopsys.com/2014-11-19-Synopsys-Expands-IP-Accelerated-Initiative-with-New-DesignWare-IP-Prototyping-Kits-for-10-Interface-Protocols
Posted in DDR Controller, DDR PHY, DDR3, DDR4, DIMM, LPDDR3 | Comments Off
Posted by Marc Greenberg on November 5th, 2014
A good friend of mine alerted me that Dell’s latest product lines featuring DDR4 memory are scheduled to ship as early as next week. A quick summary:
The “Entry-Advanced” Dell Precision Tower 5810 workstation (starting at $1209). Entry level gets an Intel® Xeon® Processor E5-1603 v3 and 8GB of DDR4-2133 expandable to faster CPUs and 16GB of DRAM. Estimated ship date Nov 14th.
The Premium Dell Precision Tower 7810 and 7910 Workstations (starting at $1539 and $2059 respectively). Entry level for the 7810 gets an Intel® Xeon® Processor E5-2603 v3 and 8GB of DDR4-2133 expandable to faster CPUs, dual 12-core CPUs and 64GB of DRAM. Estimated ship date Nov 14th.
The Dell Precision Rack 7910 (starting at $2129) is a server that can hold up to 16 DDR4 DIMMs (512GByte), estimated ship date November 26th. To make the 512GByte configuration, it’s 16x32GB DDR4 ECC LRDIMMs for $11,277.50 and according to the website it “May delay your Dell Precision Rack 7910 ship date” although it appears that more normal memory configurations would be available sooner.
The Dell “13th Generation” PowerEdge rack servers R430, R530, R630, R730 and R730xd (starting at $1929 for the R630) and T630 tower (starting at $1609) are servers that can hold up to 24 DDR4 DIMMS (768GByte when using 32GB LRDIMMs), various estimated ship dates including Nov 14th and Nov 26th. Like the Rack 7910 they take up to 32GB DDR4 ECC LRDIMMs; additionally the PowerEdge may offer memory RAS features like Memory Sparing, Advanced ECC (Single Device Data Correction), and Memory Mirroring features depending on the model.
As for the Hexagonal styling of the Alienware “Area 51″ A51, entry level on that is $1699 for a 4th generation Intel Core(tm) i7-5820K CPU and 2 channels of DDR4-2133 (shipping December 1st), ranging up to $4549 for the Intel Core(TM) i7-5930K CPU and 4 channels of DDR4-2133 (plus a whole lot more in the graphics, storage, power supply, and other areas), estimated ship date December 18th. Don’t forget to add the 4K 32″ monitor (not included)!
Pricing and shipping dates reported were as viewed on Dell.com on November 5, 2014.
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | Comments Off
Posted by Graham Allan on October 16th, 2014
Yesterday was Memcon time again. Memcon is the event that Denali started as a one-day conference in Silicon Valley that is all about memory. After Cadence acquired Denali, Cadence now hosts the event.
Along with Memcon, we typically see at least one related press release. The one from Cadence this year really caught my eye. Yesterday, Cadence issued a press release that was titled “Cadence Announces Industry’s First Multi-Protocol DDR4 and LPDDR4 IP Solution”. http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=101015_ddr4&CMP=home The release states “Extends memory leadership from LPDDR3/DDR4/3 to include LPDDR4 with performance up to 3200Mbps.”
Are they really “First” or “Leading”?
Synopsys issued an April 23, 2014 press release announcing our LPDDR4 IP Solution. That press release stated “Supports LPDDR4 up to 3200 Mbps with low power consumption. Backward compatibility with LPDDR3 and DDR3/4 SDRAMs simplifies design transition from one SDRAM standard to the next”. http://news.synopsys.com/2014-04-23-Synopsys-Announces-Industrys-First-Complete-LPDDR4-IP-Solution-for-High-Performance-Low-Power-Mobile-SoC-Designs
The products appear similar, but one was announced 6 months before the other. You decide, is the Cadence announcement a truthful press release?
Posted in DDR Controller, DDR PHY, DDR4, LPDDR4 | Comments Off
Posted by Marc Greenberg on October 10th, 2014
Have you been looking for DDR4 datasheets? Here is a roundup of what’s available online from the memory vendors:
Micron datasheets of their DDR4 4Gbit dies in X4 and X8 widths and in DDR4-2133 and DDR4-2400 speed bins are available here: http://www.micron.com/products/dram/ddr4-sdram#fullPart - Hover over the datasheet icon and then click on “Download PDF” to get them.
Samsung datasheets of the DDR4 4Gbit dies in X4 and X8 widths and in DDR4-2133 and DDR4-2400 speed bins are available here: http://www.samsung.com/global/business/semiconductor/product/computing-dram/catalogue - Click on a part number and then click on the PDF link to get them
SK Hynix datasheets of the DDR4 4Gbit dies in X4, X8 and X16 widths and in DDR4-1600, DDR4-1866, DDR4-2133 and DDR4-2400 speed bins are available here:
http://www.skhynix.com/products/computing/computing.jsp?info.ramCategory=computing&info.ramKind=31&info.eol=NOT&posMap=computingDDR4 – Click on a part number and then click the link under “Technical Data Sheet” to get them.
Of course, this is just what’s public. You may be able to get non-public datasheets for other DDR4 devices by asking the memory vendors directly.
The JEDEC standard for DDR4 is here: http://www.jedec.org/standards-documents/results/jesd79-4%20ddr4
This information is as of the date of writing this blog post – memory vendors may update, add or remove datasheets at any time.
Posted in DDR4, DRAM Industry, Uncategorized | Comments Off
Posted by Marc Greenberg on September 5th, 2014
Samsung has posted their DDR4 product guide on their website, and it gives us excellent insight into the direction that Samsung plans to go with DDR4 in the next few months with a lot of data that wasn’t previously publicly available.
The product guide shows us some things we have not seen in a while, like SoDIMMs with ECC, and also some new things like the first mention I have seen of commercially available TSV stacks of DDR4 devices (presumably using the 3DS extension to the DDR4 standard). This product guide would seem to indicate that the TSV 3DS DDR4 parts could have engineering samples available in Q3’14
The first page, the part numbering guide, shows us what dies have been incorporated into the part numbering scheme, which include:
– 4Gb and 8Gb dies
– X4 and X8 width (no mention of X16 width parts)
– Flip Chip and DDP (Dual Die Package) packages
– Commercial temperature range (0-85c) & normal power
– DDR4-2133 speed grade with 15-15-15 timing
– DDR4-2400 speed grade with 17-17-17 timing
No mention was made of:
– X16 width (although page 6 hints at the availability of an X16 device)
– Extended temperature range
– Reduced power
– Speeds above DDR4-2400
The second page, the component product guide, shows 4Gb dies in X4 and X8 width as available now, and 8Gb dies in X4 and X8 width with engineering samples in 3Q’14
The third page, the module ordering information, shows us what modules have been incorporated into the module numbering scheme, which include:
– RDIMMs, LRDIMMs, and SoDIMMs
– 288-pin format RDIMM and LRDIMM; 260-pin format SoDIMM
– 72-bit width DIMMs (these are typically used as 64 bits data with 8 ECC check bits in servers and other devices with enterprise-class reliability requirements)
– Memory Buffer chips from IDT and Montage
It appears that the module ordering information may not be fully up to date with the information in the module product guide that follows.
Pages 5-6, the module product guide, describes in total 22 different DIMMs (of which 14 have part numbers and 8 have TBD part numbers). Highlights are:
– ECC RDIMMs in 8GB and 16GB using 4Gb X4 devices, 1 and 2 ranks respectively, MP availability
– ECC RDIMM in 8GB using 4Gb X8 device, 1 rank, MP availability
– ECC RDIMMs in 16GB and 32Gb using 8Gb x4 devices, 1 and 2 ranks respectively, ES in 4Q’14 and 3Q’14 respectively
– ECC RDIMMs in 64Gb and 128Gb using 4H TSV packaging, 8 ranks, 4Gb and 8Gb per die respectively, ES 3Q’14 and 1Q’15 respectively.
– VLP ECC LRDIMM of 32GB and 64GB, DDP (Dual Die Packages), X4 organization, 4 ranks, 4Gb and 8Gb dies respectively, MP availability and ES 4Q’14 respectively
– VLP ECC RDIMM of 16GB, DDP (Dual Die Packages), X4 organization, 2 ranks, 4Gb dies, MP availability
– ECC SoDIMMs of 8GB and 16GB, dual-rank X8 parts, using 4Gb and 8Gb dies respectively, with MP and ES 4Q’14 availability respectively
– non-ECC SoDIMMs and uDIMMs of 4GB and 8GB using 4Gb X8 dies, 1 and 2 ranks respectively, on CS availability
– non-ECC SoDIMM and uDIMM of 4GB using one rank of X16 8Gb die, ES 3Q’15 and ES2Q’15 respectively
– non-ECC SoDIMM and uDIMM of 8Gb using one rank of X8 8Gb die, ES 3Q’15 and ES2Q’15 respectively
That’s quite a list!
You can read the whole product guide here.
DDR4 is coming. Be ready! Talk to us about how we can help with your SoC designs supporting DDR4.
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | Comments Off
Posted by Marc Greenberg on September 2nd, 2014
Since last week’s announcement of Intel CPUs supporting DDR4, the first almost-announcement of a DDR4 machine by a major PC manufacturer that I have found is the Alienware Area-51 (Alienware is a Dell subsidiary). I say almost-announcement because at the time of writing this blog, Alienware’s website didn’t include any details of when it will be available for sale, or how much it would cost, or anything like a press release on it. The machine will be capable of running up to three 4K monitors simultaneously and support up to 32GB of DDR4 memory running DDR4-2133.
One could argue that ASUS is first to market, being a major PC manufacturer, and having announced three motherboards with the Intel X99 Chipset and capable of using DDR4 - in fact, these motherboards are designed to be DDR4-only because of incompatibility between the DDR3 DIMM socket and the DDR4 DIMM socket. However, I don’t see an Asus machine using these motherboards on their website yet, so it appears that the motherboards will be sold to enthusiasts and system integrators until the market builds for a machine capable of using the new Intel CPUs and DDR4.
Of course ASUS aren’t the only game in town… this excellent article over at Tweaktown compares 26 different X99-based motherboards capable of DDR4.
Now that we’ve discussed the first things first, we can discuss what’s the fastest. Remember that Intel presently validates DDR4 devices up to DDR4-2133 data rate (2133MT/s). However, if something is worth doing, it’s worth overdoing, and the folks over at G.SKILL announced they overclocked an Intel CPU on an ASUS motherboard with their new Ripjaws 4 DDR4 DIMMs to achieve a data rate of DDR4-4004 (4004MT/s)… with a little help from some liquid nitrogen to cool it down! I wonder how long it ran for…?
Posted in DDR4, DIMM, DRAM Industry, Uncategorized | Comments Off
Posted by Marc Greenberg on August 29th, 2014
As predicted in my earlier blog entry, today is the official launch of Intel’s products supporting DDR4.
The press release is here: Intel Press Release and it seems to match earlier predictions on the release of the new eight-core desktop processor, the Intel® Core™ i7-5960X processor Extreme Edition, formerly code-named “Haswell-E”. Other than DDR4, Intel reports that this CPU and its associated X99 chipset will support 10 SATA 6Gb ports and 40 lanes of PCIe.
Along with the announcement, Intel have posted their DDR4 memory validation results here, showing compatibility with DDR4 UDIMMs from Micron, Crucial, Samsung, SK Hynix and Kingston, in 4GB single-rank and 8GB dual-rank capacities, all using 4Gb X8 DDR4 devices running at DDR4-2133 data rate, 1 DIMM per channel, and running all 4 channels.
Although Intel says the will be available next week, at the time of writing at least one online retailer claims to have them available now at $1085.54 and with 170 available.
Let the DDR4 begin!
Posted in DDR Controller, DDR4, DIMM, DRAM Industry | Comments Off
Posted by Graham Allan on August 25th, 2014
JEDEC officially published the LPDDR4 standard today. It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication. That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the “PC” SDRAM market. The JEDEC committees responsible for this latest publication should be very proud of their achievement. Most of the people on these committees have “regular day jobs” outside of JEDEC and the support from the various companies involved is also appreciated.
The new standard can be found at the bottom of the page here
LPDDR4 is an interesting DRAM product. As soon as you get to page 2 of the standard (page 6 of the PDF file), you will notice a “pad order” figure. What may not be so obvious from the diagram is that LPDDR4 is designed to be a single 32-bit wide die with two independent 16-bit wide channels. This is the first traditional “DDR” SDRAM that defines more than one channel for the die. There are also 64-bit versions of the packages which include two die inside for a total of 4 independent 16-bit wide channels. Each channel has its own address/command lane. Since LPDDR4 is a 16n prefetch device (every read/write access 16 words of data), one read or write operate accesses 16 words x 16-bits or 256bits or 32Bytes of data. That is the same as LPDDR3 which is a 32-bit channel with an 8n prefetch (8 words x 32-bits). LPDDR4 is designed to operate with independent 16-bit channels which means is it not directly compatible with LPDDR3 which uses 32-bit channels in the 64-bit device or DDR4 which only ever has one channel per device. SoCs that need to interface to multiple types of DRAMs including LPDDR4 will need to incorporate the flexibility to be optimized for the type of DRAM being used.
Some of the other new features of LPDDR4 include:
- Support for data rates up to 4266Mbps
- A 1.1V operating supply (LPDDR3 and DDR4 are 1.2V)
- The address command lane is very narrow (6 bits for address/command plus clock, chip select, CKE and ODT) and it is single data rate. Multiple clock cycles are required to transfer commands (4 clock cycles for a read or write)
- Ground terminated signaling (DDR4 & LPDDR3 use VDDQ termination, DDR3 uses midpoint termination)
- A new DMI function which combines data bus inversion and data mask functionality giving you the best of both worlds (with DDR4, only one or the other function can be supported as programmed into the device)
- Two “Frequency Set Points” that support switching between two frequencies without ever being in an untrained state
The DRAM vendors are working diligently to make LPDDR4 SDRAM available. Keep your eyes out for their press releases announcing their products.
Synopsys has LPDDR4 IP available for the host devices needing to interface to LPDDR4 and other types of SDRAMs. Contact us for more information.
Posted in DDR Controller, DDR PHY, LPDDR4 | Comments Off
Posted by Marc Greenberg on August 20th, 2014
Following today’s event in Seoul, there are still two more JEDEC LPDDR4 Workshops and Mobile Forums coming up in the next few weeks.
This Friday (August 22nd) there will be an event in Hsinchu, Taiwan, followed by the Santa Clara CA event on Sept 22-23. More details here
Synopsys will be presenting “Using LPDDR4 Multi-Channel Architecture for Performance and Power” at the LPDDR4 workshops, being presented today (August 20) by HB Choi in Seoul, Friday by Tom Liu in Hsinchu, and on Sept 23 by me (Marc Greenberg) in Santa Clara.
Graham and I both plan to attend the Santa Clara event – please be sure to come by and say “Hi” and ask us any DDR questions you may have.
Posted in DDR Controller, DDR PHY, DRAM Industry, Low Power, LPDDR4 | Comments Off
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