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Committed to Memory
  • About

    This memorable blog is about DRAM in all its forms, especially the latest standards: DDR3, DDR4, LPDDR3 and LPDDR4. Nothing is off limits--the memory market, industry trends, technical advances, system-level issues, signal integrity, emerging standards, design IP, solutions to common problems, and other stories from the always entertaining memory industry.
  • The Authors

    Graham Allan

    Graham Allan is the Sr. Product Marketing Manager for DDR PHYs at Synopsys. Graham graduated from Carleton University's Electrical Engineering program with a passion for electronics that landed him in the field of DRAM design at Mosaid in Ottawa, Canada. Beginning at the 64Kb capacity, Graham worked on DRAM designs through to the 256Mb generation. Starting in 1992, Graham was a key contributor to the JEDEC standards for SDRAM, DDR SDRAM and DDR3 SDRAM. Graham holds over 20 patents in the field of DRAM and memory design.

    Marc Greenberg

    Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 10 years of experience working with DDR Design IP and has held Technical and Product Marketing positions at Denali and Cadence. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology roles in Europe and the USA. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.

Qualcomm announces first application processor with LPDDR4 capability

Posted by Marc Greenberg on April 16th, 2014

This happened a little bit quietly last week – but Qualcomm has announced the first product that I’m aware of that will use LPDDR4 memory.

The processor is the Snapdragon 810 and you can read the press release here.

Naturally, these devices support the latest 64-bit mobile CPUs, native 4K video, image sensors up to 55MP, HDMI 1.4, Cat6 LTE, USB 3.0, Bluetooth 4.1, UFS Gear2, eMMC 5.0, SD 3.0 (UHS-1) and 802.11AC; all manufactured on 20nm process technology.

The memory performance is LPDDR4 1600MHz (assuming 3200Mbps data rate) with 2 64-bit channels giving an aggregate bandwidth of 25.6GByte/sec bandwidth according to the spec sheet here.

Qualcomm says that these products, the Snapdragon 810 and its sister product the Snapdragon 808, will “begin sampling in the second half of 2014 and expected to be available in commercial devices by the first half of 2015.”

Roll on, LPDDR4!

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Posted in DDR Controller, DDR PHY, IP, Low Power, LPDDR4, Uncategorized | No Comments »

Two DDR Tidbits

Posted by Graham Allan on April 7th, 2014

The definition of tidbit is:

1:  a choice morsel of food

2:  a choice or pleasing bit (as of information)

I’m going with the second one here.

DDR Tidbit #1

Did you happen to see last week’s episode of The Big Bang Theory called “The Indecision Amalgamation” that includes DDR memory getting a shout out?  At one point, the show featured Emmy award winning ultra-nerd Sheldon Cooper talking to his girlfriend Amy about his video game purchase dilemma – whether to buy the PS4 or the XBOX One.  Sheldon quips that he doesn’t think Amy is paying proper attention to his problem.  She apologizes and then feigns interest with overly enthusiastic responses as Sheldon explains the memory each system uses (DDR3 versus GDDR5).  The brief and comical exchange can be viewed at http://youtu.be/ue8eeQMar1M

DDR Tidbit #2

On a more serious note, DRAM vendor Micron Technology has a wonderful web site that is loaded with very useful information if you know where to look.  Some of the most useful information found there are their DRAM related application notes which Micron calls “Technical Notes”.  I have recently discovered a new one about DDR titled “Using DDR4 in Networking Subsystems”.  The name is a bit misleading and it is definitely worth a read as it contains an excellent overview of DDR4 and many of the new features found in DDR4 (15 pages worth!) and ends with design considerations for a few typical networking applications.  This document can be found at http://www.micron.com/-/media/Documents/Products/Technical%20Note/DRAM/tn_4003_DDR4_network_design_guide.pdf.  Be sure to look through the other technical notes from the past, there are some nuggets in there.  Thanks, Micron.

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Posted in DDR3, DDR4 | No Comments »

Intel announces DDR4 support

Posted by Marc Greenberg on March 20th, 2014

This is a big day for DDR4: For the first time, Intel has announced DDR4 support in their desktop CPU roadmap.

If you have been paying attention to other sources (or if you have private access to data as I do) then you’ve known that Intel has been working on DDR4 for a while, and DDR4 was shown at Intel Developer Forum last year.

Intel has announced:
– An 8-core desktop processor, “New Intel® Core™ i7 Processor Extreme Edition” (Codename Haswell-E) as the first desktop platform supporting DDR4 memory, with availablity in 2H2014
– A 5th generation Intel® Core™ processor with Intel® Iris™ Pro (Codename Broadwell) based on 14nm manufacturing process

I’ll be doing a blog on Iris Pro shortly…

You can read the whole presentation from Intel here:
http://www.intel.com/newsroom/kits/desktop/2014/pdfs/DT_press_day_briefing.pdf

Marc

A slide from Intel's presentation at http://www.intel.com/newsroom/kits/desktop/2014/pdfs/DT_press_day_briefing.pdf - Page 25

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Posted in DDR4, DRAM Industry, Uncategorized | No Comments »

The first DDR4 DIMMs are for sale!

Posted by Marc Greenberg on March 19th, 2014

I think I have found the first DDR4 DIMMs available for consumer purchase anywhere. Crucial and a few others were showing DDR4 DIMMs at this year’s Consumer Electronics Show (CES) in January, so it’s nice to see that they translated into real products.

Engineering samples of DDR4 have been available for some time (Synopsys has several DDR4 devices that we used to characterize our DDR4 PHY testchips), but as far as I know this Crucial DIMM is the first publicly available DDR4 module. If you know of an earlier example of where a consumer could buy a DDR4 DIMM, please post it in the comments.

As I write this (March 19, 2014), through the link at crucial.com, $445.99 plus tax and shipping will get you two single-rank 8GB DIMMs, each DIMM composed of 18 of 4Gb 4-bit wide, 1.2v DDR4-2133 parts with CAS Latency 15, plus a Memory Buffer chip (that makes it a registered DIMM) and a Serial Presence Detect (SPD) chip plus some ancilliary components.

One thing to note is that the DDR4 module mentioned above is very clearly intended for servers. Support for X4 DRAM parts, Error Correcting Codes (ECC) and Registered DIMM are all features from the server/enterprise space that don’t commonly get used in consumer/desktop/notebook computers and are generally not supported by consumer CPUs nor consumer motherboards. That ties up very well with Synopsys’s predictions that DDR4 will enter the server/enterprise space first and then gradually make its way into the consumer market.

This module, albeit perhaps the first of its kind publicly available for purchase, is substantially more expensive than a similar consumer-grade DDR3 DIMM. The big question is: Why would you buy this DDR4 DIMM? There are a few possible reasons:

– You are validating some kind of system that will use DDR4 in the future
– You have an application where the reduced power consumption of DDR4 is important to you (Crucial says these DDR4 modules use 40% less power than their DDR3 equivalents)
– You are building a high-reliability, high-performance server
– You want to be the first to tell your online gaming buddies that you have a DDR4 rig

Let’s look at each of these in turn.

The first thing I want to point out is, you need a motherboard that supports DDR4 to use a DDR4 DIMM. In fact, as I searched the web today, I couldn’t find a single motherboard for sale that could accept a DDR4 DIMM… Nor a CPU from the major desktop CPU manufacturers whose datasheet says it’s DDR4-compatible… We know they are coming in the near future, so let’s assume that you’ve solved that problem, or that you’re reading this blog post at some point in the future when some DDR4 Motherboards are available.

If you are validating a DDR4 system, then you need DDR4 to do it of course – so that’s an easy decision.

The power consumption of DDR4 is attractive for many types of systems. The memory in most computing devices uses a large percentage of the total system power and being able to reduce the power has many benefits. If we’re comparing with DDR3-2133 modules that are available today, the DDR3 modules available today fall into two categories:
– DDR3 DIMMs where the DDR3 parts on the DIMM were marked by the memory manufacturer for DDR3-2133 data rates. Typically the manufacturer would have speed-sorted these devices at the time of manufacturing and these would generally be from the fast process corner which is also typically the high leakage corner and also typically the high power process corner.
– Overclocked DDR3 DIMMs where the DDR3 parts on the DIMM were marked by the memory manufacturer for a speed lower than DDR3-2133 and which have been speed-sorted by the DIMM manufacturer and/or respecified to run at a higher-than-normal voltage of 1.6v or even 1.65v, which burns more power than 1.5v.
– I was not able to find any low-voltage (1.35v) DDR3L DIMMs specified higher than DDR3-1600 speeds.
Compared to these devices, we can certainly expect less power per bit from the 1.2v IOs on the DDR4 DIMM, as well as the Data Bit Inversion function of DDR4, if you have a motherboard to support DDR4.

If you are building a high-performance, high-reliability server, this DDR4 DIMM could be attractive. Crucial’s DDR4-2133 DIMM is a registered DIMM with X4 DRAMs and ECC; whereas the fastest DDR3 DIMM I could find with those features was DDR3-1866. In the high-reliability server space, end-users are reluctant to overclock their DRAM parts, so this DDR4-2133 DIMM could be attractive by potentially offering more bandwidth than DDR3-1866 if you have a motherboard that can support it. In addition, many of the “RAS” features of DDR4 – Reliability, Availablity, Serviceability – are intended for use in high-reliability systems. Check out my recent Electronic Design article for more.

If your objective is to be able to brag about your DDR4 rig to all of your online gaming buddies (assuming that you can find a motherboard that supports it), if you have a technologically savvy group they’re likely to point out the following:
– The latency of this DIMM, at 15 clock cycles, is higher than most of the overclocked DDR3 DIMMs
– Overclocked DDR3 DIMMs are available that are rated by the DIMM manufacturers to run at higher speeds than 2133MT/s (I’ve seen some at 3000MT/s and one claiming 4000MT/s operation)
– The memory buffer on a registered DIMM adds latency compared to unbuffered DIMMs.
– The bank group arrangement in DDR4 is a new twist on memory scheduling, and unless the memory controller in the CPU is optimized for DDR4 bank groups, you’re likely to have lower bandwidth from DDR4 than DDR3 at the same clock frequency. On the other hand, when taking proper advantage of the DDR4 bank groups, it may be possible to get more bandwidth than DDR3. Shameless plug and/or a topic for another day: feel free to ask how you can take proper advantage of DDR4 bank groups in Synopsys’s uMCTL2 memory controller!

So there we have it: after 10 years of development, the first DDR4 DIMM for sale. Now you just need to find a motherboard for it…

Marc

I have to remind everyone that Synopsys does not specifically endorse any particular DIMM manufacturer or online retailer.

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Posted in DDR Controller, DDR PHY, DDR3, DDR4, DIMM, DRAM Industry, Uncategorized | No Comments »

“How Fast Can My DDR Go?”

Posted by Graham Allan on February 3rd, 2014

As a provider of DDR PHY and controller IP, the question we get asked the most goes something like this:  “Will your PHY support a {insert short description of system here} at {fill in the speed here} Mbps?  Lately, I am receiving a lot of questions around DDR4 such as “Will your DDR4 PHY support one dual rank UDIMM at 2667Mbps”?

Unfortunately, the answer is never what someone wants to hear.  The answer is usually “It depends”.  For example, DDR4 at 2667Mbps is a very high data rate for a parallel, single ended, 72-bit channel populated with 2 ranks of 4-bit wide SDRAMs.  That is a load of 2 SDRAMs per bit of data and 36 SDRAMs on the address/command bus!  That’s why RDIMMs and LRDIMMs were invented – to isolate the address/command (RDIMM) and data (LRDIMM) loading from the channel.

The maximum speed in such systems is not only a function of the PHY but rather the signal integrity of the entire system – PHY, SoC, package, PCB & DRAMs.  For example, in heavily loaded, multi-rank systems, the additional loading on both the address/command and data buses leads to a slower edge rate, which reduces the eye width, degrading the setup and/or hold time required by the SDRAM.  This impact must be taken into consideration during the signal integrity analysis of the timing for the interface as this reduction in eye width leads to a smaller data capture window.  Traffic dependent effects such as SSO (Synchronously Switching Outputs), crosstalk, and ISI (Inter-Symbol Interference) must also be taken into consideration.

Factors to take into consideration when analyzing a system for maximum speed include the package type (QFP?  BGA?  Wire bond?  Flip chip?), number of PCB layers, track spacing (in the package substrate and the PCB), amount of on-die decoupling, PHY power:signal ratios, package power:signal ratios, PHY deskew capability, operating conditions (PVT), etc.

An analogy I frequently use is one with cars and their maximum speed.  What if your friend asked you how fast can your car go?  How would you answer?  Even if you own the fastest production car in the world, something like the Bugatti Veyron Super Sport, you have to think about the answer.  How fast can it go if the road has sharp bends?  How about a dirt road?  Is it raining?  Is it snowing?  Is there other traffic on the road?  Are the tires inflated properly?  You get the idea.  Maximum car speed and DDR speed require similar qualification.

Once you have defined the entire DDR sub-system, only then can you proceed with a signal integrity analysis to verify if the target speed can be met with confidence.  That confidence comes from a series of timing budgets.  Each timing budget contains uncertainty contributions from the transmitter, the channel or interconnect, and the receiver.  For each timing budget, the SoC’s DDR PHY only contributes to the transmitter uncertainty or the receiver uncertainty depending on if you are writing or reading, respectively.  Everything else comes from the DRAM data sheet or the physics of the channel.  If, once you add up all the uncertainties, you have less than one bit period (e.g., half a clock period for the DDR data channel), then your timing budget passes.  Note that many timing budgets fail because they assume everything bad can happen at the same time which is virtually impossible in real life.  Typically, some of the dynamic uncertainties (those impacted by data pattern or operating frequency) need to be tamed in the analysis to avoid an overly pessimistic timing budget.

For more information on timing budgets for DDR interfaces, check out the Synopsys white paper at http://www.synopsys.com/dw/doc.php/wp/ddr_signal_integrity_wp.pdf.  This white paper may be from 2009 but the concepts are the same and apply more today than they ever have!  Then check out the ten tips to success for your SoC’s DDR Interface at https://www.synopsys.com/dw/doc.php/wp/ddr_top10_wp.pdf.

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Posted in DDR Controller, DDR PHY, DDR4, DIMM, IP, Signal Integrity | Comments Off

Happy 10th Birthday DDR4!

Posted by Graham Allan on January 13th, 2014

Believe it or not, work the DDR4 standard was first started back in 2004.  That’s now 10 years ago!  Happy 10th birthday DDR4.  10 years ago Facebook was started up, there was no Twitter (2006), no iPhone (2007), and Google went public for $85/share (it is now $1,123/share).  Even after those 10 years, you can’t go out a buy a computer with DDR4 in it.  The JEDEC standard for DDR4 was published in September 2012 so why isn’t everyone using it?  Why did it take so long?

That’s a long complicated story.  Fundamentally, it’s just plain hard to make a single ended, wide parallel interface operate at the data rates envisioned for DDR4.  Physics is getting in the way as the nanoseconds gave way to picoseconds and fewer and fewer of them.  The traditional wide DDR SDRAM interface is running out of headroom and the system design compromises to enable such high speeds are getting expensive.  It took a lot of bright engineers a long time to figure out what features are required in DDR4 to make it work in systems, and then agree on what was required, and then agree on how to tell other people what was required (e.g., write the standard).  In my opinion, DDR4 is the most complicated DRAM standard transition since asynchronous DRAM gave way to the SDRAM in the mid-1990s (and that took 5 years from first work on the standard to computers shipping with it).

Also, for most PCs, laptops and embedded applications – DDR3 has been good enough when you consider price, latency, performance, etc.  But, as it always is in the DRAM game, it’s mostly about price!  Only servers crave DDR4 for the lower power the SDRAM offers and only servers are willing to pay for it.  Higher data rates are nice but it’s the lower power that is most attractive.  DDR4 is the first DRAM standard that does not target PCs and laptops for the first application market.  Since DDR4 really targets servers first, that is a smaller segment of the DRAM market so the TAM for DDR4 is smaller than it was for DDR3 and will remain so until DDR4 ends up in laptops and PCs (both of which are declining markets themselves).  That is a chicken and egg problem.  Laptops and PCs will not embrace DDR4 until it becomes cheaper than DDR3 yet the shrinking TAM for DDR4 means the volume will not ramp very quickly and volume largely determines the price in the DRAM market.

So basically, there is nowhere for DDR4 to go yet and the future is only bright-ish.

Add to the complex equation that consumers are abandoning PCs and laptops for ultrabooks, tablets and smartphones which use lower power mobile SDRAMs such as LPDDR2 and LPDDR3.  The volume for LPDDR2/3 is ramping up while the volume for DDR3 is waning.  There is a lot more industry momentum around the mobile DRAMs (e.g., LPDDR2/3/4) than there is around the “PC” memories (e.g., DDR3/4) because the volumes are increasing and the prices are higher for mobile DRAMs.  More of anything at a higher price is attractive if you sell that thing!  However, nothing lasts forever and as the memory market volumes teeter towards mobile DRAMs and away from the PC DRAMs, I predict the prices of mobile DRAMs will fall, eventually to below the price per bit level of the PC DRAMs.  This will likely happen within the next 2 years.

Finally, back to that DDR4 standard…  For anyone who is familiar with the DDR4 standard, it does not define the 3200Mbps data rates that most articles about DDR4 talk about.  How many times have you read that DDR4 is twice as fast as DDR3?  That was true back when DDR3 was only standardized up to 1600Mbps.  DDR3 has since been enhanced to accommodate data rates of up to 2133Mbps.  The maximum speed for the current DDR4 standard is 2400Mbps (only 13% faster than the maximum speed for DDR3).  In fact, 3200Mbps, once we get there, is only 50% faster than DDR3.  There are also some other areas where the standard is not complete.  JEDEC has been working diligently to update the standard – that cat was let out of the bag in a recent EEtimes article: http://www.eetimes.com/author.asp?section_id=36&doc_id=1320534&itc=eetimes_sitedefault&cid=NL_EET_Daily_20140103&elq=10ac88effa334363983119d0e84ed904&elqCampaignId=3302.  One of those updates is likely to be for the speed grades above 2400Mbps.

DDR4 will have a future, but it will never be the DRAM “rock star” that DDR3 is.  DDR3 has already been the king of DRAMs for longer than DDR2 was and it still has a long runway ahead of it.  Long live the King!

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Posted in DDR4, DRAM Industry, Low Power, LPDDR3, LPDDR4, Signal Integrity | 3 Comments »

When is LPDDR3 not LPDDR3? When it’s DDR3L…

Posted by Marc Greenberg on January 10th, 2014

Laptop Shipping Label

This is the shipping label from the laptop I bought, showing 8192MB of LPDDR3 SDRAM

For years, I have been predicting that Low-Power DDR (LPDDR) devices would make the crossover from mobile devices into laptops.

That prediction came true last year when a MacBook Air was introduced that uses LPDDR3 as it’s main memory.

I recently purchased a fairly powerful Windows 8 laptop for home use and I was surprised to see on the shipping label that it was purported to contain 8GBytes of LPDDR3 SDRAM, as you can see in the above photo (manufacturer’s name obscured for reasons that will become clear later).

After having contributed to the LPDDR standards at JEDEC for years and predicting their arrival in laptops for some time, I was pretty excited to become the second person in my household to own a device containing LPDDR3 (as I blogged earlier, my Wife gets all the good tech in the Greenberg household). In fact, the 4th generation Intel Core (TM) processor in my laptop does support LPDDR3 devices, according to its databook.

Alas, it was a little too good to be true. Digging in to the laptop’s service and maintenance manual, I found that the memory in my new laptop was actually DDR3L and not LPDDR3. I’m sure it was an honest mistake on the part of the laptop manufacturer and not an intent to mislead anyone; I am probably one of a handful of people in the world where the kind of memory inside would influence my purchasing decision. It’s also partly true; DDR3L is a lower-voltage (and thus lower power) version of DDR3, but the term “LPDDR3″ refers to a specific DRAM implementation that is not DDR3.

So what’s the difference between DDR3, DDR3L and LPDDR3? I get that question a lot, and there are a lot of differences. I have summarized some of the key differences in the table below. The short summary is, LPDDR3 is more expensive but has much lower standby power and a better form factor for mobile devices; while DDR3 and DDR3L are less expensive and consume more power but are more suitable for larger memory arrays found in PCs and servers.

How’s the laptop? Great, I love it. It replaces an aging desktop, so the use model is similar to the old desktop, but with the added benefit of being more portable around the house. I’ve seen people carrying around 17″ laptops before I didn’t appreciate how big it really is until I owned one. It’s got a giant battery and it’s never far from a power socket, so I don’t miss the power savings from LPDDR3 at all in this laptop, but I will definitely be looking for LPDDR3 or LPDDR4 in my next mobile device purchases.

DDR3-DDR3L-LPDDR3 Comparison

Comparison between DDR3, DDR3L and LPDDR3 Devices

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Posted in DDR3, DRAM Industry, Low Power, LPDDR3 | Comments Off

The first LPDDR4 Device: Now there are three winners

Posted by Marc Greenberg on January 7th, 2014

Last week I blogged on how Samsung and SK Hynix had both issued LPDDR4 press releases on the same day.

I just read the transcript of tonight’s Micron earnings call (Jan 7th, 2014), and within it, Micron’s President Mark Adams is quoted as saying, “We are also the first supplier to sample low-power DDR4 to our customers and chipset partners.” (Source: http://seekingalpha.com/article/1933411-micron-technologys-ceo-discusses-f1q-2014-results-earnings-call-transcript?page=5 )

So now we have three claims:
Samsung: “…developed the industry’s first eight gigabit (Gb), low power double data rate 4 (LPDDR4), mobile DRAM…” (Source: Samsung Press Release )
SK Hynix: “…developed the world’s first 8Gb(Gigabit) LPDDR4(Low Power DDR4)…” (Source: SK Hynix Press release )
Micron: “We are also the first supplier to sample low-power DDR4 to our customers and chipset partners.” (Source: Micron Earnings Call Transcript )

Who was actually first? We may never know…

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Posted in Uncategorized | Comments Off

LPDDR4: The battle is on, but who drew first blood?

Posted by Marc Greenberg on January 2nd, 2014

Happy New Year to all our blog readers!

My mailbox was full of LPDDR4 announcements this morning as both Samsung and SK Hynix made press releases on LPDDR4 availability on the same day this week.

In fact, both companies’ press releases announced that they had developed the first 8Gb LPDDR4 device, which creates a question – who actually made the first one?

The answer to that question is likely known to a very small number of smartphone OEMs, but we can look at the data available to us to come close to an answer.

Firstly, a quick primer on LPDDR4:
- LPDDR4 is expected to be the follow-on DRAM memory to LPDDR3,
- LPDDR4 is expected to be used in high-end smartphones and tablets,
- LPDDR4 is expected to have double the bandwidth per pin of LPDDR3,
- LPDDR4 is expected to have a new 1.1v LVSTL I/O standard with a 350mV swing that should reduce power per bit transferred,
- LPDDR4 is expected to have 2 16-bit channels and 16 banks per die,
- JEDEC (the memory standards body) is working towards a published standard for LPDDR4 in 2014
Graham and I attend LPDDR4 standard task group meetings at JEDEC and we’re bound by confidentiality rules so I can’t make any definitive statements on the forthcoming standard beyond what’s already published online.

I can tell you that my private discussions with several smartphone chipmakers and OEMs last year indicated that they were expecting to receive LPDDR4 engineering samples from memory manufacturers in the first half of 2014. Those same smartphone chipmakers are already designing LPDDR4 interfaces into their next-generation smartphone chipsets. The press releases from Samsung and SK Hynix are totally believable in that context.

One might also ask, “Where is Micron in all this?” I searched the Micron website this morning for any LPDDR4 announcements and found none, however, that doesn’t mean that they’re not doing anything. As one of the three largest DRAM manufacturers, and with a relatively small number of first adopters for LPDDR4 devices, Micron may be marketing directly to their customers instead of making press releases. Having said that, Micron have added LPDDR4 parts to their part numbering scheme and created part numbers for speeds up to 2133MHz (4266Mbps data rate or 17GByte per second per die). Dan Skinner from Micron made an excellent presentation on LPDDR4 at the JEDEC Mobile Memory Forum in May 2013. You may draw your own conclusions.

Now let’s break down what was actually announced in each of the Samsung and SK Hynix press releases.

What was announced Samsung SK Hynix
Development schedule “…developed the industry’s first eight gigabit (Gb), low power double data rate 4 (LPDDR4), mobile DRAM…” “…developed the world’s first 8Gb(Gigabit) LPDDR4(Low Power DDR4)…”
DRAM Density 8Gb 8Gb
DRAM Speed “…the LPDDR4 chip will enable a data transfer rate per pin of 3,200 megabits per second (Mbps)…” “This new product works at 3200Mbps…”
Process Technology 20nm class 20nm class
Availability “…will provide its new 8Gb LPDDR4 DRAM in 2014…” “The new interface LPDDR4 is expected to be loaded onto flagship mobile devices at the end of 2014…”
Press Release URLs Samsung Press Release SK Hynix Press Release

So we can see the press releases are quite similar. Hynix announced that they’re “providing the samples of LPDDR4 to major customers”. Separate from this press release, the advance program for ISSCC in February 2014 includes a paper from Samsung on a 1.0v 3200Mbps LPDDR4 device indicating progress to reduce the I/O voltage from 1.1v to 1.0v and a core voltage reduction to under 1v.

So which of the three major DRAM manufacturers was actually first to have a working LPDDR4 device in their lab? We may never know. Who delivered the first LPDDR4 engineering sample to a smartphone chipset maker or OEM is only known to a handful of those customers. What’s important is that LPDDR4 is clearly coming and you should consider whether LPDDR4 makes sense for your next product. If you’re starting a new chip design that uses DRAM, you should ask Synopsys how we can help you succeed with LPDDR4 and other high-speed interfaces.

– Marc Greenberg

This post was edited to provide more obvious links to the Samsung and SK Hynix press releases.

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Posted in DRAM Industry, Low Power, LPDDR3, LPDDR4 | Comments Off

Could mobile DRAM exceed PC DRAM shipments in 2014?

Posted by Marc Greenberg on November 19th, 2013

Mobile DRAM has certainly come a long way in the last few years, but I didn’t expect to see this prediction quite so soon, that “…the shipment of mobile DRAM is likely to officially surpass that of PC DRAM in 2014“.

That quote, from the DRAMeXchange research division of TrendForce, would cap off an amazing run of popularity for mobile memory if it proves to be true.

The history of mobile DDR DRAM memory is proof that great things can come from humble beginnings.

There were manufacturer specifications for mobile DDR DRAM long before there was a JEDEC spec for it. The first LPDDR specifications (sometimes called LPDDR1, mDDR) which were very similar to the DDR standard (“DDR1″) that was being used in the PCs of the day, the main differences being reduced standby power, the lack of a DLL in the LPDDR parts, and (for me) the annoying property that the CKE pin needed to be driven oppositely for LPDDR parts compared to DDR parts at bootup. LPDDR was several years behind DDR in specification maturity and LPDDR didn’t even get its own JEDEC specification number (JESD209) until 2007, before that it was considered by JEDEC as a variant of the PC DRAM and given a JESD79 standard number like the PC DRAMs.

LPDDR2 was an amazing and difficult effort. A small group of people were regular attendees of the JEDEC JC42.6 subcommittee meetings – I attended more than a dozen in-person meetings and countless calls – and we struggled to get meeting space, time on the agenda, and tried to avoid getting sucked into the mainstream PC DRAM proceedings while we explained why LPDDR2 had to be different from DDR2. We had to invent an IO, and let this be my public apology for the name “HSUL12″ (High Speed Unterminated Logic) which I proposed for the LPDDR2 IO, but in my defense I will say it was the best option, and none of us predicted that HSUL12 would eventually become a terminated IO at the higher speeds of LPDDR3.

Suddenly there was this pressure to make LPDDR2 faster, and we didn’t believe it could be done, until several smart people on the committee figured out that if you were to terminate the IOs, reduce the IO capacitance, and provide a means of training the interface, that you could make an LPDDR3 that was as fast as DDR3.

Before the JEDEC committee was done with LPDDR3, there was the pressure for LPDDR4, and although DDR4 is hitting the market first, it appears that LPDDR4 will be faster than DDR4, which is also quite a turn of events. And people are already looking at what comes next…

It would be pretty amazing to me to see if mobile DRAM does indeed exceed PC DRAM shipments. I had always hoped for it, but never predicted it as soon as 2014.

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Posted in Low Power, LPDDR3, LPDDR4 | Comments Off