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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

FPGA-Based Prototyping in Real Time

Posted by Michael Posner on February 2nd, 2014

In a recent customer meeting they described how they used FPGA-Based prototyping and explained the two use models. It was an interesting exchange which I thought would also benefit the blog readers. The two use modes were described as “real time” and “functional” prototyping.

In reverse order, functional prototyping is what I think of as traditional prototyping. The clocks are scaled but still the highest performance model of the SoC with the goal of early software development and ensuring the hardware is validated against the software. HW/SW integration and System Validation are all possible with the FPGA-based prototype.

The other use model, real time, is the one that promoted me to discuss this on the blog as I sometimes forget this usage model. The customer has a very specific need to tune an analog circuit which requires high performance real time operation to get accurate results. The part of the SoC modeled for this purpose is cut down to the bare necessities. This design then utilized the high speed transceivers of the FPGA to interface with the analog logic. The RTL would be tuned to reach the highest performance, in this case over 450 MHz, enabling the real time operation required. This design is a perfect fit for the new HAPS-DX systems which offers a small high performance FPGA with plenty of high speed transceiver links to connect the system to the analog circuit.

We sometimes forget the high speed analog portions of SoCs and real time FPGA-based prototyping is essential to aid the validation of the digital/analog interface. Along the same theme, one of Synopsys’ DesignWare PHY validation engineers popped into my office and explained that he had complete simulation across the HAPS-DX HT3 connectors, across 4” of FR4 then a model of a new DWC PHY board which included another 4” of FR4. After a discussion on crosstalk, reflections he drew some wiggle lines showing the wide open eye diagram at 700 MHz. Now I’m technical but after that discussion I know that while I’m comfortable with digital 0’s and 1’s I am not with analog wiggly lines.

Off-subject here is a summary of my recent car purchase experience

  • First of all I stated upfront that this is a luxury purchase with a set cash spending limit (I informed them the exact amount). I had already done my research and a used 2012 is all I could afford. After telling me the dealer had no 2012’s they started to upsell me on a 2013. Again I reminded them of my spend limit and that I was pretty sure that I cannot afford a 2013. They insisted they would work with me on the price. We walk around the car lot and then moved inside to start negotiation.
  • The car sales person lead with the standard ploy and offered a significant discounting off MSRP. I’m sorry but MSRP is “suggested” retail price engineered to provide car dealers with a starting point for negotiation. The problem was that even with the discount the price was significantly over my spending limit. I declined the offer and the sales person went off to talk to their manager.
  • The sales manager came in and said they wanted to “meet the person who would walk away from such a great deal”. Well buddy now you have, what now? I don’t fall for that one either, it’s not a good deal as it’s not within my budget. While that strategy might work with others it does not work with me.
  • Then the sales manager says, “How about you finance the extra?” Why in the world would I do that!!! I don’t “need” this car, do you people not understand that. I cannot afford this 2013, I knew that going into this but the sales person said they would work with me. This is not working with me, this is a plain old upsell.
  • Finally the sales manager shows me the “dealer” invoice stating this is what we paid for the car. The dealer invoice showed the value of this 2013 being more than they are offering to sell it to me. Give me a break, they would be out of business in if they sell cars at a loss. The dealer invoice is just another way to make the customer think they are getting a great deal. I told them that if they were really willing to sell the car at a loss then they would accept my price limit and sell me the car at that price point. They did not accept my offer.

I did not buy a car this day. The funny thing is that a day later I found a used 2012 at another dealer but it was listed at a price higher than the other dealer wanted for the 2013. I thought this fact would help me negotiate on the 2012 price…. I was wrong, they were firm on the price point. Oh well, no new track car for me.

Talking of track cars I was struggling with not having a project to work on at home. Saturday morning  I pulled together an old remote control kit with two servos, some micro switches, a dual motor gearbox and a track vehicle chassis. (Tamiya makes great kits perfect for home projects like this) Here is a picture of the electronics. Note the popsicle sticks glued to the servos with the micro switches. These operate the two motors on the dual gearbox. Very simple setup, one set controls forward and backward and the other set cut the power to one or the other motor giving the vehicle steering capabilities.

Here is the “finished” tracked vehicle. It looks like a mad scientist project. Whatever you think, it’s a lot of fun to drive around the house.

And finally a little video of it in action: http://www.youtube.com/watch?v=TPxulAEQbg0 and another with the cardboard bulldozer attachment: http://www.youtube.com/watch?v=rCh-tgi3uh8

What fun things have you built recently? Send me a comment and let me know.

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Posted in Early Software Development, HW/SW Integration, In-System Software Validation, Mick's Projects, Real Time Prototyping, System Validation | Comments Off

How To: Enable Early Software Development, Find Critical Bugs and Save Up To 6 Staff Months of Effort

Posted by Michael Posner on January 25th, 2014

Enabling early software development, finding critical bugs while saving up to 6 staff months of effort sounds like the holy grail of the design and validation. The funny thing is that it’s not a mythical creature, this is the reality of FPGA-based prototyping, specifically HAPS FPGA-based prototyping solution.

Synopsys surveyed it’s HAPS customers (Using a 3rd party called TechValidate) and asked them to describe the value they get from using HAPS. The results in my opinion were pretty overwhelmingly positive. Here is a snippet of the results.

HAPS enables early software development

HAPS helped discover critical bugs

HAPS saves up to 6 months of development effort

All the other results can be found here:

http://www.synopsys.com/IP/techfacts/haps-techfacts/Pages/default.aspx

These results show why so many companies utilize HAPS. I’m feeling lonely, please comment on the value you get from HAPS so that I have something to blog about next week

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, In-System Software Validation, Man Hours Savings | Comments Off

Reducing Risk with Pre-Silicon Demonstrations

Posted by Michael Posner on January 17th, 2014

This week’s blog is going to show you how FPGA-based prototyping delivers a whole new level of WOW factor to a new product introduction. Oh, and this also sends a message of reduced risk to the prospect customer. OK, so here we go, recently Synopsys announced the industry’s first USB Superspeed 3.1 10 Gb/s platform to platform, host to device, data transfer demonstration. Here is a link to the news release.

http://news.synopsys.com/2013-12-10-Synopsys-Demonstrates-Industrys-First-SuperSpeed-USB-10-Gbps-Platform-to-Platform-Host-Device-IP-Data-Transfer

It’s one thing to make claims in paper but delivering a real demonstration of the capability adds a whole level of credibility to the data being presented. Here are the set of videos of the real demonstrations of USB 10G transfers

 The Synopsys HAPS and DesignWare IP was also used by the USB-IF to demonstrate the new USB Superspeed 3.1 10Gb/s capability:  http://www.anandtech.com/show/7652/usbif-updates-us-on-type-c-connector-demonstrates-usb-superspeed-31-transfers

 WOW……….

I’ve mentioned this in a couple of my blogs that in addition to FPGA-based prototypes being used for early software development, HW/SW integration, System validation they are the single best pre-silicon method to demonstrate new product capabilities to your prospect customers. Seeing the product in action is far more credible and valuable than simply reading a product pitch or spec sheet. A real pre-silicon demonstration leaves the prospect customer with a feeling of reduced risk with your new product as they just saw it and played with it. (it feels far more real) The same demonstration platforms can also be delivered to the prospect customer enabling a more complete evaluation or for early software development of applications that will sit on top of this new product.

Are you using FPGA-based prototypes to deliver pre-silicon demonstrations?

Also, did you like this shorter blog or my longer more in-depth blogs which I did the last couple of times?

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Posted in FPGA-Based Prototyping, Tips and Traps | Comments Off

FPGA-Based Prototyping Best of the Best

Posted by Michael Posner on January 10th, 2014

As it’s my first blog of 2014 (Happy New year and all that) I wanted to reflect back on 2013 and what better way to do that than review the best of the best of my blog postings from 2013. So drum roll please… here is my short list of cracking blog posts from 2013 in chronological order. This is not a list of all the blogs (but it did turn out to be a big list) just the ones that I personally think have the most valuable FPGA-based prototyping information.

Also, check out my new Blog Bio Photo –> 007 Style !!

How IO Interconnect Flexibility and Signal Mux Ratios Affect System Performance

One of the “Breaking The Three Laws” is that your SoC partitioned blocks typically have more signals than physical IO’s on the FPGA. Technically this is not one of the three laws but it should have been and as I own this blog I can make one more up. Welcome to the Breaking The Four [...]

Direct Route or Take the Bus?

Last week’s blog was on direct interconnect density and the effect it has on pin mux ratios. The example focused on using HSTDM but one of the readers correctly pointed out that interconnect density effects any pin muxing scheme, not only HSTDM. The rule of thumb is the greater the density of interconnect routes the [...]

UFC: Cables Vs. PCB Traces

UFC: Cables Vs. PCB Traces With the new HAPS-70 all cable based interconnect architecture we often get asked about overall raw performance of the cables vs. PCB traces. Below is the data on the raw cable and new HapsTrak 3 connector performance. This in itself shows that the cable and connector architecture are cable of running [...]

Jim Hogan falls prey to HAPS cloak of invisibility

I used to own a Ford F350 truck and it was huge with the long wheel base, full bed, extended crew cab measuring a length of about 25 feet (8 meters). The problem was that it came installed with a cloak of invisibility. I didn’t know it had a cloak of invisibility when I purchased [...]

EDACafe Video’s and the best dressed presenter

While at DAC, EDACafe video interviewed me discussing the HAPS-70 FPGA-based prototyping solutions. You can find the video here: http://www10.edacafe.com/video/Synopsys-Mick-Posner-Director-Product-Marketing/40055/media.html I liked the interview style and the whole interview was shot in one take, no breaks and was completed in less than 5 minutes. I think you will find the video informative so please watch [...]

Complex SoC Prototyping using Xilinx Virtex-7 based HAPS-70 Systems

At the recent SNUG UK Paul Robertson from Broadcom presented a paper on their use of FPGA-Based Prototyping for their current generation of SoC’s. For those with Synopsys SolvNet access the paper can be found by following this link: http://www.synopsys.com/Community/SNUG/UK/Pages/Abstracts.aspx?loc=UK&locy=2013#C1 Based on participant votes Paul was awarded with the prestigious “Best of SNUG” award. Congratulations [...]

Understanding IP and IP to SoC Prototyping

I’m presenting at the quarterly GSA Intellectual Property (IP) Working Group Meeting this morning and while reviewing my slides I thought I would blog on a couple of aspects of IP (RTL blocks) and IP to SoC Prototyping. I’ve blogged on this topic before but it was ages ago and even I’ve forgotten what I spoke [...]

Do you use a hammer to put in a screw?

This week I was asked to compare the Synopsys HAPS systems to FPGA vendor evaluation boards. I only have good things to say about the FPGA vendor evaluation boards but when comparing these evaluation boards to HAPS for serious FPGA-Based Prototyping I just said, “That’s like using a hammer to put in a screw”. A [...]

Designing an Electrochemical Cell

A couple of folks complained that my last blogs have been a bit long and boring. (Boring! Me?) So I would like to start this week and apologize to all my 5th Grade readers, I’ll try harder in the future to use smaller words and more pictures. The good news is that this week is [...]

Accelerating Prototyping Hardware Assembly

This week I wanted to focus on a discussion around prototyping hardware assembly. Prototype hardware assembly is the process to tailor FPGA-prototyping hardware to meet the needs of the project. The first type of prototype assembly would be to build a custom platform directly matching the projects requirements. The building of prototyping hardware is the [...]

Xilinx FPGA’s for FPGA-Based Prototyping

If we look at the FPMM survey respondent data it’s clear to see that the favored FPGA device for FPGA-based prototyping is Xilinx devices This week Xilinx announced the Virtex® UltraScale™ VU440 3D IC. http://press.xilinx.com/2013-12-10-Xilinx-Doubles-Industrys-Highest-Capacity-Device-to-4-4M-Logic-Cells-Delivering-Density-Advantage-that-is-a-Full-Generation-Ahead This is the device that Xilinx wants the future generation of FPGA-based prototyping hardware to make use of. Rather than [...]

Tear down of the new HAPS-DX FPGA-based prototyping system

I’ve talked about streamlining IP to SoC prototyping and the use modes that prototypers use for IP validation. This week Synopsys announced the new HAPS Developer eXpress (HAPS-DX) prototyping system. This new HAPS-DX system is perfect for complex IP and subsystem prototyping and ties in nicely with the flow that I have been blogging about [...]

Enjoy!

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Posted in Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Technical, Tips and Traps | Comments Off

Tear down of the new HAPS-DX FPGA-based prototyping system

Posted by Michael Posner on December 20th, 2013

I’ve talked about streamlining IP to SoC prototyping and the use modes that prototypers use for IP validation. This week Synopsys announced the new HAPS Developer eXpress (HAPS-DX) prototyping system. This new HAPS-DX system is perfect for complex IP and subsystem prototyping and ties in nicely with the flow that I have been blogging about for streamlining IP to SoC. Similar to what I did last week with the Xilinx press release I thought I would do a tear down and cut to the chase and detail how HAPS-DX will benefit you.

Oh just so you know, this is a super long blog as I’m going to be on vacation over Christmas and New Year and won’t be blogging for a couple of weeks. With this blog being so long it will take you until 2014 to read. Please, please, please take the time to read it over hot coco and biscuits.

HAPS-DX is targeted at complex IP and subsystem prototyping and its 4 million ASIC gate capacity is perfect for this usage. I know this as Synopsys is the #1 Interface IP provider with DesignWare IP and all these IP’s will fit nicely inside of HAPS-DX. I expect we will see more use of HAPS-DX with DesignWare IP in the future… Using a smaller FPGA with a more basic board form factor means that the price point of HAPS-DX is in line with the expectations of the teams doing complex IP and subsystem prototyping. Complex IP and block design teams are usually more cost sensitive than the wealthy SoC team. Our customers love the HAPS prototyping capabilities but some others think the price of HAPS puts it out of their reach and they have to make do with inferior solutions. Enter HAPS-DX, yay, HAPS premium prototyping capabilities at a price point that satisfies everyone. Contact your local and friendly Synopsys sales person for specific pricing.

A platform like HAPS-DX is essential as more and more IP blocks will be making up the full SoC. To accelerate the time to market of the SoC you need to accelerate all parts of the design and validation tasks starting at the IP level. If you can accelerate the early tasks you can start other SoC activities earlier such as SoC integration and early software development.

Below are the highlights from the press release, which I’ll use these as the main tear down points from this point on.

Highlights:

  1. HAPS Developer eXpress (HAPS-DX) supports up to four million ASIC gates and easily integrates with HAPS-70 systems to enable seamless software development, hardware/software integration and system validation from IP to complete SoCs
  2. HAPS-DX includes optimized software for FPGA synthesis, debug and clock optimization supporting fast prototyping modes to accelerate time-to-first prototype
  3. Superior debug capabilities are built in with HAPS Deep Trace Debug, which can store seconds of signal trace data, and supports Synopsys Verdi, which delivers superior debug visualization
  4. Pre-validated DesignWare IP and access to a broad portfolio of HAPS daughter boards and FPGA Mezzanine Cards (FMCs) enable the quick assembly of prototypes
  5. Included Synopsys Universal Multi-Resource Bus (UMRBus) interface enables hybrid prototyping by providing a seamless connection between HAPS and Synopsys Virtualizer-based virtual prototypes for pre-RTL software development

I numbered the points so it’s easier to refer back to them in the blog. Starting where you would expect me to start, with #1,this point is all about enabling a seamless flow from IP to SoC prototyping. The HAPS-DX is targeted at complex IP and subsystem prototyping but that IP or subsystem usually ends up in an SoC and the last thing you want to do is to repeat the prototyping effort at the SoC level for those same blocks. HAPS-DX was developed with the streamlining of IP to SoC prototyping in mind. HAPS-DX provides reusable hardware and a software flow that is interoperable within a greater SoC project.

As pictured above the HAPS-DX was designed with reuse in mind. The HAPS-DX can be used directly as a daughter board connected to the larger HAPS-70 systems. This means that if IP prototyping is done right the same setup can be quickly incorporated into the SoC level prototype. This translates to reduced effort for the SoC team as the IP team did most of the work for them. The hardware needs to be able to support this usage and a methodology of planning for IP to SoC prototyping needs to be deployed. See here for my previous blog on IP to SoC prototyping. You can use the HAPS High-Speed Time-Domain Multiplexing between HAPS-DX and the HAPS-70 meaning that you are not limited to physical pin connectivity. HAPS HSTDM enables many signals to be packaged up and sent across the high performance link. Value summary: Start software development earlier from SoC prototype being operational earlier.

#2 is going to be a HUGE benefit to the complex IP/Subsystem prototyping teams as well as the SoC teams in the future. Along with HAPS-DX you get prototyping specific software customized for HAPS-DX at extra charge, which is an immediate cost benefit that I know everyone will like. More importantly this software specifically addresses the needs of the ASIC IP and subsystem prototypers, which are a little different than that of pure FPGA synthesis users. As talked about in this blog, the needs of prototypers are different than the needs of a designer targeting an FPGA as part of their final product. This new HAPS software is specifically architected to address the challenges of time to operational prototype, performance, debug and productivity. With this new software you should be able to get the HAPS system up and running faster meaning you get a gain of time to market and as mentioned earlier you can start the SoC integration tasks earlier.

This new HAPS software incorporates the core unique Synopsys technologies along with a new set of capabilities specifically addressing prototyping challenges. At the start of the prototyping project the prototyping engineer is not so worried about squeezing the optimum performance out of the FPGA. They really want to get to a functional prototype as quickly as possible so they have something to hand off to keep the software developers or validation team happy. Once they have handed off that image they can work on optimizing the prototype. The HAPS-DX software delivers on both with capabilities customized for time to first operational prototype and a path to high performance.

What’s not mentioned here directly is that the new software is very ASIC flow like rather than FPGA like. We see a trend that companies no longer have specific “FPGA experts” for prototyping; they use the same validation engineers that are used to working with Design Compiler synthesis scripts and VCS simulators. The HAPS-DX software provides a more ASIC like design flow with bottom up design flow, TCL scripting and multi-processing for improved productivity. FPGA-based prototyping software tools have grown up. Value summary: Start IP validation and software development earlier from earlier prototype availability

#3 is all about debug and the bottom line is that with HAPS-DX you are going to get greater debug visibility, which means you should be able to track down the source of the bug faster and productivity should go up. Debug is a hot topic with respect to FPGA-based prototyping and while there have been point tool solutions trying to solve the problem in the past, the HAPS-DX was designed with the need of debug built right in.

When debugging you want greater visibility and the capability to store more trace data. In a simulator you have almost infinite trace data storage, but in hardware you are limited to the physical storage medium. HAPS-DX delivers software that automates the insertion of debug instrumentation providing a simulator like experience in addition to integrated HAPS Deep Trace Debug built right onto the hardware. This is not a new concept for HAPS, I’ve blogged about these capabilities before, here and here. What is new is that HAPS-DX has it all built-in to both the physical hardware and the included software flow. Now you can quickly add debug capabilities into your prototype right from the get go of the project rather than adding it later when someone is beating on your door for more visibility to find the root cause of a bug.

Here you can see the DDR3 memory directly built into (and supplied with) HAPS-DX. I spoke to the engineer who spearheaded the HAPS Deep Trace Debug capabilities and asked him for an example of the benefit to users. He’s an engineer and answered me in engineering terms. His answer was “Think 128 signals captured at 100 MHz, you have the capability to store 5 seconds of trace data on the 8GB DDR3”. 5 seconds of trace data !!!!! That’s huge in the world of at speed debug. Add to that the fact you can write out FSDB which is the native waveform database for the Verdi debug tool. Verdi is used extensively in the ASIC debug space and now you can use the same capabilities with your HAPS-DX prototype. If you have access to Siloti you can also use the visibility expansion capabilities and get close to 100% visibility of select modules. Value summary: Higher productivity from ability to find and fix bugs faster

#4 is all about easing prototype assembly which I blogged about recently as well (you would almost think I planned all these blogs). I’m won’t comment on the DesignWare IP support, as mentioned above I’ll save that for a future blog. What is important to you is that HAPS-DX supports both the validation modes that you use and enables a huge range of hardware daughter boards so you can tailor the system to your specific project needs. HAPS-DX supports the traditional standalone mode, PCIe connected and the emerging hybrid prototyping use modes. I expect that hybrid is going to be a popular use mode for HAPS-DX as you can immerse the IP in a virtual representation of the SoC without having the actual RTL.

The alternative to buying HAPS-DX would be building a specific FPGA board that meets your project’s needs; it’s the age old make vs. buy. Most engineers think that designing a single FPGA platform is easy, and for an experienced designer it might be. The board can be designed with the needed interfaces built right onto it keeping it cheap to deploy. However, I know many teams that have designed great FPGA boards but still got burnt during the active project. The issue is marketing. Yep, the marketing team comes in with a late change request, the latest example I heard was a shift from USB 2.0 to USB 3.0, and unfortunately the hardware didn’t support the new requirement. The team had to scramble, redesign the boards and the project slipped 3-6 months. Yuck. HAPS-DX’s advantage is that it supports both HapsTrak 3, the same connector standard used with HAPS-70, as well as providing an FMC interface module.

With HT3 you get to pull from the large portfolio of available Synopsys daughter boards and others from 3rd party vendors that provide specialized daughter boards for HAPS systems such as Gigafirm, who I visited while I was in Japan and highlighted in this blog. In addition, the FMC interface module enables you to utilize the HUGE range of FMC style daughter boards available. There are literally 100’s (no joke I counted) of available FMC daughter boards available enabling AD/DA, serial connectivity, imaging processing and many, many more. Basically you get to tailor HAPS-DX the way you like it. It doesn’t get easier than that and even that pesky marketing team can come in and change the requirements on you at the last minute or worse mid project and all it not lost. Simply reconfigure HAPS-DX with a new daughter board expanding its usage to the new requirement. And if that was not enough, when the next project comes along you can reuse HAPS-DX assembled with a new set of daughter boards meeting the requirements of the new project. Value summary: Easy prototype assembly reduces effort and greater reuse increases return on investment

Finally, #5 is all about the more advanced use modes. The HAPS Universal Multi-Resource Bus, UMRBus, is the gateway to connecting the HAPS prototype to host machines. The UMRBus capability is built directly into the HAPS-DX meaning no add-on cost and comes with a set of example designs easing the setup of the prototype. As mentioned above, the hybrid use mode is getting more and more popular especially for IP validation. While it was once fine to validate a block outside of the context of an SoC, the CPU and software have become essential as part of the validation of the IP or subsystem. You actually need to validate the real software against the IP to know that it operates correctly. Enter the PCIe connected modes and hybrid prototyping. These operation modes enable software to be run on a host and executed on the real hardware representation of HAPS-DX. In the hybrid mode you model the system in a virtual prototype such as Virtualizer and then communicate to the HAPS-DX via the UMRBus. Synopsys already provides a library of transactors which act as the translation between the SystemC environment and the signal and pin toggling needed in real hardware. You immerse the IP in a realistic representation of the real SoC ensuring that when the IP is integrated into the larger SoC you already have high confidence that it’s fully operational. Value summary: Greater productivity from rapid deployment of advanced use modes

Oh boy, this blog is huge……. please, please, please take the time to read it. Of course if you are reading this then you have made it to the bottom, congratulations.

So summing up, with HAPS-DX you get a flow from IP to SoC, prototyping software that accelerates the time to first operational prototype, built in debug for greater debug visibility, fast prototyping assembly with HT3 and FMC daughter boards and the support for all expected prototype use modes. Actually the press release bullets nailed the benefits. I still think my tear down of the points will help explain better how each of these benefits affects you more directly.

  • HAPS-DX increases your productivity, making your manager happy
  • HAPS-DX reduces your effort, making you happy
  • HAPS-DX reduces your risk, making everyone happy

Happy Holidays

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Posted in ASIC Verification, Debug, FPGA-Based Prototyping, Getting Started, Technical | Comments Off

Xilinx FPGA’s for FPGA-Based Prototyping

Posted by Michael Posner on December 14th, 2013

If we look at the FPMM survey respondent data it’s clear to see that the favored FPGA device for FPGA-based prototyping is Xilinx devices

This week Xilinx announced the Virtex® UltraScale™ VU440 3D IC.

http://press.xilinx.com/2013-12-10-Xilinx-Doubles-Industrys-Highest-Capacity-Device-to-4-4M-Logic-Cells-Delivering-Density-Advantage-that-is-a-Full-Generation-Ahead

This is the device that Xilinx wants the future generation of FPGA-based prototyping hardware to make use of. Rather than spending too much time picking apart the announcement I’m going to try and summarize it in my own words. Then I’m going to share my blog with friends over at Xilinx and request that they expand on my points and add anything that I missed in a guest blog.

In my humble opinion the key capabilities specific to FPAG-based prototypers are:-

  • Capacity
  • Routing resources
  • Clocking structure

 So starting with capacity, the VU440 is a whopper of a large FPGA, Xilinx claims 50 Million equivalent ASIC gates. I think this claim is a bit of a whopper, as in I personally do not think that you could map a 50 Million ASIC gate design into this device. Each FPGA vendor counts ASIC gate equivalent slightly differently so it’s very hard to compare ASIC technology gates to FPGA equivalent ASIC gates. For example Synopsys uses the Xilinx Virtex-7 2000T in its HAPS-70 series and we publicize 12 Million ASIC gate capacity per FPGA. This calculation of ASIC gates has come from the 10+ years of experience in FPGA-based prototyping. We claimed 2 million ASIC gate capacity of the Virtex-5 330, 4.5 million ASIC gates for the Virtex-6 760 and as stated above, 12 million ASIC gates for the Virtex-7 2000T. Our customers don’t complain that their ASIC RTL does not fit into our systems so we feel confident that our calculation of ASIC gate equivalent is pretty spot on.

Regardless of the ASIC gate counting differences the VU440 is over double the size of the 2000T meaning that we expect it to provide over 25 Million ASIC gate capacity per FPGA. This is great for FPGA-based prototypers as by the time this device is available the designs being prototyped will need this capacity increase. During the transition from V5 to V6 and V6 to V7 we saw no consolidation of systems, as in for example a customer using a dual FPGA system did not move to a single FPGA system with the new FPGA which had double the capacity, they moved to the dual FPGA system with the new FPGA. Some customers even moved to larger systems such as from the 4 to the 8 FPGA system. This tells me that the size of the designs was scaling at a faster rate than the FPGA technology. I expect this to be true in the future to.

Routing resources is very important to FPGA-based prototyping as the code that is being thrown at these devices is ASIC RTL and not specifically “tuned” for FPGA. The requirement of translating ASIC RTL to FPGA is driving the need for prototyping specific software tools that are geared towards solving this ASIC to FPGA translation with reduced turn-around. While FPGA implementers who’s final product utilizes the FPGA device prototypers mostly don’t care what the device is they want to get a model up and running fast so they can quickly enable their software developers. Look at the FPMM survey responses below, mapping ASIC RTL to FPGA is still the #1 challenge by a long way. I’m going to blog about this need more in the future.

Staying on track with routing Xilinx states that the new VU440 has a greater number of passive interposer interconnect (features 5x more inter-die bandwidth). This is a 3D device so it has multiple Super Logic Regions (SLR’s) which connect to each other via this passive interconnect. With more interconnect the users should see faster fitting times, (FPGA Place & Route) from the higher number of possible solutions available. This increased interconnect should also result in greater utilization (Xilinx claiming up to 90%) which means you can stuff more into the device.

Finally clocking, Xilinx is claiming “ASIC like” new clocking structures and clock routes that span SLR boundaries. This is really important to FPGA-based prototypers as the code that is being targeted to these devices is ASIC RTL so by nature is designed with ASIC style clock trees. With the new Xilinx architecture being closer to ASIC clocking the designs *should* translate better into the FPGA device. Don’t take my word for it, look at the FPMM survey responses below, translating ASIC clocks to FPGA is the #2 challenge identified. Xilinx’s ASIC like clocking will potentially ease the support for ASIC clocking structures and with the new higher number of available clocks even ASIC’s with thousands of clocks should be easier to target to this new FPGA.

This combined with the clocks that now span SLR boundaries means that higher performance should be achievable. Of course don’t forget that the overall system performance of an FPGA-based prototype is usually not dictated by the single FPGA performance but by the interconnect between the FPGA’s and the pin multiplexing (when you have more signals between FPGA’s than pins). This is why Synopsys offers HAPS High Speed Time-Domain Multiplexing, HAPS HSTDM, which packages up signals and transfers them between FPGA’s are Gigabit speeds. The use of HAPS HSTDM is almost transparent to the users when they use the Synopsys tools which automate the insertion of the HAPS HSTDM IP.

WOW, this blog got long…….

So to summarize the new Xilinx UltraScale VU440 FPGA looks like it will be very exciting for FPGA-Based Prototypers. I am also looking forward to seeing how Altera responds to this <insert evil grin here>.

What is your opinion of the new Xilinx device? Post a comment and let me know.

Now off topic, I finished the toy I have been making for my son, the Command Module. I think it turned out very well. It has plenty of switches, dials and interactive buttons to ensure that when mixed with a little imagination it can be turned into anything my son can think of. Here is a video of it in action: https://www.youtube.com/watch?v=SxyXtHnBkMQ 

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Command and Control

Posted by Michael Posner on December 7th, 2013

It’s been a quiet week for me and prototyping but I did talk to an engineer about command and control of an FPGA-based prototype which I thought was quite interesting I will share the story.

The engineer was designing a subsystem and within the FPGA-based prototype wanted the capability to pre-load the DDR memory with contents as well as to dynamically control the register configuration. Initially the engineer was thinking about building custom hardware and software capabilities to achieve this which was a long and risky approach. I was able to make the engineer very happy by providing them an overview of the available Universal Multi-Resource Bus (UMRBus) capabilities the HAPS systems have.

To solve the pre-load problem the engineer had the UMRBus can be combined with a transactor which enables data to be easily written across from the host directly into the DDR memory. The UMRBus interfaces with a standard transactor like one for AMBA AXI. The data is written from the host and the transactor passes the data to the on chip bus interconnect which enables the data to be written to memory. The engineer can use the simple TCL based UMRBus interface from the host to facilitate this data write or could also make use of the generic C++ API and create a more comprehensive setup. It should be noted that in addition to pre-loading the memory like this the memory can also be read back for post process data analysis.

To solve the problem of dynamically controlling the DUT within the prototype the UMRBus can be deployed again. This time rather than using a full transactor the engineer would make use of the Client Application Interface Modules, CAPIM, which is a simple write/read interface which can be customized to meet the design interfaces needs. This was perfect for this use case as the DUT had a simple registered interface meaning the CAPIM could quickly be wired up to it. Again the CAPIM can be accessed via the simple TCL interface or from the C++ API.

Problem solved, happy engineer.

Talking of command and control I’m currently building a toy for Christmas which is designed to be like a command and control module.

This is just a picture of a little bit of the project. The front panel will have switches, buttons, dials and LED’s which my son will be able to play with. It doesn’t really do anything specific other than light up LED’s but when you add a child’s imagination to this it will turn into amazing things. The command module of a boat, car, space ship, submarine and everything else that they can imagine. I’ve been working on it for a couple of weeks now and I’ll post pictures of the final product closer to Christmas.

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System Validation and Compliance Testing of PCIe Gen3

Posted by Michael Posner on November 29th, 2013

While wandering though the DesignWare IP testing lab in our office I found this:-

It’s sort of hard to see but this is a HAPS-70 S12 platform connected to a LeCroy PCIe protocol and electrical compliance tester. The DesignWare PCIe controller core has been implemented in the FPGA and in this setup is using the FPGA devices transceivers for the electrical interface. The split between the DesignWare controller and the Xilinx transceivers is at the PIPE interface.

The pod sitting on top of the HAPS-70 is the Universal Multi-Resource Bus pod, which enables remote access, high speed configuration and dynamic debug capabilities.

I’m pretty sure the setup was being used for PCIe Gen 3 compliance testing in preparation for an upcoming PCIe SIG meeting.

The DesignWare PCIe core is designed for SoC usage and the testing on the HAPS platform provides a reference that the core has been hardware validated and compliance tested. This is of course without having to harden it in silicon so the HAPS setup is a far more flexible solution for the digital controllers. It was great to see the HAPS technology being used to benefit our own teams at Synopsys.

Short blog this week as I am currently digesting turkey from the USA thanksgiving and need to take a little nap.

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Accelerating Prototyping Hardware Assembly

Posted by Michael Posner on November 23rd, 2013

This week I wanted to focus on a discussion around prototyping hardware assembly.

Prototype hardware assembly is the process to tailor FPGA-prototyping hardware to meet the needs of the project. The first type of prototype assembly would be to build a custom platform directly matching the projects requirements. The building of prototyping hardware is the alternative to buying an off-the-shelf solution. The advantage of building the hardware is that you can tailor it to exactly meet the projects requirements. The disadvantage is this process is time consuming due to the long development timeline and bring-up debug process. I’ve also run into many customers who got burnt at the last minute when marketing made a last minute spec change which the custom platform does not support. Whoops, back to square one to do a frantic redesign which typically results in project delays

This is why off-the-shelf prototyping hardware is so popular. Off-the-shelf prototyping hardware, like HAPS, offers the stability of a pre-designed and validated platform but has the disadvantage of requiring the user to tailor the platform to meet the project’s needs. Some hardware vendors offers interfaces such as Ethernet directly on the prototyping board. The problem with fixed interfaces is that if the project needs them great, if the project does not then the hardware is just wasting IO resources which could be used for other purposes. HAPS is a generic reusable platform which you tailor to meet the needs of the project. There are lots of off-the-shelf daughter boards for this purpose such as DDR3, SRAM, PCIe, Ethernet, SATA, Flash, Lab. However it’s impossible for Synopsys to design and build all types of daughter boards to meet every projects need (but we try hard to). While in Japan last week I visited the Embedded Technology (ET) show in Yokahama and met with a company called Gigafirm. Gigafirm (http://www.gigafirm.com/)  has designed a set of HAPS daughter boards supporting the HAPS-70 series of products delivering daughter board support for V-by-One and embedded DisplayPort (eDP)

Above you can see Gigafirms daughter boards installed on a HAPS-70 S24 platform, the HAPS system with two Virtex-7 2000T devices. V-by-One and eDP are used for image and video designs of which there are many design starts at Japanese based customers.The V-By-One Hapstrak 3 (HT3) daughter board enables the THine (http://www3.thine.co.jp)

V-By-One evaluation boards to be connected directly the HAPS platform and supports both RX and TX capabilities.

The eDP daughter boards are designed for the HAPS Multi-Gigabit (MGB) connector interface. These high speed daughter boards enable both RX and TX eDP capabilities on the HAPS-70 systems.

I was very impressed with the quality of the Gigafirm deliverables. Gigafrm is helping customers accelerate prototype assembly by providing off-the-shelf high quality daughter boards enabling the HAPS systems to be tailored to meet the designs validation needs.

While at ET in Japan I also say the Fujitsu evaluation and development platform showcase connection to the HAPS-70

The Fujitsu development platform enables customers to evaluate the Fujitsu products and jump starts their software development tasks. The Fujitsu platform interfaces to the HAPS system via a transparent PCIe interface. The connection to HAPS enables customers to extend the platform with the capacity to model their own design blocks and validate them operating against the Fujitsu subsystem.

The Fujitsu evaluation platform is called the Phoenix. What a great name IMO.

It’s great to see the eco-system that has built up around the HAPS FPGA-based prototyping solution.

Finally, thanks to everyone who sent me a note about my allergic reaction that I suffered last week. The good news is that since that time I have only suffered a single smaller reaction which resulted in a fat lip and swollen cheek. I have not pin-pointed what is triggering the reaction but by the process of elimination I am narrowing down the suspect foods.

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Learning A New Thing Every Week

Posted by Michael Posner on November 16th, 2013

I don’t know about you but this has been a whirlwind week for me. I was at the corporate Synopsys offices in Mountain View CA working with the HAPS hardware and software development teams. I also video interviewed Eric “Hollywood” Huang on the DesignWare 10G USB 3.1 teams use of the HAPS-70 systems. We will edit and post that video in a couple of weeks. I was making fun of Eric because he is always doing videos and it looks so easy. I have to say doing videos is not easy as Eric makes out. Kudos to him.

I received a copy of the DSP-FPGA 2013-2014 resource guide this week and I was pleased to see the HAPS-70 highlighted on the cover.

That was the highlight of the week for me. The lowlight was that I found out the hard way that I have a severe allergic reaction to something. On Thursday afternoon after a sushi lunch and then a snack of pretty much every type of candy made available to employees at our office my lower lip started to swell up. I knew I was having an allergic reaction to something but it was just my lip so I was not that worried by it and set off to the airport via returning my rental car. I did stop off and pick up and take two antihistamine tablets just in case. Unfortunately within the 20 minutes it took to get to the Avis rental car return center my lower lip has continued to swell and both my upper lip and right side of my face were swelling up. Not good.

A nice lady called Carrie greeted me as I got out of the rental car and she asks me the standard “How are you today sir?” I usually reply “I’m fine” but of course today I didn’t. I calmly said to her “Usually I would say I’m ok but today I seem to be having an allergic reaction and to be honest I’m going to go downstairs and find myself a paramedic!”. Carrie was great, rather than just continuing with her job she grabbed my bags and escorted me to the lower floor and got the paramedics on the phone. Based on the fact that my face had swollen up in less than 30 minutes the paramedic dispatcher confirmed what I already knew, allergic reaction. Thanks Carrie for taking good care of me.

Within 3 minutes the fire department had arrived (standard protocol) and 5 of the nicest and beefiest firemen came to talk to me. Then the paramedics came and took me to the hospital. The paramedics confirmed that taking the antihistamine was the right thing to do. Anyway to put a long story short at 4pm I was in hospital and by 7pm I was discharged. The face swelling went down as fast as it came up.

Here I am 5 minutes before discharge. I’m rather sad looking but at least most of the swelling had subsided and I was going to live to blog another day.

Unfortunately as I ate a whole load of different things I have no idea what triggered the reaction. The result of this means I now have a new tool as part of my standard travel stuff, an Epipen…

Joy…… Like the title states, learning a new thing every week… I didn’t say learning a good thing every week….

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