BLOGS & FORUMS
Breaking The Three Laws
|Breaking The Three Laws|
Posted by Michael Posner on November 7th, 2014
Dear Dr. Lauro Rizzatti,
I enjoyed reading one of your recent articles http://electronicdesign.com/eda/hardware-emulation-weapon-mass-verification but was dismayed that you were still quoting limitations from the early years of FPGA-based prototyping. I recommend you refresh your knowledge and read my recent blog on the top myths of FPGA-based prototyping busted. http://blogs.synopsys.com/breakingthethreelaws/2014/09/top-3-myths-of-fpga-based-prototyping-busted/
I’m looking forward to future articles integrating the latest information.
Just in case you don’t take the time to read Dr. Lauro’s article the three points of out of date information were on capacity supported, time to first prototype operation and debug.
Quote “Even in the largest configurations, they address designs with about 100 million gates.”
– New Data Point, Synopsys HAPS supports 288 Million ASIC gates
Quote “ Conversely, very long setup time to map a design into a proto board and rather limited design visibility are its two main drawbacks.”
– New Data Point, Synopsys HAPS and ProtoCompiler software accelerated time to first prototype and delivers high visibility debug.
When you correct these mistakes the radar graph in the article changes quite a lot.
Just in case you missed my blog on the top myths here is a direct link to it again: http://blogs.synopsys.com/breakingthethreelaws/2014/09/top-3-myths-of-fpga-based-prototyping-busted/
Posted in ASIC Verification, Debug, Man Hours Savings | Comments Off
Posted by Michael Posner on October 30th, 2014
In previous blogs I have spoken a lot about automation, features and capabilities which accelerate time to operational prototype and deliver higher performance enabling you to run more software against your design representation. These capabilities are designed to reduce the need for prototyping expertise and effort…….. but not to zero. Anyone who tells you that no expertise or effort is needed is not telling you the whole truth. This was the basis of this blog, “Breaking the three laws” of which the first law is ASIC are FPGA Hostile! Who can tell me what the other two laws are? I know but this is like a quiz for my readers.
Pictures in the blog are posted large so they are easier to read, click on the picture to see the full view version.
Synopsys has created a simple three phase definition for FPGA-based prototyping, including methodology guidelines and I am happy to share them with you. The three phases split into 1. Make Design FPGA Ready. 2. Bring Up Functional Prototype. 3. Optimize Prototype Performance. Follow these three phases and you will be on a path for FPGA-based prototyping success.
Make Design FPGA Ready
This is probably the most important step as the rule of thumb is garbage in, garbage out. There is only so much automation a tool can deliver so understanding the basic needs and best practices for FPGA-based prototyping is essential. Synopsys ProtoCompiler can help here with automated ASIC to FPGA translation, clock conversion and replication as needed. However you should always follow the best practices defined here to yield better results in the final implementation. Don’t forget, full best practices can be found in the FPMM, FPGA-based Prototyping Methodology Manual.
Bring Up Functional Prototype
Once code is prepared the bring up functional prototype phase is entered. This is the phase with the goal of getting the prototype up and running as quickly as possible, TTFP, enabling the team to hand off a platform to the software developers. The faster they get a platform the most productive they can be. Even if you have traded off a little performance to get the fastest time to prototype your software team will thank you for the fast enablement. ProtoCompiler and HAPS helps here, especially in the partition phase, I recently blogged about this: Abstract Partition Flow Advantage. Another important best practice is to plan your debug needs upfront in this phase, don’t treat it as an afterthought. This is exactly why in the ProtoCompiler flow debug is highlighted ensuring you at least give it some thought.
Optimize Prototype Performance
As you have already delivered an operational prototype to your software team you have a little breathing space now to focus on performance optimizations. In the fast turn-around abstract partition flow ProtoCompiler might have identified some bottlenecks that you skipped past in order to achieve fastest time to prototype. Now you have time to focus on these and other areas of the FPGA-based prototype to squeeze the most out of the solution. An example of this was shared with me recently where the prototype was fully operational at 9 MHz but with a little more effort, new partition and careful analysis of critical paths, the prototype performance was increased to 13 MHz. What a great improvement.
So there it is, three simple phased approach ensuring successful prototyping, enjoy!
Happy Halloween, here is the costume that I built, I call it Atomic Dinosaur. I am a construction spray foam master and it has LED lights down it’s back too!
That’s some crazy eyes I’ve got going on…………….
Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps | Comments Off
Posted by Michael Posner on October 24th, 2014
This week’s blog is a bit of a mashup (Yes that is a real word, a mashup, in development, is something that uses content from more than one source to create a single new offering) as I am pulling together two topics to create one. The #1 usage case of prototyping is for early software development. You can do this very early, pre-RTL using Virtual Prototypes, later in the design cycle with FPGA-based Prototypes but it’s the bit in the middle that this week’s blog examines.
The bit in the middle is typically unit level or IP validation with the goal of early software development before the rest of the subsystem is available. The DesignWare IP Prototyping Kits : http://www.synopsys.com/IP/ip-accelerated/Pages/ip-prototyping-kits.aspx were designed to address the need for immediate productivity and early software development for DesignWare IP’s. The kit includes the actual DesignWare IP modeled on HAPS-DX and an ARC based Software Development Platform
The question which has been raised a couple of times is what if you are not using an ARC processor in your end SoC? At this point I usually start probing a little more as to what type of software is being developed, if its physical layer and processor specific then yes the ARC software development platform is not going to work for you. If it’s higher layer software then typically the software engineer does not care as it’s layers above and abstracted from the physical execution machine. But what do you do in the case where you need physical layer and processor specific software development?
Lets use the example that you want to enable early software development on an ARM-based system representation and you still want to validate your design under test modeled on a FPGA-based prototype. The problem is that your SoC engineers have not complete the subsystem design and/or you don’t have access to the RTL to put the processor subsystem on the FPGA-based prototype along with your DUT.
One solution would be to do similar to what Synopsys did with the DesignWare IP Kits and that is connect the FPGA-based prototyping platform to a physical daughter board containing an ARM-based subsystem. One of the possible ways to do this is to use an off-the-shelf Xilinx Zynq based daughter board. The Zynq device includes a Dual Cortex-A9 MPCore processor subsystem and provides the ability to connect this to the FPGA-based prototyping platform via an AXI tunnel across typically FMC connectors. This is true for the HAPS series where you have the ability to connect the Zynq based board to HAPS via FMC cables.
Great right? Hummm…. Seems too good to be true…… Yes, you are right, this use mode is a trade-off. While you can execute ARM-based code against your prototype you are not running the software against YOUR ARM-based subsystem. You are stuck with the processor configuration hard-coded into the Zynq device which you know will never match your SoC subsystem. Also, in the case of the Zynq it’s the 32bit processors not the 64bit versions. There is a better way to enable early software development using a processor subsystem which is a better match to your SoC’s subsystem, it’s the Hybrid Prototyping approach.
I’ve blogged about this before, one such case was Zoro’s use of Hybrid Prototype for early software development for USB 3.0 : http://blogs.synopsys.com/breakingthethreelaws/2014/06/zoro-delivers-hybrid-prototype-for-early-software-development/
The advantage of using a Hybrid Prototype rather than a fixed hardware daughter board is that the virtual processor based subsystem can be tailored to more specifically match the SoC subsystem design. New to virtual prototyping? Don’t worry, Synopsys provides ARM Virtual Development Kits (VDK’s) : http://www.synopsys.com/Systems/VirtualPrototyping/Virtualizer-Development/Pages/vdk-family-arm.aspx to jump start your development. These VDK’s can be used at the starting point for your customization to match your SoC’s need. This full virtual environment is expanded to a Hybrid Prototype with the use of the off-the-shelf transactors which are a bridge between the TLM virtual and the RTL hardware systems. You are not sacrificing performance either as the Synopsys Hybrid Prototyping solution enables asynchronous operation between the Virtualizer and HAPS ensuring that the software env executes at speed as well as the hardware env which is typically required to keep real world interfaces alive.
What a mashup !!! It’s clear to me that Hybrid Prototyping is a far better solution to enable early software development as you can customize the processor subsystem to more precisely match the SoC. This way the software code created and executed on the prototype is a closer or direct match to the software which will run on the SoC.
Posted in ASIC Verification, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, IP Validation | 1 Comment »
Posted by Michael Posner on October 20th, 2014
It’s the age old question, what came first, the chicken or the egg?
When we ask this question about FPGA-based prototyping then the answer uncovers some interesting facts about the evolution of this technology. When first utilized most customers would build their own boards and tailored them to the exact SoC project’s needs. The advantage of this is that the board is specifically designed for the SoC, meaning it included the exact real world interfaces needed and an interconnect architecture specifically matching the SoC architecture. The result of this customization was the best FPGA-based prototyping hardware for the SoC project. Of course because the hardware was customized for the exact project needs the hardware was typically not reusable in the next projects.
To address the need of reusability along came 3rd party commercial FPGA-based prototyping boards. They offered a generic FPGA-based prototyping hardware solution that enabled reuse across projects. But at what technical cost we ask ourselves? The boards offered many real world interfaces but the interconnect (PCB traces) were not customized to the needs of the SoC being modeled. The result sometimes was that the highest performance could not be reached as you had to force fit the SoC prototype implementation to the fixed interconnect topology. This force fitting means that high signal multiplexing ratios were needed reducing the system performance. I blogged (How IO Interconnect Flexibility and Signal Mux Ratios Affect System Performance) about the relationship between these before. The HAPS-50 and HAPS-60 systems provided both PCB traces and flexible connector options which started to address the need for commercial hardware that could be customized directly to the needs of the SoC. The HAPS-70 systems revolutionized this approach by providing the ability to tailor the system to the exact requirements of the SoC using intelligent high performance links. I have previously blogged (UFC: Cables Vs. PCB Traces) about the fact that the performance of these flexible links is as good as pure PCB traces. I’ve also blogged (The Secret Ninja-Fu for Higher Performance Prototype Operation) about how this flexibility enables higher performance prototypes.
But the problem is not that simple to solve. SoC prototypes are multi-FPGA so sometimes large blocks could be split up across multiple FPGA’s which add new interconnect requirements. So how are these handled as you don’t know about them until you come to partition the SoC? The answer is that you need an integrated solution which can quickly generate a partition from an associated interconnect architecture but also provide the flexibility to adapt it. This is what Synopsys calls the abstract partition flow with ProtoCompiler and HAPS-70. In summary, the combination of ProtoCompiler and HAPS-70 enables you to quickly create an abstracted interconnect architecture representation, generate a partition solution for it, then incrementally customize it based on the needs of the SoC. Let me share an example which was from the Imagination PowerVR 6XT on HAPS collaboration case study presented at recent SNUG events.
In the ProtoCompiler flow for HAPS-70 you first create an abstract representation of the interconnect between FPGA’s. This is very quick to create as it’s a simple text file with TCL commands defining the connections. The picture below is an example of such an abstract system interconnect. Remember that there are no fixed traces between FPGA’s but this abstract is not exact connections, just a representation of possible IO interconnections. Then run ProtoCompiler
ProtoCompiler in this case study took less than 1 minute to come to a five Xilinx Virtex-7 FPGA partition. Remember that ProtoCompiler is HAPS-Aware so it incorporates the hardware capabilities in automatically. The picture below shows some of the reports from ProtoCompiler at this point. Firstly the expected FPGA utilization and secondly, the most important, signal to multiplexing ratio report.
The mux ratio report has highlighted the worst case mux-ratio, 16, on a path from FPGA A to FPGA D. Remember that the higher the mux ratio the lower the system performance. Within 1 minute ProtoCompiler not only partitioned the design but it also identified the main bottleneck based on the abstracted interconnect architecture. The flow is incremental so at this point you go back to the abstract file.
We know the HAPS-70 interconnect is flexible so in the abstract flow we theorize that we need more physical IO between FPGA A and FPGA D. In our case we are going to raise the IO count from 200 to 300. This is a one line change in the abstract file as seen in the below picture.
ProtoCompiler is re-run and again generated a new partition result in a matter of minutes. Looking at the mux report now you can see that the more dense IO between FPGA A and FPGA D has relived the multiplexing ratio. The new ratio is 12 which means our prototype will run at higher performance. This is the solution to the chicken and egg question, you don’t want to fix your hardware interconnect architecture until you have a partition solution. Then based on the partition solution you want to fine tune the hardware to best match the partitioned SoC requirements. The Synopsys solution of ProtoCompiler and HAPS-70 is the only integrated solution that provides this capability. This rapid and incremental flow results in hardware that is tailored to the exact SoC prototyping requirements and of course you maintain the reuse aspect as the hardware can be reconfigured to your next SoC project’s needs.
Finally….. I have been build a new toy, this is a conveyor belt toy with working conveyor belt, articulation and many lights.
You can see the toy in action here: https://www.youtube.com/watch?v=2aVdOXWo-2Q
Posted in Man Hours Savings, Mick's Projects, System Validation, Use Modes | Comments Off
Posted by Michael Posner on October 10th, 2014
Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09, starting in reverse order this week.
Certify 2014.09 is now available and we’ve packed it with new capabilities. Below is just a snippet of the new additions.
- Advanced synthesis options deliver improved timing QoR, correlation and rapid timing closure. On average 5-6% timing QoR improvement. Just flip a switch, non-disruptive use mode.
- Exploratory P&R, Improved Timing QoR, better routability and runtime by optimizing P&R setting based on the design. Determines different P&R settings based on the design. Runs multiple parallel P&R jobs and gets the best results. Compare QoR Results and Save Best P&R Settings. Up to 8% improvement in post P&R results
- Distributed Processing, Allows running different jobs on network machines. Improved Runtime and delivers quicker turnaround.
Onto Rabbets, who here knows what a Rabbet is? No, that’s not a typo, Rabbet……. Anyone, Bueller…. Bueller…. Bueller….. ok, no one, good, as until recently I didn’t know what it was either. Simply put it’s a groove cut into the edge of something: http://en.wikipedia.org/wiki/Rabbet
Why am I talking about Rabbet edges you ask? Well we have just released a new daughter board for HAPS which is designed to connect the center rows of Hapstrak 3 connectors to it’s adjacent FPGA partner East/West
It’s a small board with very high signal integrity but we found that it was pretty tough to remove, enter the rabbet. A small groove cut in the edge of the board ensures that the included little plastic pry bar can be used to safely remove the board. (Remember that ESD precautions should always be observed).
On the HAPS systems the Hapstrak 3 (HT3) connectors are bank and SLR mapped 1:1 with the Xilinx Virtex-7 2000T FPGA pins. No HT3 connector IO crosses Xilinx’ SuperLogic Region, SLR, boundaries. This is hugely important as ensures that additional SLR crossings are reduced as the Xilinx P&R tool naturally can route directly to pins of a connector within the associated HT3 connector.
See the two examples below from a real multi-FPGA SoC design which was targeted at both a board with connectors that are not bank and SLR matched and the HAPS-70 systems with 1-1 bank and SLR mapping.
Wow, the SLR crossing adds a 2x delay on the critical performance path, this tanks system performance
No additional forced SLR crossing with HAPS. This is a pure hardware capability, no amount of synthesis and P&R software can work around this.
Posted in Daughter Boards, Man Hours Savings, Use Modes | Comments Off
Posted by Michael Posner on October 3rd, 2014
We have just uploaded a stack of product videos. Below is a list of the latest three. (I think they are sexy!!)
• Prototyping Imagination’s PowerVR Series 6XT dual-cluster 64-core GPU with Synopsys HAPS and ProtoCompiler
A video showing the multi-FPGA system used to model IMG’s GPU. The system has real-time video out for visual inspection of the images
• Speed IP/RTL Block Bring-up and SoC Validation with HAPS-DX
A video explaining the methodology, flow and capabilities which enable a block to be prototyped and debugged on HAPS-DX and seamlessly integrated into an SoC prototype on HAPS-70
• Synopsys ProtoCompiler for RTL Debug with HAPS Systems
A video showing the new ProtoCompiler debug capabilities including multi-FPGA with deep trace
They can all be found (plus more) here: http://www.synopsys.com/Systems/FPGABasedPrototyping/Pages/Videos.aspx (Sexy right?)
A couple of weeks ago I blogged about my 20 years at Synopsys. Well this week one of the Synopsys sales people was nice enough in their own time to create a depiction of what I look like now vs. 20 years ago. Below you can see the then and now depiction.
THANKS, Mr. Synopsys sales person…. You know who you are…. I know where you sit
To set the record straight below is a picture I snapped off this week after a haircut.
No supermodel for sure but I still got my hair…
Posted in ASIC Verification, Bug Hunting, Debug, DWC IP Prototyping Kits, Early Software Development, Humor, IP Validation, Man Hours Savings | 1 Comment »
Posted by Michael Posner on September 27th, 2014
While visiting a customer this week in the UK I asked the following question:-
Mick: How many people work here?
Response: oh, about 1/2 of them……………………….
Now at first I assumed they meant that half the people work at this site and half at their other site…. In reality my jetlag was blinding me to the fact that this was actually a joke. Funny, I thought I would share. The brits, they are very funny.
Welcome Zebax & EDADoc new HAPS Connect Members
Zebax Technologies offers test modules (breakout adapters) enabling debug and test of design solutions using high-speed b2b connectors covering multiple single/differential ended signaling standards for test equipment, FPGA Mezzanine Card, FMC, standards, including HSMC, VITA 57.1, and HAPS. Additionally Zebax offers test modules catering to ASIC bring up/characterization and HDMI, USB 3.1 and DP electrical test boards. You can find out more about Zebax here http://www.zebax.com/
EDADoc, www.en.edadoc.com provides PCB design and services and is experienced in HAPS daughter board design.
See all the HAPS Connect Members here: http://www.synopsys.com/Systems/FPGABasedPrototyping/Pages/haps-connect-program.aspx (EDADoc is not listed yet but will be soon)
Don’t forget to sign up to the RSS feed (link below) and get my blog posts sent directly to you
Posted in HAPS Connect Program | Comments Off
Posted by Michael Posner on September 19th, 2014
This week at SNUG Japan I presented on how you can utilize FPGA-based prototyping to differentiate your products. Basically the theme of the presentation was earliest, fastest and highest debug. The earlier a prototype is made available the more productive you can be with it translating into accelerated time to market. The faster the prototype the more tests or complex scenarios could be run translating into higher quality products. With earlier prototype availability and more complex software being run you need better debug capabilities to rapidly track down bugs. The presentation seemed to be very well received and if you have a SolvNet ID you should be able to find the presentation within the SNUG proceedings soon.
Another of the presentations was “Successful Complex GPU IP Implementation on Synopsys HAPS Platforms using ProtoCompiler” which covers the details on the implementation of Imagination’ PowerVR 6XT Dual core GPU on HAPS. There was a live demonstration of the system during the social event after the technical track. Below you can see Andy, one of the Synopsys Application Consultants standing behind the demo booth.
The GPU partitioned across four Xilinx Virtex-7 FPGA’s using ProtoCompiler and is running at over 12 MHz. A fifth FPGA is used as the testbench and interface to the host PC. DriverLive OpenGL is executing on the platform with real time video output. Andy helped setup this same demonstration at SNUG in Taiwan. He seems happier in Taiwan, I wonder why?
There were some other interesting demos, the first was by Fujitsu Semiconductor who was showing off their development platform for the S70 and S73 SoC’s. The Fujitsu S70 development board is connected to a HAPS system via a PCIe Gen2 link. The HAPS extends the development platform and enables customers of the Fujitsu S70 to test their own IP and subsystems.
Another demo was of the DesignWare PCIe Gen3 solution. The PHY test chip board is HUGE. I’m not sure if you can see it but there is a HAPS system attached to the top of it.
Finally there was a demo of the DesignWare IP Prototyping Kit for USB 3.0, part of the IP Accelerated Initiative. The demo was pretty nifty, it starts with all the hardware turned off, the system is then switched on and you watch Linux boot up in a matter of seconds right in front of you. This shows the power of the setup to enable immediate productivity for either early software development for the IP, IP configuration and HW/SW validation
Finally a question, what is the nearest planet to the Sun? Post a comment to respond.
Posted in Bug Hunting, DWC IP Prototyping Kits, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation | 2 Comments »
Posted by Michael Posner on September 13th, 2014
This week I’ve spent most of my time busting the top three myths of FPGA-Based Prototyping, specifically in respect to the HAPS solution based. The top 3 are:-
- Capacity limited to less than 100 Million ASIC Gates
- It takes months to get prototype working
- Limited debug visibility
These myths are cast backs from the dark ages of FPGA-based prototyping, also known as BMWS, Before Mick Worked at Synopsys, which was a very long time ago, refer to this blog for details http://blogs.synopsys.com/breakingthethreelaws/2014/09/how-to-shaped-the-eda-landscape-and-the-world-we-live-in/
Lets take the first myth: Capacity limited to less than 100 Million ASIC Gates. The HAPS-70 series of FPGA-based prototyping hardware is based on the Xilinx Virtex-7 2000T FPGA’s. Synopsys rates each of these as 12 million ASIC gates, which is a conservative measure coming from years of experience in synthesizing ASIC RTL to FPGA. When the HAPS-70 series was launched back in 2012 Synopsys supported the automated and seamless integration of up to 12 FPGA’s which is equivalent to 144 Million ASIC Gates…. Myth BUSTED !!!! The unique HAPS architecture with its intelligent flexible interconnect architecture (rather than fixed PCB traces), combined with the HAPS proprietary high speed time domain multiplexing, enables the multi-FPGA system to be tailored to the SoC design under test achieving the highest of performance.
But wait…. There’s more….
At the same time that Synopsys launched ProtoCompiler, automated prototyping software for HAPS, we also launched support for up to 288 Million ASIC gates, 24 FPGA’s in a system. ProtoCompiler delivers the design flow managing the large SoC Prototyping project and a HAPS daughter board called the HAPS External Clock Distribution Board, HAPS-ECDB, manages the seamless clocking, reset, configuration and synchronizing across systems. So not only is the myth of capacity limited to 100 Million ASIC gates BUSTED, it’s obliterated. To add credibility to this we even have customers utilizing such systems.
Now for the second myth: It takes months to get prototype working. This problem has been solved with integration between prototyping hardware and software. Even before ProtoCompiler was launched Synopsys delivered Certify automating the flow from ASIC RTL to FPGA-based prototype. To be honest what Certify lacked was a robust partition engine and in-depth integration with the hardware. ProtoCompiler was built with full integration and knowledge of the HAPS hardware target and a partition engine which can leverage the HAPS architecture flexibility. The result is that the time to first prototype (TTFP) can be reduced to as little as a week from first RTL drop…. Myth BUSTED !!!
The great thing is that due to the close integration of ProtoCompiler with HAPS you don’t trade off performance either so the end model still delivers on the #1 requirement of prototyping which is performance.
Time to bust myth 3: Limited debug visibility. First we need to get one thing straight, in FPGA-based prototyping there are hardware limitations as to how much debug data can be stored. While it’s technically possible to get simulator like visibility in HAPS the tracing logic and size of the memory storage needed would make it cost ineffective. But debug visibility is not limited. Take the HAPS-DX, it has built-in HAPS Deep Trace Debug. HAPS Deep Trace Debug is an integrated capability of ProtoCompiler DX combined with the HAPS-DX hardware. You have the capability to do simulator like debug of the design under test. How much debug visibility do you get… well an example is that you can trace 128 signals with a capture rate of 100 MHz hardware speed and you would get 5 seconds of debug data. Or you could trace more signals for a shorter period… I say Myth Busted !!!
But guess what… there is more…..
As seen above, Synopsys also delivers a multi-FPGA solution as part of ProtoCompiler which does not require memory on the HAPS system itself or usage of the Hapstrak connectors. Again this capability is enabled by the tight integration between the ProtoCompiler software and the HAPS hardware systems.
- Capacity limited to less than 100 Million ASIC Gates – BUSTED !!! Synopsys delivers 288 Million ASIC gate support
- It takes months to get prototype working – BUSTED !!! ProtoCompiler & HAPS delivers TTFP in as little as 1 week
- Limited debug visibility – BUSTED !!! ProtoCompiler & HAPS delivers deep trace debug
Are there any more FPGA-based prototyping myths you would like me to bust? Drop me a comment and I’ll work on them
Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, Man Hours Savings | Comments Off
Posted by Michael Posner on September 6th, 2014
It might be hard for you to comprehend but I have just celebrated my 20th year at Synopsys!!! (I started when I was 12…….. honest and I’ve just celebrated by 29th birthday for the 14th time) This blog is a short history of my time at Synopsys and how I think I have helped shape the EDA landscape which in turn has influenced the world we live in today.
I joined Synopsys in October 1994 as a hotline engineer supporting Design Compiler, as did everyone back in those days, but also to specifically focus on the newly acquired Logic Modeling line of products, the LM/MS hardware modelers and the simulation SmartModels.
Boy I look young in that picture…… Alex, the person to the right of me, was hired a month before me, he too is still in the EDA business just proving that once you enter its very hard to leave. Alex was interviewed based on his great technical collage record, I was interviewed as the hiring manager loved Land Rovers and I had put in my aspirations section that I one day wanted to own one… The hiring manager also found it funny that I had put “Birdman of Brighton 1992” as one of my achievements. (Which is true by the way). Anyone with a sense of humor and some technical skills needed to be interviewed he said. Supporting hardware modeling (extra points for those of you who know what hardware modeling was) and SmartModels put me squarely in the Verification and Validation track and that theme continued during all my years at Synopsys.
While in the support role in the UK I used to create examples of the Hardware Modeler and SmartModels in action. I send these to customers to help them ramp up with the tools. At the same time I packaged them up and posted them on an internal website so other Synopsoids could use them. Well this leveraged activity was noticed by management in the USA and in 1997 I moved to the Synopsys Oregon office and took on the role as Technical Marketing Manager for the Hardware Modelers and SmartModel products. As I remember it these were the years of Synopsys, the soul of silicon. I create a DAC demo using the hardware model of the TMS320C51 and the Synopsys VSS simulator (bonus points if you remember VSS) which flashed Synopsys the Soul Of Silicon across a simulated display. In 1999, during my time as Technical Marketing Manager I was awarded the very prestigious Synopsys “Excellence” Award, recognizing my dedication to customer success and excellent execution. I’ve been striving to be awarded this for a second time but even though I have voted for myself a number of times I’ve not received it again. I helped launch Synopsys Arkos emulator and Synopsys Cyclone cycle based simulator, both of which were amazing technology (IMO). Cyclone was a simulator that you could rewind!! Fancy that, hit a bug and simply rewind the simulation and review the events leading up to the issue….
In 2001 I started the ramp up to true marketing and was promoted to Product Marketing Manager where I revolutionized Synopsys memory models by introducing the DesignWare Memory Models which were compiled RTL with an intelligent C core enabling advanced testbench capabilities. At the same time I took on responsibility for the ARM AMBA-Bus-Based synthesizable IP which is still a critical part of the DesignWare IP offerings and utilized in 1000’s of chips.
In 2006 I was promoted again and took on the additional roll of DesignWare SATA IP. It was really more of the same in respect to my job requirements but as I always strive for excellence I did my very best job to drive the adoption of the IP solution. It was during this role that I started to travel much, much more especially internationally. This travel has not stopped and I’m pretty sure my rear end is now the shape of an economy airplane seat. We rode the semiconductor downturn and during this time I was happy that my “yes” approach to everything paid off. I’m always happy to take on anything that is thrown at me and during the years of reduced expenses I was happy that I was reviewed as an essential resource bringing high value to Synopsys.
2010 signaled by shift from IP to FPGA and I took on the role Product Marketing Manager for Synopsys FPGA-Based Prototyping products, both the HAPS hardware and the software products. I felt refreshed after doing IP for so long it was nice to have new challenges and REAL hardware again. Of course with real hardware comes totally different problems to solve. So all of this brings us to today,
I’m now Director of Marketing for FPGA-based prototyping products. 20 years of hard work has got me here and I’m really happy to have been a part of Synopsys, the best EDA company on the planet (IMO). Yes things have changed, Synopsys was pretty small when I first joined, less than 1000 people, and now we have people, processes and thousands of products, but the core values have not changes. I’m looking forward to my next set of challenges….. I also think about how many products on the market have been influenced by the products that I have lead, it’s hundreds and some have revolutionized our daily lives.
Thanks to everyone I have worked with over the last 20 years..
I need a couple of ideas of FPGA-based prototyping topics to blog about, please send me a comment with some ideas
Posted in Humor | 2 Comments »
| © 2015 Synopsys, Inc. All Rights Reserved.