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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Top 3 Myths of FPGA-based prototyping BUSTED

Posted by Michael Posner on September 13th, 2014

Myth Busted

This week I’ve spent most of my time busting the top three myths of FPGA-Based Prototyping, specifically in respect to the HAPS solution based. The top 3 are:-

  • Capacity limited to less than 100 Million ASIC Gates
  • It takes months to get prototype working
  • Limited debug visibility

These myths are cast backs from the dark ages of FPGA-based prototyping, also known as BMWS, Before Mick Worked at Synopsys, which was a very long time ago, refer to this blog for details http://blogs.synopsys.com/breakingthethreelaws/2014/09/how-to-shaped-the-eda-landscape-and-the-world-we-live-in/

Lets take the first myth: Capacity limited to less than 100 Million ASIC Gates. The HAPS-70 series of FPGA-based prototyping hardware is based on the Xilinx Virtex-7 2000T FPGA’s. Synopsys rates each of these as 12 million ASIC gates, which is a conservative measure coming from years of experience in synthesizing ASIC RTL to FPGA. When the HAPS-70 series was launched back in 2012 Synopsys supported the automated and seamless integration of up to 12 FPGA’s which is equivalent to 144 Million ASIC Gates…. Myth BUSTED !!!! The unique HAPS architecture with its intelligent flexible interconnect architecture (rather than fixed PCB traces), combined with the HAPS proprietary high speed time domain multiplexing, enables the multi-FPGA system to be tailored to the SoC design under test achieving the highest of performance.

But wait…. There’s more….

HAPS External Clock Distribution Board, HAPS-ECDB, automated the integration of up to 24 Xilinx Virtex-7 2000T FPGA's

At the same time that Synopsys launched ProtoCompiler, automated prototyping software for HAPS, we also launched support for up to 288 Million ASIC gates, 24 FPGA’s in a system. ProtoCompiler delivers the design flow managing the large SoC Prototyping project and a HAPS daughter board called the HAPS External Clock Distribution Board, HAPS-ECDB, manages the seamless clocking, reset, configuration and synchronizing across systems. So not only is the myth of capacity limited to 100 Million ASIC gates BUSTED, it’s obliterated. To add credibility to this we even have customers utilizing such systems.

Now for the second myth: It takes months to get prototype working. This problem has been solved with integration between prototyping hardware and software. Even before ProtoCompiler was launched Synopsys delivered Certify automating the flow from ASIC RTL to FPGA-based prototype. To be honest what Certify lacked was a robust partition engine and in-depth integration with the hardware. ProtoCompiler was built with full integration and knowledge of the HAPS hardware target and a partition engine which can leverage the HAPS architecture flexibility. The result is that the time to first prototype (TTFP) can be reduced to as little as a week from first RTL drop…. Myth BUSTED !!!

ProtoCompiler integrated with HAPS delivering Time to First Prototype, TTFP, in as little as 1 week

The great thing is that due to the close integration of ProtoCompiler with HAPS you don’t trade off performance either so the end model still delivers on the #1 requirement of prototyping which is performance.

Time to bust myth 3: Limited debug visibility. First we need to get one thing straight, in FPGA-based prototyping there are hardware limitations as to how much debug data can be stored. While it’s technically possible to get simulator like visibility in HAPS the tracing logic and size of the memory storage needed would make it cost ineffective. But debug visibility is not limited. Take the HAPS-DX, it has built-in HAPS Deep Trace Debug. HAPS Deep Trace Debug is an integrated capability of ProtoCompiler DX combined with the HAPS-DX hardware. You have the capability to do simulator like debug of the design under test. How much debug visibility do you get… well an example is that you can trace 128 signals with a capture rate of 100 MHz hardware speed and you would get 5 seconds of debug data. Or you could trace more signals for a shorter period… I say Myth Busted !!!

But guess what… there is more…..

HAPS Deep Trace Debug with non-intrusive and seamless integration

As seen above, Synopsys also delivers a multi-FPGA solution as part of ProtoCompiler which does not require memory on the HAPS system itself or usage of the Hapstrak connectors. Again this capability is enabled by the tight integration between the ProtoCompiler software and the HAPS hardware systems.

In summary:-

  • Capacity limited to less than 100 Million ASIC Gates – BUSTED !!! Synopsys delivers 288 Million ASIC gate support
  • It takes months to get prototype working – BUSTED !!! ProtoCompiler & HAPS delivers TTFP in as little as 1 week
  • Limited debug visibility – BUSTED !!! ProtoCompiler & HAPS delivers deep trace debug

Are there any more FPGA-based prototyping myths you would like me to bust? Drop me a comment and I’ll work on them

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, Man Hours Savings | Comments Off

How to shape the EDA landscape and the world we live in

Posted by Michael Posner on September 6th, 2014

It might be hard for you to comprehend but I have just celebrated my 20th year at Synopsys!!! (I started when I was 12…….. honest and I’ve just celebrated by 29th birthday for the 14th time) This blog is a short history of my time at Synopsys and how I think I have helped shape the EDA landscape which in turn has influenced the world we live in today.

I joined Synopsys in October 1994 as a hotline engineer supporting Design Compiler, as did everyone back in those days, but also to specifically focus on the newly acquired Logic Modeling line of products, the LM/MS hardware modelers and the simulation SmartModels.

Mick & Alex enjoy a beer in the UK

Boy I look young in that picture…… Alex, the person to the right of me, was hired a month before me, he too is still in the EDA business just proving that once you enter its very hard to leave. Alex was interviewed based on his great technical collage record, I was interviewed as the hiring manager loved Land Rovers and I had put in my aspirations section that I one day wanted to own one… The hiring manager also found it funny that I had put “Birdman of Brighton 1992” as one of my achievements. (Which is true by the way). Anyone with a sense of humor and some technical skills needed to be interviewed he said. Supporting hardware modeling (extra points for those of you who know what hardware modeling was) and SmartModels put me squarely in the Verification and Validation track and that theme continued during all my years at Synopsys.

While in the support role in the UK I used to create examples of the Hardware Modeler and SmartModels in action. I send these to customers to help them ramp up with the tools. At the same time I packaged them up and posted them on an internal website so other Synopsoids could use them. Well this leveraged activity was noticed by management in the USA and in 1997 I moved to the Synopsys Oregon office and took on the role as Technical Marketing Manager for the Hardware Modelers and SmartModel products. As I remember it these were the years of Synopsys, the soul of silicon. I create a DAC demo using the hardware model of the TMS320C51 and the Synopsys VSS simulator (bonus points if you remember VSS) which flashed Synopsys the Soul Of Silicon across a simulated display. In 1999, during my time as Technical Marketing Manager I was awarded the very prestigious Synopsys “Excellence” Award, recognizing my dedication to customer success and excellent execution. I’ve been striving to be awarded this for a second time but even though I have voted for myself a number of times I’ve not received it again. I helped launch Synopsys Arkos emulator and Synopsys Cyclone cycle based simulator, both of which were amazing technology (IMO). Cyclone was a simulator that you could rewind!! Fancy that, hit a bug and simply rewind the simulation and review the events leading up to the issue….

Flow for using Synopsys' hardware modeler with Synopsys' Cyclone cycle based simulator

In 2001 I started the ramp up to true marketing and was promoted to Product Marketing Manager where I revolutionized Synopsys memory models by introducing the DesignWare Memory Models which were compiled RTL with an intelligent C core enabling advanced testbench capabilities. At the same time I took on responsibility for the ARM AMBA-Bus-Based synthesizable IP which is still a critical part of the DesignWare IP offerings and utilized in 1000’s of chips.

In 2006 I was promoted again and took on the additional roll of DesignWare SATA IP. It was really more of the same in respect to my job requirements but as I always strive for excellence I did my very best job to drive the adoption of the IP solution. It was during this role that I started to travel much, much more especially internationally. This travel has not stopped and I’m pretty sure my rear end is now the shape of an economy airplane seat. We rode the semiconductor downturn and during this time I was happy that my “yes” approach to everything paid off. I’m always happy to take on anything that is thrown at me and during the years of reduced expenses I was happy that I was reviewed as an essential resource bringing high value to Synopsys.

2010 signaled by shift from IP to FPGA and I took on the role Product Marketing Manager for Synopsys FPGA-Based Prototyping products, both the HAPS hardware and the software products. I felt refreshed after doing IP for so long it was nice to have new challenges and REAL hardware again. Of course with real hardware comes totally different problems to solve. So all of this brings us to today,

Mick Posner, 007, Director of Marketing, FPGA-based Prototyping Products

I’m now Director of Marketing for FPGA-based prototyping products. 20 years of hard work has got me here and I’m really happy to have been a part of Synopsys, the best EDA company on the planet (IMO). Yes things have changed, Synopsys was pretty small when I first joined, less than 1000 people, and now we have people, processes and thousands of products, but the core values have not changes. I’m looking forward to my next set of challenges….. I also think about how many products on the market have been influenced by the products that I have lead, it’s hundreds and some have revolutionized our daily lives.

Thanks to everyone I have worked with over the last 20 years..

I need a couple of ideas of FPGA-based prototyping topics to blog about, please send me a comment with some ideas

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Posted in Humor | 2 Comments »

Speeding Prototype to Host Connectivity

Posted by Michael Posner on August 14th, 2014

A Chain picture which I thought would represent the link from host to HAPS.

A while back I talked about the various prototype to host connectivity modes facilitating IP and SoC validation including Hybrid Prototyping. The use of the Synopsys Universal Multi-Resource Bus, UMRBus for short, is key to deploying these use modes. Synopsys introduced the UMRBus along with the HAPS-60 systems and it’s popularity has grown ever since. The UMRBus provides an easy to use infrastructure for any user of the HAPS systems to configure, monitor and expend the capabilities of the HAPS system.

The UMRBus technical architecture. One side you have the hardware client application interface module, CAPIM for short. The otherside you have the generic UMRBus API which is the software layer which you program against

Synopsys provides the high level UMRBus API and the hardware interface modules along with the HAPS systems. These are the same building blocks that the Hybrid transactors are built on top of and which are delivered as part of ProtoCompiler. Multiple UMRBus connection modes are supported depending on the goal of the usage such as simple remote access and configuration to full blown high performance data streaming and Hybrid Prototyping. The follow is a list of the various connectivity modes and the expected performance. You can use these to pick the best connectivity solution to match your prototyping needs.

UMRBus over USB. The easiest connection mode as you just plug a USB cable from the host into the HAPS System either HAPS-70 or HAPS-DX

Typically the USB connection mode is used when all you want to do is remotely configure and debug the prototype.

UMRBus pod connecton. This provides the most flexibility in connectivity with UMRBus access to any and every FPGA in the system.

The UMRBus pod enables a seamless interface into the HAPS system with direct visibility into any FPGA in the HAPS chain.

This is UMRBus over a PCIe Paddle board. Basically the UMRBus is a layer on top of PCIe delivering the UMRBus capabilities over a very high performance link

This is a very high performance UMRBus mode for the HAPS-DX making it perfect for IP validation where lots of data need to be streamed on and off of the prototype. Using this mode over 400 MB/s streaming data bandwidth can be achieved

Same high performance as UMRBus over the paddle board, over 400MB/s with the added flexibility of a cable based connection

The UMRBus over PCIe MGB connection is similar to the PCIe paddle board version for the HAPS-DX and works for the HAPS-70 via a flexible cable setup. This connection method can also be used on the HAPS-DX and delivers similar performance of over 400MB/s.

We provide example designs showing how each of the UMRBus connection modes can be used as well as integration with the prototyping software tools including the new ProtoCompiler and ProtoCompiler DX. This makes any of the modes super quick to deploy.

So as you can see, lots of options to connect HAPS to a Host for advanced prototyping.

(I’m off on vacation for two weeks, so sorry, I doubt that I’ll blog during that time.)

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Posted in ASIC Verification, Daughter Boards, Hybrid Prototyping, IP Validation, Use Modes | 1 Comment »

Solving the ASIC Prototype Partition Problem

Posted by Michael Posner on August 8th, 2014

A couple of weeks back I posted a humorous list of the quotes I use in my day to day life, one of which is “Hope is not a strategy”

Well as it turns out this caused quite a fluster as apparently hope is a strategy, well sort of. Here is a link to a Harvard Business Review Article – Hope as a Strategy, well sort of.


The premise is that when hope is based on real-world experience, knowledge and tangible and intangible data, it results in trust, which is necessary to implementing any strategy. What do you think about that? Is the word hope being used to explain the standard  practice of planning and factoring in the calculated risk assessment? If yes, this is going to totally revolutionize my life.

To ensure we have a little FPGA-based prototyping content this week I highly recommend the new Synopsys white paper on Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

ProtoCompiler whitepaper explaining how the challenge of multi-FPGA ASIC prototyping is solved automatically

The white paper describes the challenges of ASIC prototyping when the design has to be split up over multiple FPGA’s and how the new ProtoCompiler tool solves these challenges automatically. It’s a highly technical paper with in-depth data on how to rapidly partition an ASIC design ready for high performance prototyping. The ProtoCompiler tool can partition process a design in lass than 5 minutes and highlights bottlenecks which will limit the prototyping performance and pointers on how to resolve to deliver the maximum optimization.

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Posted in Humor, Man Hours Savings, Project management, System Validation, Use Modes | 1 Comment »

PCIe trends and how to accelerate Gen3 prototyping

Posted by Michael Posner on August 1st, 2014

Market trends for PCIe between 2013 and 2014

We are seeing PCIe Gen3 being integrated into many different types of SoC’s. The above summarizes the changes we are seeing in the market across 2013 and 2014. One notable area is that PCIe is moving into enterprise storage with PCIe being used for the interface to NAND flash storage devices. The below picture shows the key needs in the segments. PCIe Gen 3 is a great fit for storage as it offers 8Gb/s transport rate across a single lane with x2, x4, x8, x16 lane configurations resulting in huge bandwidth potential. My thanks to Scott Knowlton, of the Express Yourself Blog for the PCIe market data and segment analysis

PCie market segmentation and the main requirements of each

In June 2014 Synopsys ran an internal “FPGA Fest” this is an event where the Synopsys prototyping engineering teams invites all our field application consultant specialists into town for an intensive week of technical training. I attended the training as well and snapped off a couple of pictures of the PCIe Gen3 x4 lane example design training. The design is the DesignWare PCIe Gen3 controller core configured as an end point with x4 lanes. It includes an embedded DMA and software application that enables data to be read/written from and to the prototype. The DesignWare controller IP core is implemented on the HAPS-DX system and interfaces to the PCIe Gen3 capable host via the Xilinx high speed IO’s (Rocket IO transceivers). Don’t forget, I blogged about PCIe Gen3 on HAPS-70 in the past.

Top view of the HAPS-DX plugged into the host

HAPS-DX plugged into PCIe Gen3 capable host

Side view of the HAPS-DX. Here you can clearly see the HAPS-DX kit’s included PCIe Gen3 x8 capable paddle board. This is a daughter board which enables a direct passive connection from the HAPS-DX to the host’s PCIe slot. The paddle board is a highly cost effective way to create the physical link from the HAPS-DX to the host. We offer cabled versions as well which provide greater flexibility in the HAPS-DX placement but at additional cost of course. The SI characteristics of the HAPS PCIe Gen3 paddle board are fantastic (not a technical term I know…) ensuring a stable and robust connection.

View of HAPS-DX PCIe gen3 x8 capable paddle board connected to PCie Gen3 capable host PC

Finally the proof is in the pudding. Here is a picture of the reported bandwidth of the PCIe Gen3 x4 lane connection. WOW, ~700MB/s that’s fast.

Synopsys software application showing results of DesignWare PCIe Gen3 x4 end point running on HAPS-DX. ~700 MB/s fast

Do you want a PCIe Gen3 setup like this? If yes, contact me as we are preparing to release the IP Prototyping Kit for it.

Off subject…. A while back I built a small bird house with my son and he requested we put a label on it saying “Welcome Birds” so the birds would know it was for them. Well as it turns out the sign worked and we have had little birds going in and out all summer. My son said to me last weekend, “Daddy we need to build another bird box for all the other birds” I’ve been busy so to divert his attention I said that if he designed it I would help him build it. 5 minutes later he returns with a piece of paper with the design. He had designed a bird house high rise, yes, a multi-story bird house. Well I promised that if he designed it, we would build it and so here is the result.

High rise or multi-story bird house that Mick Posner built with this son

I should note that his design had way more floors but I negotiated him down to just three. We all love how it turned out. My son helped with the cutting on my radial arm saw, nailing with my framing nail gun, drilling the holes and screwing in the bolts. My father exposed me to tools when I was young, I am trying to do the same in a safe and controlled manor. All the timber used was from the scrap left over from tearing out one of our old fences.

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Posted in Daughter Boards, DWC IP Prototyping Kits, IP Validation, Mick's Projects, Real Time Prototyping | 1 Comment »

HOW TO: Achieve Fastest Time to Operational Prototype and Highest Performance

Posted by Michael Posner on July 24th, 2014

Road runner the bird, not the cartoon

If you didn’t know the above picture is of the greater roadrunner (Geococcyx californianus). Trust me I didn’t just make up the Latin name. The Latin name means “Californian earth-cuckoo”. This blog is about how to achieve the fastest time to operational prototype, accelerating ASIC and SoC verification, speeding validation and the road runner was first image that popped into my mind when I wanted to articulate fast. There has been a lot of talk about Time To First Prototype, TTFP, recently so I thought I would blog a how to on achieving accelerated TTFP. I thought I’d raise the bar and deliver a how to on both achieving this AND get the highest operational performance out of the FPGA-based prototype.

If you have found yourself reading this blog you are looking for the magic solution but I am afraid I have to burst your bubble, there is no black magic solving this problem.

Home made no back magic logo

It’s better, all you need is a fully integrated FPGA-based prototyping solution. Yep, that simple, blog done, thank you :) (What? You want to know why an integrated solution solves all your problems!) To answer this we need to quickly review the challenges to FPGA-based prototyping. The below picture describes the challenges to prototyping, based on a recent survey that Synopsys ran. It also includes on the left the solutions to these individual challenges.

Click on the images to view the whole picture. I made them large so they were easy to read.

Survey results defining the challenges of FPGA-based Prototyping and the combined HW/SW capabilities needed to solve them

Do you spot the common theme? The challenges cannot be solved with hardware or software alone, it’s the combination that solves the problem. An example is performance, I’ve blogged about this is the past that it’s the combination of hardware interconnect flexibility and the ability to deploy a high speed time domain, differential signaling, solution that is the key to achieving the highest performance. In this case the software has to have intimate knowledge of the hardware, it’s electrical and SI characteristics to be able to correctly implement the high speed time domain IP in the multi-FPGA prototype design. At the same time ALL hardware must meet a minimum level of performance across all interconnections to ensure that when the prototype design image is deployed across many systems it always runs reliably.

Summary examples of what integrated capabilities are of the Synopsys solution

Debug is another good example. To deliver the highest debug visibility you need both a software flow that enables instrumentation of the RTL, graphical display AND hardware capabilities to store the physical data. The result of integration reduces your need for expertise as the solution has the expertise. Same for partitioning across multiple FPGA’s, as the software is hardware aware and the hardware can be tailored to the software recommended best interconnect topology the result is optimal.

Lucky for you, Synopsys delivers a fully integrated solution of ProtoCompiler plus HAPS so you don’t have to wait. And… if you call now, not in 5 minutes but now, I’ll personally visit your site to say hello.

Synopsys' integrated FPGA-based prototyping solution including ProtoCompiler software, HAPS FPGA-based hardware, debug, DesignWare IP, Support, HAPS Connect Program

While ProtoCompiler was only recently launched its delivering some fantastic customer results, see below, accelerating time to first prototype and delivering the highest performance. This was a customer design, 48 Million ASIC gates, four Xilinx Virtex-7 FPGAs. ProtoCompiler is fully integrated with HAPS leveraging its strengths. HAPS interconnect can be tailored based on the ProtoCompiler recommendations and ProtoCompiler understands the HAPS architecture and resources such as clocks and resets. ProtoCompiler is built around a stable code base of Synopsys’ mature and unique compilation and synthesis engines delivering the highest QoR for out-of-the-box results.

Synopsys achieves fastest time to prototype and highest performance operation with ProtoCompiler plus HAPS

A fully integrated solution delivers not only accelerated time to first prototype and highest performance but also reduces your effort as it’s doing the hard work for you. Just don’t tell your boss otherwise he will give you more work.

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Posted in ASIC Verification, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation | 2 Comments »

Going vertical for all the right reasons

Posted by Michael Posner on July 17th, 2014


By far my favorite aircraft growing up was the Harrier jump jet. Back in those days it was the only jet aircraft with vertical takeoff and landing (VTOL) capabilities. I dreamed of flying one and even owning my one. Actually I still dream of owning one. I like the idea of a helicopter as you can vertically takeoff and land meaning you have a wide range of landing zones. The problem with a helicopter is that it’s very slow in comparison to a plane so it would take you ages to get any real distance. Hence the Harrier was a perfect option for me, vertical takeoff and landing and jet speed in the air, it’s the best of both worlds.

In the land of FPGA-based prototyping there is a lot of horizontal and not much vertical, especially when it comes to daughter boards. Traditional daughter boards are flat or horizontally mounted to the system such as the HAPS DDR3 daughter board pictured below.  


There is nothing wrong with a daughter board like this, in fact the above daughter board has exceptional SI characteristics and operates at very high performance. However we found that some customers ran into challenges when it came to building custom daughter boards specifically tailored to their needs. Here is a summary of some of the issues they ran into.

  • Customers daughter board was quite big but it only required a couple of IO’s interfacing to the system.  Often the daughter board covered up more connectors or blocked airflow and fans just because the daughter board PCB had to be large to accommodate the custom logic
  • The daughter board required a big connector, but again only required a couple of IO’s. The size of the connector forced the size of the daughter board PCB to again cover things.
  • Once in a while the customer actually wanted to get access to both sides of the daughter board. Sometimes this was to connect to both sides, other times to probe. They would build a long daughter board expanding out of the system to do this. It was typically mechanically unsound.

Enter the Synopsys R&D Boffins! They could have ignored this little gripe with daughter boards, lets face it, the issue is annoying but not the end of the world. But that’s not good enough for the Synopsys! So drum roll please……. for the worldwide announcement of the availability of the VERTICAL HAPS daughter board. Yes, vertical….


The new vertical daughter board addresses the issues laid out above.

  • For daughter boards that use relatively few IOs, say up to 50 (HT3 connector IO count) but require more PCB real estate than a typical LAB board, building in a vertical way is excellent. Look at the picture, the board form factor is huge yet it only plugs into and utilizes one HT3 connector. It does not block any other connectors or airflow.
  • Same for the problem of the big connector, a vertical board enables a HUGE connector to be used if wanted.
  • Oh my, you can even access both sides of the daughter board, perfect for additional PCB access and probing.


The HAPS HT3 spec is being updated to define the new HT3 vertical daughter board and will be available to all existing HAPS-70 customers. Synopsys validated the form factor and usage and now shares it with any HAPS-70 customer that wants it.

So now we can all go vertical. Ease of use, functionally with performance, it’s like the Harrier jump jet of FPGA-based prototyping daughter boards. Someone once made fun of the upper frame on the HAPS-70 systems, now who’s laughing……

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Posted in Daughter Boards, Project management | 1 Comment »

Off the Cuff Video from DAC meets Zombie apocalypse

Posted by Michael Posner on July 10th, 2014


One of my worst nightmares is to completely fail at something, actually one of my worst nightmares is a Zombie apocalypse where I am one of the zombies but that’s a story for another day. At DAC I was interviewed by EDACafe, one of those 3-5 minute casual interview videos that are done in one take. They call them casual but I can tell you they are nowhere near casual, I am personally super nervous in these. I am happier with well scripted and edited videos but I also understand that the off-the-cuff videos are well received by the viewer.

Anyway, here is the video from DAC 2014.


Remember the video is completely unscripted and shot in one take. I’m not a fan of seeing myself on video but I must admit that suit and tie combo rock. You can also hardly tell that I’m recovering from pneumonia.


Talking of off-the-cuff videos at DAC, here is another one (link below), this time featuring Asheesh Khare from Synopsys, explaining the new DesignWare IP Prototyping kits. All I can say is WOW!! Not only does Asheesh explain the solution very clearly he does it at the same time as connecting up the hardware and powering it up. Now that’s a professional at work. In future I will be renting Asheesh as my body double and have him star in all my videos.


And finally one last video from a USA 4th of July party….. https://www.youtube.com/watch?v=dDKQt4SY5Qs Nothing like celebrating the USA independence from England with beer and a big canon. Enjoy.

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Posted in DWC IP Prototyping Kits, Early Software Development, Humor, IP Validation, Man Hours Savings, Use Modes | Comments Off

You don’t buy a dog and bark yourself

Posted by Michael Posner on July 2nd, 2014


I have a set of witty one liners which I use to respond to a variety of situations that I encounter in my everyday life. Some are insightful and designed to share my wisdom while others are just supposed to be a little humorous. The title of this blog is one and I have listed a set of my favorite quotes below including the typical situations which I use them. Feel free to use these in your everyday situations as I am sure they will be as impactful for you as they are for me. I might not have been the first person to come up with these quotes so don’t get upset if you use the same ones already.

“Don’t let the technical details get in the way of a good story”
As I’m in Marketing I use this one frequently. Many times I see presentation material getting bogged down in the nitty gritty technical feature review and missing the VALUE and BENEFIT that the solution brings to the customer. This is when I use this quote to remind the team to start with the end, what is the benefit to the customer and then construct a story to deliver this message.


“Hope is not a strategy”
Oh by far this is my most used quote. I never rely on hope, I make things happen by planning out an execution path to reach the end goal. All too often I hear things like “I hope we can get this working” or “I hope we can repeat this success”. Hope is not going to help, you need to help yourself and create a plan then execute on it. People who rely on hope rarely succeed. Actually, there is a whole book on this topic.


“I see a lot of hope and not a lot of action”
I typically use this quote hand in hand to the one above. I use this to describe a plan which has a lot of holes or gaps between actions or if I see no progress towards a goal. It’s great to have a goal with a plan to reach it but if you are not putting in the effort to action the plan you are back to hope and as we now know, hope is not a strategy.

“A vision without a plan is just a wish”
Notice there is a bit of a theme going on here. It’s great to have a vision but if you don’t have an execution plan to work towards you are just wishing for it to happen. Life is not a movie, wishes are not real so if you want to deliver on a vision you need to plan and execute.


“Givers need to set limits as takers rarely do”
I’m a giver, this does not mean I’m a sheep and follow the herd it means that I set a very high bar for myself and always want to over achieve and impress. This of course can lead to personal issues when it’s taken for granted that you will always get the job done no matter of the situation. It’s fine for a giver to push back and set limits. Quote by Henry Ford, American industrialist a man I admire greatly.


“You’re quick or you’re dead in this game”
I use this one to respond to a variety of situations. Sometimes I use this when I rush to get to the front of the line at the airport when a flight in cancelled. Ok, so a situation like this is not life or death but if you are going to secure a seat on the next flight you have to act fast. I’ll also use this when I am the first to get a second serving to food, similar to survival of the fittest.


“Do not judge by the problem, judge by how the problem is solved”
I love this quote. A while back the hotel laundry shredded the sleeve of one of my very favorite shirts when it got caught in the machine. This could have been a horrible situation but the hotel handled the problem very well. First they found a store that sold the very same shirts, unfortunately the store did not have my size so the hotel was unable to directly replace. They then offered to pay for a new shirt, regardless of the type, when I purchased a new one. As it happens that shirt was purchased in London’s Heathrow airport and while on a business trip I purchased a replacement. 6 months later I return to the hotel which had shredded my shirt and handed them the receipt for the new shirt. The hotel gave me the cash value. My shirt could have been destroyed at any hotel, that stuff happens. Judge by how the problem is solved and not by the problem itself. The problem solving is what sets everybody apart.


“Who needs products when you have PowerPoint”
I don’t actually say this but my R&D team has used it with me when the presentation I created is 12 months ahead of the product deliverables. Marketing at its finest is what I say and linked to the “Don’t let the technical details get in the way of a good story” quote as seen earlier. Also used in the TV Series “Better off Ted” which IMO was one of the funniest TV shows around and I highly recommend it.


And finally, “You don’t buy a dog and bark yourself”
I rarely use this one anymore as to be honest it annoys pretty much everyone you use it with but it does communicate a very powerful message across so use the power wisely. This states, without directly saying it, is this is not my job. I have used this with select individuals when they expect me to do something when clearly I do not have the matching skill set and they do but are just too lazy to do it themselves. This quote is highly abusive so don’t expect the person you use it on to ever speak to you again. (Which is some cases is exactly why I use it)

Do you have other quotes you use day to day in your life? If they are PG rated then please share via comments…

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Posted in Humor | 1 Comment »

B2B for Accelerated Time to First Prototype and Assembly

Posted by Michael Posner on June 27th, 2014


This week Synopsys announced the HAPS Connect Program. The HAPS Connect Program is an eco-system of third-party daughter board and services partners for HAPS systems. The HAPS Connect Program expands the choice of HapsTrak and Multi-Gigabit board and service offerings available for HAPS systems. The first members include Fidus, eInfoChips, Sarokal, Gigafirm, Back9 Designs, HDLabs and Zoro. Synopsys is helping connect business to business to accelerate prototype assembly which I have blogged about before here. The HAPS Connect Program helps customers to:

  • Develop HAPS prototypes faster by leveraging compatible daughter boards from leading industry hardware vendors
  • Reduce project risk by taking advantage of hardware and services from vendors with HAPS system expertise
  • Save on prototype development costs and resources by using products and services tailored for HAPS systems


You can see a full list of participating vendors here.

I personally wanted to launch a program like this as I’ve been working with vendors individually for many years. The HAPS Connect Program formalizes the process making it easier to connect HAPS FPGA-based Prototyping customers with vendors with HAPS expertise. Really what I am saying is this program makes my work easier and as we all know it’s all about me J

I think by now all my readers know that I race cars as a hobby but you probably don’t know that I also love to off-road my Toyota FJ. I was out last weekend and for once managed to get some good pictures of the play. The first two don’t make the trail look that hard but just know that by the end of the day I had beaten up the undercarriage of my truck more than ever before and left me limping home with a blown shock absorber and destroyed right front suspension.

Note that the front tire is floating off the ground


I love how compressed the rear tire is, shows the articulation you can get with this Toyota.


It’s not all about the off road play, the view from this mountain range is beautiful.


Finally the crew


It’s the July 4th USA week next week so I am not sure if I am going to blog yet. I do have LOADS to blog about but wanted to spread it over a couple of blogs as I’ve noticed that my long blogs bore people to death. Over the next couple of weeks I’m going to talk about PCIe Gen3 prototyping at full speed,  more on the Synopsys IP Accelerated Initiative, my video from DAC and information on building vertical daughter boards, yes vertical!! I have also been asked to write up “Mick’s Quotes” these are a set of quotes I use around Synopsys when interacting with my team, peers and other groups within Synopsys. These quotes are deep and you will be able to use them to wow other with your insight.

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Posted in HAPS Connect Program, Man Hours Savings, Milestones | Comments Off