HOME    COMMUNITY    BLOGS & FORUMS    Breaking The Three Laws
Breaking The Three Laws
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

What to use first, Emulation or Physical Prototype?

Posted by Michael Posner on February 19th, 2016

I ran into the article below titled Emulation vs. Prototyping.

http://www.eetimes.com/author.asp?section_id=36&doc_id=1328736

This article ALMOST got it right (IMO), but not quite. Firstly it should not be “vs.”, the two technologies are complementary and typically used side by side so it should be “&”. Secondly, with todays challenges the trend is that engineering teams start with Prototyping, not Emulation. Here I am not talking about Virtual Prototyping which we all know is designed for very early in the project usage, I am talking about FPGA-based Physical Prototyping.

HAPS-80 with HAPS ProtoCompiler production systems in the lab, picture angle 2

The reason is that early SW development is so important and in addition you need to quickly thrash out system level issues. The only way to capture these issues is to run the software, typically an OS, against the hardware and you want to enable a mass of software engineers with these models. Physical Prototyping with a product such as HAPS enables this. There was a SNUG customer presentation by Realtek in Taiwan on this very subject:

http://www.synopsys.com/Community/SNUG/pages/proceedingLp.aspx?loc=Taiwan&locy=2015 Look for TA5.2 Earliest SW/HW Co-Development for Complex SoCs Using ProtoCompiler Enabled FPGA Prototyping Platforms

The presentation presents the use of HAPS ProtoCompiler with HAPS systems to enable early software development and hardware verification.

Remember you still bring up emulation to debug the HW issues that cannot be resolved with pure prototyping.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development | Comments Off

Fantastic New Blog Post, Honest

Posted by Michael Posner on February 12th, 2016

This weeks blog can be found here: https://blogs.synopsys.com/tousbornottousb/2016/02/12/will-usb-type-c-burn-my-device/

Yes, I am using the Breaking the three laws blog to promote my new USB blog. I promise you will see value in this new blog.

So not to disappoint, I’ll share a little project I just completed with you.

I’ve not built anything in metal recently and I wanted to refresh my welding skills.

Mick's welding project

Can you guess what this is going to be?

Mick's welding project, painted black

I bet you didn’t guess that it’s a removable section for my roof rack. This section slots in when the sunroof opening is. The issue it resolves is when I have my roof top tent installed I had to be careful not to step on the sunroof breaking it, or worse, falling through it when it’s open.

Sunroof roof rack cover installed

I think the cover turned out very well and really matches the rest of the rack. Not bad for a home build

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Admin and General, Humor, Mick's Projects | Comments Off

Video: Using HAPS to Verify DesignWare USB Type-C IP Functionality

Posted by Michael Posner on February 5th, 2016

In a continuation of last week’s blog titled “Validating USB Type-C using Physical Prototyping” one of the key USB folks here at Synopsys, Morten Christiansen, made a short 30 second video of the DesignWare USB Type-C physical prototype in action. (Click the picture to take you to the video)

DesignWare USB Type-C on HAPS Video

While this video is short it highlights the real world interactivity and full functionality that only a physical prototype delivers, pre-silicon. It’s understated in this short chip but this video shows a real USB Type-C enabled device being connected to a fully functional physical prototyping hosting the DesignWare USB Type-C IP. Talk about risk reduction!!! Just think about what your boss or prospective customer will think of a real working system, huge boost in the overall confidence of the design tape-out. Oh and lets not forget that you have happy software engineers to as they also get a pre-silicon fully functional platform to debug and develop against.

As the leading provider of interface IP, Synopsys has very high quality standards and an operational physical prototype is a key milestone during our IP development.

Thanks Morton for making this short video!! A couple of the readers may know Morton from his participation in the USB Organization. A quick search of his name finds you a list of the USB specs that Morton helped write.

Want to know more about USB Type-C? Just pop over to the “To USB or not to USB” blog.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

I had a couple of FILO days last week, First In, Last Out. There were just not enough hours in the day to get everything done that I wanted. I’m always in the office before the sun comes up but leaving well after the sun had gone down means it was a very, very long day. Super productive though so it was well worth putting the extra effort in. Work hard so you can play hard as they say.

First In, Last Out - My truck in the Synopsys car park

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Milestones, Real Time Prototyping | Comments Off

Validating USB Type-C using Physical Prototyping

Posted by Michael Posner on January 29th, 2016

USB Type-C Connector

This week Synopsys Introduced the DesignWare USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection. USB has been continually evolving and USB Type-C is the one cable to connect them all. The USB Type-C is already gaining widespread acceptance and is becoming the most rapidly adopted USB standard in history. The need to rapidly adopt a new standard comes with challenges for the design engineers, verification team and the software developers.

Synopsys has solved the challenges for these three groups. The DesignWare IP solution is fully validated and ready to integrate into your design. The digital controller is validated against the analog PHY portion significantly reducing integration risk. Engineers can reduce the time and effort of integrating the IP into SoCs utilizing the DesignWare USB-C 3.1/DisplayPort 1.3 IP subsystems, IP prototyping kits and IP software development kits supported as part of the IP Accelerated initiative. Design engineers, verification engineers and software developers challenges solved!

Physical Prototyping with HAPS and HAPS ProtoCompiler plays a key part in this validation. The HAPS solution is used as the hardware verification platform of choice for the DesignWare IP development team. The HAPS systems are used as the operation platform as part of USB certification. Below you can see the HAPS-DX IP development platform being used as part of USB Type-C certification.

DesignWare USB Type-C compliance testing on HAPS-DX

Below is a close up of the USB Type-C connector.

HAPS USB Type-C daughter board

This highlights one of the key benefits of the HAPS systems, they are highly flexible, modular and can be rapidly adapted using daughter boards to support the latest and greatest interface needs.

Want to know more about USB Type-C? Just pop over to the “To USB or not to USB” blog. Have a look at the right hand side of the page, you might find something that surprises you.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in ASIC Verification, Bug Hunting, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Project management, System Validation, Use Modes | Comments Off

Results from Xilinx UltraScale VU440 based HAPS-80 with HAPS ProtoCompiler

Posted by Michael Posner on January 22nd, 2016

I visited the Synopsys offices again this week and sat down with a couple of the R&D engineers to discuss what our customers should expect in respect to performance when they utilize the new HAPS-80 and HAPS ProtoCompiler. I blogged about this a while back, I now have the latest information.

HAPS-80 with HAPS ProtoCompiler production systems in the lab

These results here are for a multi-FPGA design using the HAPS ProtoCompiler 2016.03 code base targeting the new HAPS-80 system. In this case we are comparing against a design running on HAPS-70 using HAPS ProtoCompiler. The focus of the test is to measure the performance of the pin multiplexing capability which is the typical bottleneck of system performance within a multi-FPGA physical prototype. The results are fantastic, HAPS-80 with HAPS ProtoCompiler 2016.03 multi-FPGA pin multiplexing capability using Synopsys’ proprietary HSTDM is exhibiting an increase in performance on average of 15% right out of the box. This is a direct apples to apples comparison for the same pin multiplexing ratio. It’s of course possible that with the move to the new systems that other factors also improve the achievable performance. The R&D team also believe there is room for improvement but would like more time to stress test the higher performance version to ensure 100% reliable operation across all HAPS-80 systems.

There have also been enhancements made in HAPS ProtoCompiler 2016.03 timing driven system route engine that on average cuts ~8ns off the critical path. Take for example your systems are currently running at 15 MHz which is a 66ns period. Shave off 8ns resulting in a period of 58ns and you increase the system performance to over 17 MHz a 14% increase. Combine this with the faster HAPS-80 with HAPS ProtoCompiler HSTDM capability and there is a potential for significant performance improvements. This capability is available for both HAPS-70 and HAPS-80.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in UltraScale | Comments Off

Xilinx UltraScale VU440 FPGA Production Devices Finally Available

Posted by Michael Posner on January 15th, 2016

It’s been about a year that I have been blogging on the new Xilinx UltraScale VU440 FPGA devices and Xilinx is finally shipping production devices. I say finally not because they are late, they are actually shipping exactly as communicated, but finally due to the pent up demand for systems utilizing these large prototyping capable devices is bursting at the seams. Synopsys is shipping hundreds of systems to deliver on our backlog.

While at the Synopsys Corporate offices this week I was able to visit the lab and snap off a couple of pictures of the newly built HAPS-80 production systems utilizing the production Xilinx UltraScale VU440 devices and running the production images generated by HAPS ProtoCompiler. I’m biased of course but I think this is a pretty great looking setup. What do you think?

Pictures from the lab

HAPS-80 with HAPS ProtoCompiler production systems in the lab

HAPS-80 with HAPS ProtoCompiler production systems in the lab, picture angle 2

Close up of connector covers which are removed when connector is in use and pcb cover.

And to celebrate I even created a new one slide version of the HAPS-80 with HAPS ProtoCompiler benefits… enjoy.. but I doubt you will see this version in any “official” Synopsys slide deck :)

Don't expect to see this in the official Synopsys presentation slide deck

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in UltraScale | Comments Off

The best of the best for 2015 – Physical Prototyping Blog Awards

Posted by Michael Posner on January 8th, 2016

Happy New Year and all that. What an fantastic 2015 for physical prototyping and I expect 2016 to be even better now the Xilinx UltraScale based solutions are rolling out. Of course the highlight of the work year for me was the launch of the HAPS-80 with ProtoCompiler.

HAPS-80 with ProtoCompiler Key Benefits

  • Reduces time to high-performance prototype to <2 weeks
  • Built-in debug capabilities – capture 1000’s RTL signals /FPGA
  • Delivers up to 100 MHz multi-FPGA system performance
  • Scalable, modular, large capacity – up to 1.6B ASIC
  • Fastest and incremental tool flow
  • Compatible with HAPS-70 & HAPS-DX

Below is a flashback to 2015’s Top 10 blog topics as rated by readership hits. #1, most popular.

#1 : https://blogs.synopsys.com/breakingthethreelaws/2015/02/how-many-asic-gates-does-it-take-to-fill-an-fpga/ No one seemed to get the relevance of the chicken crossing the road but that’s just how my brain works. The blog title was like a joke, “why did the chicken cross the road?”, “How many ASIC gates does it take to fill and FPGA?” do you see the connection?

#2 : https://blogs.synopsys.com/breakingthethreelaws/2015/02/part-deux-how-many-asic-gates-does-it-take-to-fill-an-fpga/ Second part of the blog post which explains how to calculate how many ASIC gates it takes to fill and FPGA. Spoiler alert… there is no golden calculation which can be used for this purpose.

#3 : https://blogs.synopsys.com/breakingthethreelaws/2015/09/introducing-haps-80-with-fully-integrated-protocompiler-shifting-the-market-to-an-integrated-prototyping-solution/ Introduction of the key benefits of HAPS-80 and ProtoCompiler

#4 : https://blogs.synopsys.com/breakingthethreelaws/2015/12/understanding-xilinx-system-logic-cells-vs-logic-cells/ The answer to why Xilinx changes the way they report FPGA capacity and the technical details behind it

#5 : https://blogs.synopsys.com/breakingthethreelaws/2015/10/xilinx-ultrascale-vu440-device-now-25-greater-capacity/ Xilinx has changed the way they report FPGA capacity, learn more about it here

#6 : https://blogs.synopsys.com/breakingthethreelaws/2015/08/performance-boost-from-xilinx-ultrascale-based-prototypes/ What to expect in respect to performance when moving to Xilinx UltraScale based prototype.

#7 : https://blogs.synopsys.com/breakingthethreelaws/2015/06/highest-performance-xilinx-ultrascale-based-prototypes/ Discusses what it takes to get the highest performance out of your Xilinx UltraScale based prototype. You need a combination of hardware, features, IP and a tool flow which considers timing all the way through the flow.

#8 : https://blogs.synopsys.com/breakingthethreelaws/2015/07/xilinx-ultrascale-vu440-based-haps-solution-shipping-hapsprotocompiler/ Covers the key benefits of the HAPS-80 with ProtoCompiler and links to blogs detailing each key feature.

#9 : https://blogs.synopsys.com/breakingthethreelaws/2015/03/automated-timing-biased-partitioning/ Discusses how to eliminate or reduce the number of multi-hop paths in a multi-FPGA partitioned design. Multi-Hop paths negatively impact overall system performance.

#10 : https://blogs.synopsys.com/breakingthethreelaws/2015/08/how-to-run-your-multi-fpga-prototype-at-ludicrous-speed/ What it takes to run your multi-FPGA prototype at the very highest of performance, no pin multiplexing.

#11 : https://blogs.synopsys.com/breakingthethreelaws/2015/05/comparison-of-prototyping-bridge-vs-hybrid-prototypes/ Discussing the differences & benefits of what the market calls a prototyping bridge (interface from host to prototype hardware) vs. Hybrid Prototyping

(Yes, I know the list goes to 11……..)

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

I did not relax over the Christmas/New Year break, check out my fitbit’s report of just one of my days.

Check out the floors climbed

Note the number of floors climbed. That’s not an error, that’s how many you get when you hike up the side of a mountain for 3 1/2 hours.

I also went from beard back to stubble. The beard did help with the cold weather face protection.

Mick Icy Beard

Mick No Beard

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Uncategorized | Comments Off

Prototyping Low Power Functions Using UPF

Posted by Michael Posner on December 19th, 2015

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

UPF (IEEE 1801-2009 ― Unified Power Format) is the industry standard for design and verification of low power integrated circuits. As noted above, these low power modes are a mix of hardware capabilities under software control and to verify the operation the two must be run together which poses a challenge for the verification and software engineers. Physical, FPGA-based prototyping would seem like the logical solution to this problem as you are running a high performance, cycle accurate model of the design against the real software. But there is a problem, FPGA’s are not ASIC’s .

FPGA’s are volatile

  • No power islands or partial turn off
  • Configuration file loaded from external memory

Multi-voltage cells are not present

  • Only user configurable cells

A single power and single ground

  • VCC, GND for user mapping

Click picture for full size render.

Low power intent view in ASIC

But will you cannot test the exact power domain capabilities of your design there are still many capabilities which can be modeled in the Physical Prototype which will result in higher test coverage of the designs low power capabilities. To make this process easy the Synopsys ProtoCompiler tool can read your UPF and implement a number of lower power capabilities as part of the HAPS physical prototype. This enables the software that controls these lower power modes to be more fully verified pre-silicon.

Some of the key low power capabilities which can be inferred directly from the UPF through the ProtoCompiler for HAPS flow are:-

Verify/validate logical of the islands and control manager

  • Isolation behavior
  • Retention behavior
  • Power Management Unit (PMU) connections and control

Click picture for full size render

Low power modes modeled through ProtoCompiler for HAPS

With this low power logic modeled in HAPS the design’s low power modes can be more extensively tested. The isolation and retention behavior is a mix of hardware functions controlled by software which can now both be tested together. ProtoCompiler’s implementation of the UPF directives modeled in the HAPS systems the designs inferred low power modes enables the hardware and software engineers to expand the low power mode verification resulting in lower rick risk of post-silicon issues.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

I’m taking a personal break over this holiday period so no blog for a couple of weeks. I would hope that no one is around or bored enough to want to read this blog over the break period anyway so no one will really notice.

I grew a beard for the winter break, (see below) not because I’m hip and trendy but because I like to ski/snowboard/mountain climb during the break and a beard protects your face from the wind. I’ll shave it off in January and then post a comparison picture. I like a beard for the technical reasons listed but I really don’t think it suits me.

Mick grew a beard

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes | Comments Off

Fastest Time to Productivity using DesignWare IP, HAPS with ProtoCompiler & Hybrid Prototyping

Posted by Michael Posner on December 12th, 2015

Hybrid IP Prototyping Kit

While traveling this week I found myself explaining the value of Hybrid Prototyping when used with DesignWare IP or your own IP blocks and RTL code. Simply put, using Hybrid Prototyping you can immerse the IP in the context of the SoC without needing to have RTL for the whole SoC. Hybrid Prototyping enables a Pre-RTL SoC representation to be rapidly created (using off the shelf Virtualizer Development kits as a starting point) and incorporating the block(s) under test modeled in HAPS Physical Prototype. This Hybrid Prototype is used for early software development in the case of the DesignWare IP and can be used in the same way for your own blocks in addition to increasing the verification of the design(s) under test.

Rather than writing an lengthy explanation I suggest you watch the Hybrid IP Prototyping Kits video which explains the key benefits of Hybrid Prototyping. Watch how the DesignWare Hybrid IP Prototyping Kits combine the benefits of virtual prototyping (Virtualizer) and FPGA-based prototyping (HAPS with ProtoCompiler) to speed development of DesignWare IP in 64-bit ARM-based designs

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

Can you guess where I was last week from this picture?

What Was Mick Last Week?

This is a picture explaining the perils of business travel

This explains my weight gain

Happy Holidays!

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Debug, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Use Modes | Comments Off

Understanding Xilinx System Logic Cells vs. Logic Cells

Posted by Michael Posner on December 6th, 2015

Xilinx Cover Slide

Recently I blogged on a change in the way Xilinx reports the capacity of their new UltraScale FPGA devices. At the end of the blog I left with the following questions

Inquisitive minds are asking the following questions:-

  • Why has Xilinx changed from Logic Cells to System Logic Cells?
  • What exactly is a System Logic Cell?
  • Do time machines actually exist?

In reverse, Xilinx does not have a time machine (sad L) and has not auto-magically built more capacity into the Xilinx UltraScale FPGA devices since they launched them. What they have done is changed their technology which requires an update to how they count the capacity of their FPGA’s.

First the challenge

Xilinx-1

These slides pretty much speak for themselves so no need for me to repeat.

Now introducing System Logic Cells

Xilinx-2

Key point here IMO is that this change is more consistent with how other vendors report their capacity so in essence there is a move towards a more standardized approach. It should be noted that each vendor still counts differently than each other but that’s because their technologies are different.

Now what is a System Logic Cell? First lets review the Virtex-7 architecture.

Xilinx-3

The picture above, click to enlarge, is of the Xilinx 7 Series CLB, consisting of two slices per CLB.

Now lets compare and contrast the older Xilinx 7 series CLB with the Xilinx UltraScale architecture.

Xilinx-4

<caution, technical content>

If we now look at the Xilinx UltraScale™ architecture CLB, a CLB and a slice are now one in the same. Xilinx have built new dedicated inputs for each flip-flop so that they no longer need to route through a look-up table to get access to the second flip-flop. This should reduce the overall LUT utilization. By eliminating the concept of the slice, this enables Xilinx to add a new wide function MUX at the output of the look-up tables. Now Xilinx can build functions that are made up of 8 LUTs and can all be cascaded together to build wider functions. This also allows Xilinx to build twice as wide distributed RAMs vs. previously. To support that Xilinx added a wider carry chain.

In addition, Xilinx doubled the number of clock enables. One of the most significant factors when it comes to getting higher CLB packing is having additional clock enables so that the tools can combine functions together in the same CLB that may have different clock-enable inputs on them. Finally, Xilinx also put clock-enable ignore, reset ignore and local reset inversion on all flip-flops. All this allows for tighter packing. In UltraScale, Xilinx can now pack flip-flops together where some of them may be using a clock-enable, some may not be. Same thing on the reset side. Some flip-flops can use a reset, otherwise if they don’t have a resent that’s okay. They can still be packed into the same CLB and Xilinx will invert the polarity of the reset locally rather than needing to route through a LUT just to simply change the polarity of the reset.

So all in all Xilinx’s data seems to back up the new capacity calculation. Of course the proof is in the pudding and especially in physical prototyping the only realistic way to gauge your capacity need is to run it through a tool flow such as Synopsys’ ProtoCompiler. This way you will have a more accurate design specific capacity representation. Of course this blog would have been far simpler if Xilinx has built a time machine…

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in UltraScale | Comments Off