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Breaking The Three Laws
 
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

LAST CHANCE TO VOTE: ARM TechCon Innovation Challenge 2015 – Vote for HAPS-80 FPGA-Based Prototyping System

Posted by Michael Posner on November 9th, 2015

LAST CHANCE TO VOTE: The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system

Vote-For-HAPS-80

Vote here : https://www.surveymonkey.com/r/8CJF6PL

This is why I think you should vote for the new HAPS-80 with ProtoCompiler FPGA-based prototyping system:

  • The new solution is a leap forward in prototyping technology far in advance of what the pure Xilinx UltraScale VU440 FPGA device itself enables. It’s an integrated solution of hardware, HAPS-80, with state of art tool flow from ProtoCompiler. Come into the light and no longer suffer the dark ages of just a board solution
  • The solution includes a tool flow which has radically reduced the time to first prototype. What used to take months now on average takes >2 weeks.
  • For the first time ever in a prototyping solution, high visibility debug is built into the HAPS-80 with ProtoCompiler solution providing almost seamless and minimally intrusive debug. Multiple debug modes are supported including a clock controlled full visibility mode, high performance capture mode, real time debug with a logic analyzer and a deep trace mode for long scenario capture.
  • Happiest users from the highest performance in single and multi-FPGA usage modes, shorter verification test runtimes, boot OS’s quicker. Unique synthesis and HAPS High Speed Time Domain multiplexing delivers the highest performance possible for IP and SoC designs
  • Desktop and global usage modes. Access a system locally on the engineers desk or remotely when it’s housed in a secure data center. Global accessibility ensures the highest utilization of the systems for the best ROI
  • Unmatched iteration turn-around. Automation ensures that re-spin builds are accelerated and incremental capabilities ensure that only changes need to be spun and incorporated.

This makes the solution perfect for all SoC designs, especially ARM-based.

So Vote here for HAPS-80 FPGA-Based Prototyping System: https://www.surveymonkey.com/r/8CJF6PL

Summary details from: http://www.edn.com/electronics-blogs/catching-waves/4440702/Vote-for-best-ARM-based-product- : A panel of EDN/EE Times editors and ARM experts selected 12 finalists, 3 in each of the following categories: Best Software Product, Best Chip Product, Best System, and Best IoT Product. These 12 finalists will be featured in the ARM Innovation Challenge Tour. Awards will also be given out for Best in Show and Reader’s Choice (that’s where you come in). The awards ceremony is scheduled to take place Wednesday, November 11 at 4:15 local time in the EXPO hall theater.

So, now it’s your turn to weigh in for the Reader’s Choice Vote. You have until 2PM Pacific Time on November 11 to record your vote.

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Posted in HAPS-80, UltraScale | Comments Off

ARM TechCon Innovation Challenge 2015 – Vote for HAPS-80 FPGA-Based Prototyping System

Posted by Michael Posner on October 30th, 2015

The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system

Vote-For-HAPS-80

Vote here : https://www.surveymonkey.com/r/8CJF6PL

This is why I think the new HAPS-80 with ProtoCompiler FPGA-based prototyping system should win:

  • The new solution is a leap forward in prototyping technology far in advance of what the pure Xilinx UltraScale VU440 FPGA device itself enables. It’s an integrated solution of hardware, HAPS-80, with state of art tool flow from ProtoCompiler. Come into the light and no longer suffer the dark ages of just a board solution
  • The solution includes a tool flow which has radically reduced the time to first prototype. What used to take months now on average takes >2 weeks.
  • For the first time ever in a prototyping solution, high visibility debug is built into the HAPS-80 with ProtoCompiler solution providing almost seamless and minimally intrusive debug. Multiple debug modes are supported including a clock controlled full visibility mode, high performance capture mode, real time debug with a logic analyzer and a deep trace mode for long scenario capture.
  • Happiest users from the highest performance in single and multi-FPGA usage modes, shorter verification test runtimes, boot OS’s quicker. Unique synthesis and HAPS High Speed Time Domain multiplexing delivers the highest performance possible for IP and SoC designs
  • Desktop and global usage modes. Access a system locally on the engineers desk or remotely when it’s housed in a secure data center. Global accessibility ensures the highest utilization of the systems for the best ROI
  • Unmatched iteration turn-around. Automation ensures that re-spin builds are accelerated and incremental capabilities ensure that only changes need to be spun and incorporated.

This makes the solution perfect for all SoC designs, especially ARM-based.

So Vote here for HAPS-80 FPGA-Based Prototyping System: https://www.surveymonkey.com/r/8CJF6PL

Summary details from: http://www.edn.com/electronics-blogs/catching-waves/4440702/Vote-for-best-ARM-based-product- : A panel of EDN/EE Times editors and ARM experts selected 12 finalists, 3 in each of the following categories: Best Software Product, Best Chip Product, Best System, and Best IoT Product. These 12 finalists will be featured in the ARM Innovation Challenge Tour. Awards will also be given out for Best in Show and Reader’s Choice (that’s where you come in). The awards ceremony is scheduled to take place Wednesday, November 11 at 4:15 local time in the EXPO hall theater.

So, now it’s your turn to weigh in for the Reader’s Choice Vote. You have until 2PM Pacific Time on November 11 to record your vote.

If you like this or other posts, sign up yourself and then send this URL to your friends and tell them to Subscribe.

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Happy Halloween

Happy Halloween

Yes, I did built a set of LED lights for our carved creations

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Posted in HAPS-80, UltraScale | 1 Comment »

Xilinx UltraScale VU440 Device Now 25% Greater Capacity?

Posted by Michael Posner on October 23rd, 2015

Trolling the Xilinx documentation I noticed something amazing while looking at the UltraScale FPGA Product Tables and Product Selection Guide, the VU440 UltraScale device seems to have grown in FPGA capacity. Previously quoted as 4.4M Logic Cells the VU440 is now 5.5M System Logic Cells. Incredible the VU440 is now 25% larger…. Or is it….

Click the picture for full size showing how the VU440 and other Xilinx UltraScale FPGA devices were listed when launched

Xilinx UltraScale Logic Cell Representation

Now click the picture for the full size showing how the VU440 and other Xilinx UltraScale FPGA devices are now listed

Xilinx UltraScale System Logic Cells representation

Anyone notice the difference?

Yes that’s right, Xilinx has moved from quoting FPGA device capacity in Logic Cells to System Logic Cells !!!! So unless Xilinx has some super cool back to the future time machine technology and have traveled back in time and inserted more logic, the device is the same capacity.

This highlights the conclusion from my last two blogs on this subject “How many ASIC Gates does it take to fill an FPGA?” and the finale post “Part Deux: How many ASIC Gates does it take to fill an FPGA?” THERE IS NO ACCURATE WAY TO CALCULATE ASIC GATES FROM FPGA GATES. The only true way of more accurately estimating the number of FPGA’s your SoC prototype will need is by executing FPGA area estimation within a prototyping tool such as ProtoCompiler.

Inquisitive minds are asking the following questions

  • Why has Xilinx changed from Logic Cells to System Logic Cells?
  • What exactly is a System Logic Cell?
  • Do time machines actually exist?

I’m interviewing a Xilinx representative next week, I’ll post what I find out.

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I have chickens and sadly there are many Norwegian rats in our area. The rats love chicken food and if you leave the food out overnight you will be amazed at how much food the rats eat. So a couple of years back I rummaged through my garage and came up with a solution from stuff just laying around. It included a 3000 Lbs winch which is remote controller and a solar charged battery pack.

Chicken food winch version 1

The food is pulled up into the metal bucket protecting it from the rats. However this solution seemed overkill for even me. I will say that it has worked very well other than having to pop outside to use the winch remote. What I wanted was a fully automated day/night solution so I designed and built the below prototype

Chicken food rat protection version 2

This has a day/night sensor which activates the mini winch (my design) that lifts the food cover. Sadly during testing the winch motor controller failed and drained the battery. In addition the day/night sensor had no adjustment and I noticed that on a cloudy day the food got covered.  I had built a magnetic reed switch setup to turn on and off the motor at the right points, this proved unreliable. But without failure there would be no innovation so I created version 3

Chicken food rat protection version 3

This version has a more reliable day/night sensor setup which is adjustable and has been proven to only protect the food at night. The system uses a linear actuator to lift the food into the metal bucket to protect it. However on day 5 tragedy, the food failed to lower out of the bucket and we had hungry chickens until we noticed. Basically I had undersized the battery and solar panel setup and run the battery dead.  Easy solution, larger battery and solar panel but even with this update I was not happy with the operation. The winch setup has issues and the food is not easy to detach for filling.

So now I am working on version 4. The picture below is a prototype of the core of the new build. This setup will use a scissor jack setup to raise and lower the food in and out of the metal bucket.

Chicken food rat protection version 4, scissor jack

I know what you are thinking “you have too much time on your hands”. I don’t, I just don’t sleep…

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Addressing the Dark Fibre of FPGA-Based Prototyping, Lighting the Dark FPGA’s

Posted by Michael Posner on October 16th, 2015

The term “Dark Fibre (Fiber) refers to the additional lines/capacity of optical connections a carrier would install when they laid a new pipeline. These unlit optical connections were built in assuming the need for additional capacity in the future. The thinking was that it’s cheaper to do it all at once vs. adding lines/pipelines later. The problem is that this extra capacity is going to waste and while the main carrier was not using it, someone else could have.

(There is no difference in meaning between the word fiber and fibre. Fiber is the preferred spelling in American English, and fibre is preferred in all the other main varieties of English and as I am originally from the UK I’m ignoring spell check and using the fibre spelling)

We are seeing more and more users move their FPGA-based prototype hardware off their desks and into a shared resource location. HAPS with ProtoCompiler fully supports this emerging use model. The flexible Synopsys solution can be tailored (highest performance) to individual prototyping projects needs or configured in a more generic fashion for greater flexibility when there are many different teams accessing the system.

HAPS-80 with ProtoCompiler supports IP, Block, Subsystem and SoC level prototyping

Typically customers are building these installations using a standard form factor building block, the HAPS-70 S48 or the HAPS-80 S104. Thanks to the HAPS with ProtoCompiler modularity and scalability it’s easy to chain these to support SoC designs of not up to 1.6 Billion ASIC gates.

The HAPS-80 S104, 104 Million ASIC Gate, 4-FPGA form factor, modular and scalable prototyping system

The problem is that prototyped designs don’t always use up all of the FPGA’s available and you end up with Dark FPGA’s. Dark FPGA’s is capacity that is going to waste within the large array of resources, just like Dark Fibre. But let there be LIGHT,  enter HAPS with ProtoCompiler Multi-Design Mode

HAPS-80 with ProtoCompiler Multi-Design Mode

HAPS with ProtoCompiler Multi-Design Mode allows you to use up this extra capacity by sharing the HAPS Prototyping resources across multiple users and multiple designs. In the example below there are three users exercising four design utilizing a total of seven FPGA’s. The designs range from smaller IP or block level prototypes to larger subsystem or SoC level prototypes. No Dark FPGA’s. ProtoCompiler for HAPS manages most of the complexity to create these portable prototyping images in addition to the user following a documented methodology and best practices.

HAPS-80 with ProtoCompiler Multi-Design Mode Example. No Dark FPGA's

The HAPS systems were designed for desktop usage as well as rack mount as seen in the setup below.

HAPS-80's installed into a server rack. Hey, nice rack!

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Posted in FPGA-Based Prototyping, HAPS-80, Man Hours Savings, Milestones, Project management, Tips and Traps, UltraScale, Use Modes | Comments Off

Performance, Performance, Performance, HAPS with ProtoCompiler Goes to 11

Posted by Michael Posner on October 10th, 2015

Ultimately when you hand-off your physical FPGA-based prototype to the end users there are only two things that they care about; Performance, Performance, Performance. I know I said there were only two things but performance is so important I listed it three times.

With the availability of HAPS-80 with ProtoCompiler, reaching your performance targets just got a lot easier.

This week I interviewed a number of the Synopsys R&D team to get the real users view of estimated performance from the new solution.

Starting with Single-FPGA performance

HAPS-80 S26 Single FPGA with ProtoCompiler

The simplest type of FPGA-based prototyping, the HAPS-80 S26 (26 Million ASIC Gates) system is expected to deliver up to ~300 MHz. With the Xilinx UltraScale VU440 device and a design which is highly FPGA friendly you might be able to close timing at a higher rate but in reality ASIC RTL is not FPGA optimized resulting in lower total performance. The PCB trace paths from FPGA to the HT3 connectors are all  optimized and delay matched for not only the highest performance operation but also consistent timing regardless of the HT3 connector targeted. As ProtoCompiler is HAPS-80 aware, with built-in deep technical specifications including IO pin outs, timing delays, unique capabilities, it’s a pretty simple task to prepare a design for HAPS-80 S26 platforms.

Of course single-FPGA prototyping is very limiting, typically only used for IP and very small SoC’s, so multiple FPGA’s are needed.

HAPS-80 with ProtoCompiler Multi-FPGA with 1:1 IO, no pin multiplexing

In a multi-FPGA prototype the bottleneck of performance is typically the IO between the FPGA’s. The HAPS-80 has the most FPGA IO user available and the highest flexibility of interconnect options. In some cases this is enough IO to negate the need for any pin multiplexing across the links. When no pin multiplexing is used the interconnect can be run at the global synchronous rate, which in the case of HAPS-80 is ~100 MHz. The best part about this is that ProtoCompiler’s default goal is to create a partition with no pin-multiplexing needed making it easy to meet this performance. ProtoCompiler can automatically look for this type of solution or can be guided by the user manually if the user already has a good idea of the optimum partition cut point. WOW, HAPS-80 with ProtoCompiler Goes to 11 (I’m pretty sure I used this joke before Elon Musk)

Finally if partitioning is needed then pin multiplexing needs to be used.

HAPS-80 with ProtoCompiler Multi-FPGA performance with pin multiplexing

This is HAPS-80 with ProtoCompiler’s clear strength thanks to the unique HAPS High Speed Time Domain Multiplexing capability which users rely on. With the HAPS-80 we have introduced a new version of the High Speed Time Domain Multiplexing, optimized for the Xilinx UltraScale devices which is proving to be between 20-50% higher performance than our traditional method. This is not because of the Xilinx UltraScale device, if anything the additional latency within the Xilinx IO’s the raw device IO performance is no better than the Xilinx Virtex-7 IO performance. We built in new capabilities into the HAPS-80 hardware and ProtoCompiler inserts logic optimized to this. The result is higher performance when this new pin multiplexing capability is used.

The HAPS High Speed Time Domain multiplexing scales across multiple systems and with ProtoCompiler’s knowledge of the HAPS it manages the clock and reset distribution with minimal to no impact to the users design. HAPS-80 supports up to sixteen systems in a single chain, 1.6 Billion ASIC gates.

A third pin multiplexing scheme has been developed which is targeted at transfer of lower performance signals or groups with more slack. This off-load signal capability free’s up IO’s which can be applied to the high performance signal needs resulting in lower pin multiplexing ratios and thus higher performance, in some cases as much as 2X higher performance

HAPS-80 with ProtoCompiler signal off-load bus performance

The combination of these integrated HAPS-80 and ProtoCompiler capabilities ensures that resulting prototypes are the fastest possible.

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After last week’s blog, where pasted a picture of the Halloween costume I’ve been making, I was  asked multiple times what being made of spray foam actually means. Basically I took a bike helmet and a back pack and covered them in building material expanding foam. Building foam is very sticky and depending on which type you buy either expands a little or a lot. I use a mixture of both to get the effects I want. Below is the in progress pictures of the helmet and back pack.

Bike Helmet covered in builders spray foam

Back pack covered in builders spray foam

I have installed LED lighting on both so that in the night it’s easy to see while track or treating and of course add’s to the models effect.

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Posted in HAPS-80, Performance Optimization, UltraScale | Comments Off

How to achieve a simulator like debugging experience with FPGA-based prototyping

Posted by Michael Posner on October 5th, 2015

Verdi GUI, the best debugger ever

This week we will discuss the simulator like debugging experience that users of the new HAPS-80 with ProtoCompiler solution get. The new solution includes built-in debug which means that the ProtoCompiler flow incorporates debug and the HAPS-80 hardware has debug capabilities physically built in. The ProtoCompiler flow ensures that the inclusion of debug it mostly seamless to the user and the HAPS-80 built in debug hardware ensures that the advanced capabilities are available without the need to purchase additional hardware.

Customers sadly still tell me that they are using FPGA vendor tools for debug. While these come for free with the vendor tools they are very limited and intrusive to the design being prototyped. Typically you are debugging an FPGA netlist, not the source RTL. The debug is restricted to one FPGA, not multi-FPGA as most prototypes are. They utilize FPGA memory resources for debug data storage which is intrusive to the prototyped design and limits the amount of data that can be stored. Another issue is that these tools only offer one style of debug capabilities, internal signal trace.

There is a better way to debug and this is what is offered with the HAPS-80 and ProtoCompiler Solution. First of all debug is built into the flow from the ground up and is mostly non-intrusive to the user. This addresses the issue that we see all the time, pictured below, where adding debug into the flow breaks a working prototype.

Challenges of Multi-FPGA debug

As debug is built-in from the ground up and automated through-out the flow it’s mostly seamless to the user and non-invasive to the resulting prototype.

HAPS-80 and ProtoCompiler built-in debug solution

Dedicated built in resources on the HAPS-80 hardware manage the synchronization of debug data across multiple FPGA’s and the physical storage of debug data which does not utilize FPGA embedded memory. Debug is done at the source RTL, simulator like with breakpoints, triggers and values over-laid on the original source, regardless of where the RTL ends up in a multi-FPGA prototype. Debug can be dynamic, real-time with the prototype or waveform databases can be captured, VCD and FSDB (Verdi) for post process and debug. Users can rely on the capability as this is the fourth generation of the HAPS Deep trace debug which was first launched along with the HAPS-60 systems.

The HAPS-80 and ProtoCompiler debug solution offers even more debug capabilities in addition to the built in HAPS Deep Trace Debug. The HAPS snapshot style debug enable the prototype clock(s) to be stopped and the contents of almost 100% of the signals and registers to be read-out of the system. HAPS Real Time Debug, seamlessly and mostly invisible to the end user, routes user designated signals out to a Logic Analyzer connection enabling almost limitless capture of the selected signals. Native integration with Verdi and Siloti enables seamless analysis and waveform compare in addition to the use of the signal compression and essential signal database for instrumentation.

So you can see that the new debug capabilities of HAPS-80 with ProtoCompiler deliver the closest to a simulator like experience than ever before.

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Following up from last week you can find a couple of videos from the Science and Technology museum in Shanghai here: https://www.youtube.com/user/MrMickPosner

I’m preparing for Halloween and built the below dinosaur backpack and helmet using spray foam. Yes, I can build almost anything in spray foam. The costume is also illuminated with LED’s for better visibility at night

Dino backpack and helmet made of Spray foam with LED's

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Posted in Bug Hunting, Debug, HAPS-80, UltraScale | 1 Comment »

Overcoming the three phases of prototype bring-up

Posted by Michael Posner on September 25th, 2015

The three phases of prototype bring up

Over the next couple of weeks I’ll blog with more details on the key capabilities of the newly available HAPS-80 with ProtoCompiler integrated solution.

  • ProtoCompiler, exclusive for HAPS systems, automates design flow and partitioning to reduce time to first prototype on average to less than two weeks and subsequent iterations to hours
  • Built-in debug capabilities are automatically inserted for greater debugging efficiency and visibility, enabling the capture of thousands of RTL signals per/FPGA
  • HAPS-80 FPGA-based prototyping system with ProtoCompiler delivers up to 100 MHz multi-FPGA performance and new automated high-speed pin-multiplexing
  • HAPS-80 enterprise configurations support up to 1.6 billion ASIC gates based on the Xilinx Virtex UltraScale VU440 FPGA and enable remote usage and multi-design mode for concurrent design execution

Today’s focus is on the design flow and time to first prototype operation being reduced to on average less than two weeks. Based on the FPGA-based Prototype Methodology Manual survey results this is still seen as the number #1 challenge to prototypers.

Challenges of FPGA-based prototyping users

Addressing time to first prototype means addressing the three phases of prototyping, making the design FPGA friendly, bring-up and debug and finally performance optimization. The first phase, make the design FPGA friendly, is all about automation. One of the three laws of prototyping is that ASIC code is FPGA hostile, there is no way around that so the more that can be done to automate the process the more seamless the flow becomes.

Phase 1, Make design FPGA ready

This is exactly what ProtoCompiler for HAPS delivers, automation throughout the flow to hardware. Automation including gated clocks conversion, clock replication, memory translation, partitioning and pin multiplexing insertion all the way through to guided place and route. The complete flow can be scripted for repeatability. This is the key capability in reducing the time to first prototype to on average less than two weeks. At this point you have FPGA bit files ready to test on the HAPS systems

The second phase if the bring-up and debug of the platform.

Phase 2, HW bring up and debug

In a perfect world the prototype would function out of the box, which is the case some of the time, but unfortunately not all of the time. In this phase the prototype engineer wants to check the system is configured correctly and rapidly debug. HAPS-80 with ProtoCompiler enables both. The HAPS built-in system check capability ensures that interconnect and daughter boards are correctly installed, match the design description and meet the required performance. Debug can be rapidly inserted not requiring a re-compile speeding up the design bring-up debug process. We highly recommend an incremental bring-up strategy of individual blocks then subsystem and finally SoC. ProtoCompiler supports an IP to SoC flow enabling this bring up strategy as lower level blocks can be integrated into the larger context of the design with reuse of the constraints developed at the block level.

At this point the HAPS-based prototype can be handed off to the target teams for continued bring up testing and early software development. The 3rd phase, performance optimization is also typically a fast iteration but the more focus this stage is given the better the results can be.

Phase 3, Performance Optimization

ProtoCompiler is designed to get to a result as fast as possible with out of the box high performance. If you have a little extra time to spare this performance can be optimized. In ProtoCompiler this is simply a change of configuration from TTFP (Time to First Prototype) mode to performance optimized mode. In the optimization and tuning mode the compilation optimization is enabled, synthesis target is highest performance, different partition goals and so on. While the turn-around time from RTL to bit file is increased the typical result is the highest performance.

So as you can see, HAPS-80 with ProtoCompiler successfully addresses the time to first prototype achieving on average less than two weeks to operation. Next week, built-in debug

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Last week I spent the weekend in Shanghai. To pass some of the time I visited the Shanghai Science and Technology Museum I really enjoyed it.

What an amazing looking museum.

Shanghai Science and Technology Museum

While I visited all exhibit halls I enjoyed the world of robots the most

World of Robots at the Shanghai Science and Technology Museum

This hall had some great exhibits with dancing robots, archery against a robot and much more. I really liked the little robot pictured below who put on a hip hop dance show and then more classic Chinese dancing.

The little robot that could

There was even a robot who would solve a rubix cube. You mess it up, it solved it in typically less than 1 minute.

Rubix Cude Solving robot

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, Man Hours Savings, Performance Optimization, UltraScale | Comments Off

Introducing HAPS-80 with Fully Integrated ProtoCompiler – Shifting the Market to an Integrated Prototyping Solution

Posted by Michael Posner on September 17th, 2015

Mick Introduces HAPS-80 with integrated ProtoCompiler to the world at SNUG Taiwan

Drum roll please…… Introducing the latest generation FPGA-based prototype, the HAPS-80 with ProtoCompiler solution is now available. Above I’m pictured introducing the new fully integrated solution to a packed room at SNUG in Taiwan. Below I’m staged in front of the physical side of the new solution, the HAPS-80 hardware itself. The unit on the right, the unit on the left sort of behind me is the previous generation the HAPS-70.

The HAPS-80 demo station at SNUG Taiwan. Who is that good looking guy

I recommend the introduction to the HAPS-80 solution video as it provides you the quickest summary of the new solution and capabilities. I also highly recommend you watch the video “Prototype Timing Closure with Synopsys HAPS-80” as it described the new timing driven performance capabilities specifically.

The goal of the new solution is to address the main challenges faced by prototypers as per the FPGA-based Prototyping Methodology Manual survey results and our knowledge of the needs of our customers. The key is that individually solving one or two of these challenges does not help the users, you need to solve them all to enable successful prototyping. With the introduction of the HAPS-80 with ProtoCompiler we have solved all these challenges…. And more to future proof the solution.

Challenges of FPGA-based prototyping users

The problem is that a majority of prototyping is still done in an ad-hoc style utilizing disjointed point tools and hardware, we call this the “it’s just an FPGA” mentality. The key is that you are no longer prototyping small blocks you are prototyping sub-systems and full SoC’s which even if they still fit into a single FPGA (26 Million ASIC gates now per-FPGA with the HAPS-80) require ASIC like tools to manage the complexity. Physical prototype just grew up.

Disjointed prototyping is so 1980's. You need an integrated solution

The HAPS-80 with integrated ProtoCompiler tool addresses all these challenges and delivers additional benefits setting the new standard for FPGA-based prototyping. Users no longer have to cobble together 3rd party tools with FPGA boards and struggle with debug and support. The complete solution comes from Synopsys so users don’t have to turn to multiple vendors. The benefit to the end users of a fully integrated solution is huge. Stability and reliability, expert support, advanced capabilities designed into the hardware and automatically inserted by the tool flow seamlessly, highest performance out of the box, incredible debug visibility which is higher than ever before. Oh and there is more but this blog is getting long enough already.

HAPS-80 with ProtoCompiler Benefit Summary

In the coming weeks I’ll blog on each of the key highlights of the new solution and explain the capabilities in some technical depth.

  • ProtoCompiler, exclusive for HAPS systems, automates design flow and partitioning to reduce time to first prototype on average to less than two weeks and subsequent iterations to hours
  • Built-in debug capabilities are automatically inserted for greater debugging efficiency and visibility, enabling the capture of thousands of RTL signals per/FPGA
  • HAPS-80 FPGA-based prototyping system with ProtoCompiler delivers up to 100 MHz multi-FPGA performance and new automated high-speed pin-multiplexing
  • HAPS-80 enterprise configurations support up to 1.6 billion ASIC gates based on the Xilinx Virtex UltraScale VU440 FPGA and enable remote usage and multi-design mode for concurrent design execution

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Posted in HAPS-80, UltraScale | Comments Off

Preventing Electrostatic Discharge

Posted by Michael Posner on September 11th, 2015

Lab sign posted in Synopsys. Notice the additional sign banning marketing from the hardware lab

Recently I witnessed a user of our HAPS-70 systems touch the system without taking any Electrostatic Discharge, ESD, precautions. While the units are prototypes and it’s expected that they are customized with both off the shelf and custom daughter boards and of course design specific FPGA bit files, you cannot forget ESD precautions. The HAPS-70 systems utilize the Xilinx Virtex-7 2000T FPGA’s which are fabricated in a 28nm process. The smaller the geometry the more susceptible they are to ESD. You must never, never, never handle FPGA-based prototyping hardware without taking ESD precautions.

The following table illustrates the typical magnitude of the voltage developed in some common situations

ESD build up

Here are Ten points for helping eliminate ESD damage to prototyping hardware

  1. Make sure you have a reliable ground point available near the work site
  2. Connect your body to the ground point with a wrist strap.
  3. Ground all equipment you are working on with ground straps
  4. Handle components only on a grounded anti-static work surface.
  5. Do not wear clothing which generates static electric charges every time you move.
  6. Do not handle static generating objects while working on hardware.
  7. Store all chips and other components in appropriate anti-static containers.
  8. Keep all daughter cards in anti-static envelopes until required.
  9. Be sure to turn off the power and remove the power plug from all equipment before working on it.
  10. Do not plug in or remove devices/daughter boards while the power is on.

This is not a complete list but covers the basic handling recommendations to reduce ESD damage.

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I attended a Synopsys event this week and as a little fun we were able to get a caricature done.

Mick is Evil?

I think they captured me very well.

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Customer experiences with ProtoCompiler for HAPS

Posted by Michael Posner on September 4th, 2015

Censorship is ............

Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.

So just in case you missed the data the first time around, here it is again, this time just the data points. These two examples are from existing HAPS and Certify users and I define both customers as experienced in FPGA-based prototyping. Results of ProtoCompiler run on their designs.

I can't tell you who this customer was

This first case you can see that ProtoCompiler identified a partition solution in an automated fashion which resulted in a more optimized prototype. In this case shrinking the design from three FPGA’s to two. It’s typically understood that as you consolidate a design into less FPGA’s you can achieve higher performance. The customer will realize the effect of this performance with a reduction in test runtime.

Now the second case below is an example of how ProtoCompiler can be used again to identify more optimum prototype. In this case the solution was not to shrink the design into less FPGA’s but to partition the design at other points in the design spreading it out to four FPGA’s vs. the original three FPGA version. ProtoCompiler was able to utilize HSTDM, high speed pin-multiplexing to improve the overall system performance. A byproduct of the new partition was that compile, synthesis and Xilinx place and route times were halved.

Different customer but I still can't tell you who this is either

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I’ve been dropping “easter eggs” all through my blogs for the last couple of months. If you noticed them drop me a note or comment below on where you found the easter egg. If you don’t know what the term easter egg is then look here: https://en.wikipedia.org/wiki/Easter_egg_(media)

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Posted in ASIC Verification, Early Software Development, In-System Software Validation, Man Hours Savings, Performance Optimization, Project management | Comments Off