HOME    COMMUNITY    BLOGS & FORUMS    Breaking The Three Laws
Breaking The Three Laws
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

PCIe trends and how to accelerate Gen3 prototyping

Posted by Michael Posner on August 1st, 2014

Market trends for PCIe between 2013 and 2014

We are seeing PCIe Gen3 being integrated into many different types of SoC’s. The above summarizes the changes we are seeing in the market across 2013 and 2014. One notable area is that PCIe is moving into enterprise storage with PCIe being used for the interface to NAND flash storage devices. The below picture shows the key needs in the segments. PCIe Gen 3 is a great fit for storage as it offers 8Gb/s transport rate across a single lane with x2, x4, x8, x16 lane configurations resulting in huge bandwidth potential. My thanks to Scott Knowlton, of the Express Yourself Blog for the PCIe market data and segment analysis

PCie market segmentation and the main requirements of each

In June 2014 Synopsys ran an internal “FPGA Fest” this is an event where the Synopsys prototyping engineering teams invites all our field application consultant specialists into town for an intensive week of technical training. I attended the training as well and snapped off a couple of pictures of the PCIe Gen3 x4 lane example design training. The design is the DesignWare PCIe Gen3 controller core configured as an end point with x4 lanes. It includes an embedded DMA and software application that enables data to be read/written from and to the prototype. The DesignWare controller IP core is implemented on the HAPS-DX system and interfaces to the PCIe Gen3 capable host via the Xilinx high speed IO’s (Rocket IO transceivers). Don’t forget, I blogged about PCIe Gen3 on HAPS-70 in the past.

Top view of the HAPS-DX plugged into the host

HAPS-DX plugged into PCIe Gen3 capable host

Side view of the HAPS-DX. Here you can clearly see the HAPS-DX kit’s included PCIe Gen3 x8 capable paddle board. This is a daughter board which enables a direct passive connection from the HAPS-DX to the host’s PCIe slot. The paddle board is a highly cost effective way to create the physical link from the HAPS-DX to the host. We offer cabled versions as well which provide greater flexibility in the HAPS-DX placement but at additional cost of course. The SI characteristics of the HAPS PCIe Gen3 paddle board are fantastic (not a technical term I know…) ensuring a stable and robust connection.

View of HAPS-DX PCIe gen3 x8 capable paddle board connected to PCie Gen3 capable host PC

Finally the proof is in the pudding. Here is a picture of the reported bandwidth of the PCIe Gen3 x4 lane connection. WOW, ~700MB/s that’s fast.

Synopsys software application showing results of DesignWare PCIe Gen3 x4 end point running on HAPS-DX. ~700 MB/s fast

Do you want a PCIe Gen3 setup like this? If yes, contact me as we are preparing to release the IP Prototyping Kit for it.

Off subject…. A while back I built a small bird house with my son and he requested we put a label on it saying “Welcome Birds” so the birds would know it was for them. Well as it turns out the sign worked and we have had little birds going in and out all summer. My son said to me last weekend, “Daddy we need to build another bird box for all the other birds” I’ve been busy so to divert his attention I said that if he designed it I would help him build it. 5 minutes later he returns with a piece of paper with the design. He had designed a bird house high rise, yes, a multi-story bird house. Well I promised that if he designed it, we would build it and so here is the result.

High rise or multi-story bird house that Mick Posner built with this son

I should note that his design had way more floors but I negotiated him down to just three. We all love how it turned out. My son helped with the cutting on my radial arm saw, nailing with my framing nail gun, drilling the holes and screwing in the bolts. My father exposed me to tools when I was young, I am trying to do the same in a safe and controlled manor. All the timber used was from the scrap left over from tearing out one of our old fences.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Daughter Boards, DWC IP Prototyping Kits, IP Validation, Mick's Projects, Real Time Prototyping | 1 Comment »

HOW TO: Achieve Fastest Time to Operational Prototype and Highest Performance

Posted by Michael Posner on July 24th, 2014

Road runner the bird, not the cartoon

If you didn’t know the above picture is of the greater roadrunner (Geococcyx californianus). Trust me I didn’t just make up the Latin name. The Latin name means “Californian earth-cuckoo”. This blog is about how to achieve the fastest time to operational prototype, accelerating ASIC and SoC verification, speeding validation and the road runner was first image that popped into my mind when I wanted to articulate fast. There has been a lot of talk about Time To First Prototype, TTFP, recently so I thought I would blog a how to on achieving accelerated TTFP. I thought I’d raise the bar and deliver a how to on both achieving this AND get the highest operational performance out of the FPGA-based prototype.

If you have found yourself reading this blog you are looking for the magic solution but I am afraid I have to burst your bubble, there is no black magic solving this problem.

Home made no back magic logo

It’s better, all you need is a fully integrated FPGA-based prototyping solution. Yep, that simple, blog done, thank you :) (What? You want to know why an integrated solution solves all your problems!) To answer this we need to quickly review the challenges to FPGA-based prototyping. The below picture describes the challenges to prototyping, based on a recent survey that Synopsys ran. It also includes on the left the solutions to these individual challenges.

Click on the images to view the whole picture. I made them large so they were easy to read.

Survey results defining the challenges of FPGA-based Prototyping and the combined HW/SW capabilities needed to solve them

Do you spot the common theme? The challenges cannot be solved with hardware or software alone, it’s the combination that solves the problem. An example is performance, I’ve blogged about this is the past that it’s the combination of hardware interconnect flexibility and the ability to deploy a high speed time domain, differential signaling, solution that is the key to achieving the highest performance. In this case the software has to have intimate knowledge of the hardware, it’s electrical and SI characteristics to be able to correctly implement the high speed time domain IP in the multi-FPGA prototype design. At the same time ALL hardware must meet a minimum level of performance across all interconnections to ensure that when the prototype design image is deployed across many systems it always runs reliably.

Summary examples of what integrated capabilities are of the Synopsys solution

Debug is another good example. To deliver the highest debug visibility you need both a software flow that enables instrumentation of the RTL, graphical display AND hardware capabilities to store the physical data. The result of integration reduces your need for expertise as the solution has the expertise. Same for partitioning across multiple FPGA’s, as the software is hardware aware and the hardware can be tailored to the software recommended best interconnect topology the result is optimal.

Lucky for you, Synopsys delivers a fully integrated solution of ProtoCompiler plus HAPS so you don’t have to wait. And… if you call now, not in 5 minutes but now, I’ll personally visit your site to say hello.

Synopsys' integrated FPGA-based prototyping solution including ProtoCompiler software, HAPS FPGA-based hardware, debug, DesignWare IP, Support, HAPS Connect Program

While ProtoCompiler was only recently launched its delivering some fantastic customer results, see below, accelerating time to first prototype and delivering the highest performance. This was a customer design, 48 Million ASIC gates, four Xilinx Virtex-7 FPGAs. ProtoCompiler is fully integrated with HAPS leveraging its strengths. HAPS interconnect can be tailored based on the ProtoCompiler recommendations and ProtoCompiler understands the HAPS architecture and resources such as clocks and resets. ProtoCompiler is built around a stable code base of Synopsys’ mature and unique compilation and synthesis engines delivering the highest QoR for out-of-the-box results.

Synopsys achieves fastest time to prototype and highest performance operation with ProtoCompiler plus HAPS

A fully integrated solution delivers not only accelerated time to first prototype and highest performance but also reduces your effort as it’s doing the hard work for you. Just don’t tell your boss otherwise he will give you more work.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in ASIC Verification, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation | 2 Comments »

Going vertical for all the right reasons

Posted by Michael Posner on July 17th, 2014

harrier

By far my favorite aircraft growing up was the Harrier jump jet. Back in those days it was the only jet aircraft with vertical takeoff and landing (VTOL) capabilities. I dreamed of flying one and even owning my one. Actually I still dream of owning one. I like the idea of a helicopter as you can vertically takeoff and land meaning you have a wide range of landing zones. The problem with a helicopter is that it’s very slow in comparison to a plane so it would take you ages to get any real distance. Hence the Harrier was a perfect option for me, vertical takeoff and landing and jet speed in the air, it’s the best of both worlds.

In the land of FPGA-based prototyping there is a lot of horizontal and not much vertical, especially when it comes to daughter boards. Traditional daughter boards are flat or horizontally mounted to the system such as the HAPS DDR3 daughter board pictured below.  

HAPS-DDR3

There is nothing wrong with a daughter board like this, in fact the above daughter board has exceptional SI characteristics and operates at very high performance. However we found that some customers ran into challenges when it came to building custom daughter boards specifically tailored to their needs. Here is a summary of some of the issues they ran into.

  • Customers daughter board was quite big but it only required a couple of IO’s interfacing to the system.  Often the daughter board covered up more connectors or blocked airflow and fans just because the daughter board PCB had to be large to accommodate the custom logic
  • The daughter board required a big connector, but again only required a couple of IO’s. The size of the connector forced the size of the daughter board PCB to again cover things.
  • Once in a while the customer actually wanted to get access to both sides of the daughter board. Sometimes this was to connect to both sides, other times to probe. They would build a long daughter board expanding out of the system to do this. It was typically mechanically unsound.

Enter the Synopsys R&D Boffins! They could have ignored this little gripe with daughter boards, lets face it, the issue is annoying but not the end of the world. But that’s not good enough for the Synopsys! So drum roll please……. for the worldwide announcement of the availability of the VERTICAL HAPS daughter board. Yes, vertical….

Vert-DB

The new vertical daughter board addresses the issues laid out above.

  • For daughter boards that use relatively few IOs, say up to 50 (HT3 connector IO count) but require more PCB real estate than a typical LAB board, building in a vertical way is excellent. Look at the picture, the board form factor is huge yet it only plugs into and utilizes one HT3 connector. It does not block any other connectors or airflow.
  • Same for the problem of the big connector, a vertical board enables a HUGE connector to be used if wanted.
  • Oh my, you can even access both sides of the daughter board, perfect for additional PCB access and probing.

Vert-DB-1

The HAPS HT3 spec is being updated to define the new HT3 vertical daughter board and will be available to all existing HAPS-70 customers. Synopsys validated the form factor and usage and now shares it with any HAPS-70 customer that wants it.

So now we can all go vertical. Ease of use, functionally with performance, it’s like the Harrier jump jet of FPGA-based prototyping daughter boards. Someone once made fun of the upper frame on the HAPS-70 systems, now who’s laughing……

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Daughter Boards, Project management | 1 Comment »

Off the Cuff Video from DAC meets Zombie apocalypse

Posted by Michael Posner on July 10th, 2014

Fail

One of my worst nightmares is to completely fail at something, actually one of my worst nightmares is a Zombie apocalypse where I am one of the zombies but that’s a story for another day. At DAC I was interviewed by EDACafe, one of those 3-5 minute casual interview videos that are done in one take. They call them casual but I can tell you they are nowhere near casual, I am personally super nervous in these. I am happier with well scripted and edited videos but I also understand that the off-the-cuff videos are well received by the viewer.

Anyway, here is the video from DAC 2014.

http://www10.edacafe.com/video/Synopsys-Mick-Posner-Director-Product-Marketing/43928/media.html

Remember the video is completely unscripted and shot in one take. I’m not a fan of seeing myself on video but I must admit that suit and tie combo rock. You can also hardly tell that I’m recovering from pneumonia.

EDACafe

Talking of off-the-cuff videos at DAC, here is another one (link below), this time featuring Asheesh Khare from Synopsys, explaining the new DesignWare IP Prototyping kits. All I can say is WOW!! Not only does Asheesh explain the solution very clearly he does it at the same time as connecting up the hardware and powering it up. Now that’s a professional at work. In future I will be renting Asheesh as my body double and have him star in all my videos.

http://www.youtube.com/watch?v=JeutLeSnLIs

And finally one last video from a USA 4th of July party….. https://www.youtube.com/watch?v=dDKQt4SY5Qs Nothing like celebrating the USA independence from England with beer and a big canon. Enjoy.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in DWC IP Prototyping Kits, Early Software Development, Humor, IP Validation, Man Hours Savings, Use Modes | Comments Off

You don’t buy a dog and bark yourself

Posted by Michael Posner on July 2nd, 2014

woof

I have a set of witty one liners which I use to respond to a variety of situations that I encounter in my everyday life. Some are insightful and designed to share my wisdom while others are just supposed to be a little humorous. The title of this blog is one and I have listed a set of my favorite quotes below including the typical situations which I use them. Feel free to use these in your everyday situations as I am sure they will be as impactful for you as they are for me. I might not have been the first person to come up with these quotes so don’t get upset if you use the same ones already.

“Don’t let the technical details get in the way of a good story”
As I’m in Marketing I use this one frequently. Many times I see presentation material getting bogged down in the nitty gritty technical feature review and missing the VALUE and BENEFIT that the solution brings to the customer. This is when I use this quote to remind the team to start with the end, what is the benefit to the customer and then construct a story to deliver this message.

story

“Hope is not a strategy”
Oh by far this is my most used quote. I never rely on hope, I make things happen by planning out an execution path to reach the end goal. All too often I hear things like “I hope we can get this working” or “I hope we can repeat this success”. Hope is not going to help, you need to help yourself and create a plan then execute on it. People who rely on hope rarely succeed. Actually, there is a whole book on this topic.

hope

“I see a lot of hope and not a lot of action”
I typically use this quote hand in hand to the one above. I use this to describe a plan which has a lot of holes or gaps between actions or if I see no progress towards a goal. It’s great to have a goal with a plan to reach it but if you are not putting in the effort to action the plan you are back to hope and as we now know, hope is not a strategy.

“A vision without a plan is just a wish”
Notice there is a bit of a theme going on here. It’s great to have a vision but if you don’t have an execution plan to work towards you are just wishing for it to happen. Life is not a movie, wishes are not real so if you want to deliver on a vision you need to plan and execute.

plan

“Givers need to set limits as takers rarely do”
I’m a giver, this does not mean I’m a sheep and follow the herd it means that I set a very high bar for myself and always want to over achieve and impress. This of course can lead to personal issues when it’s taken for granted that you will always get the job done no matter of the situation. It’s fine for a giver to push back and set limits. Quote by Henry Ford, American industrialist a man I admire greatly.

ford

“You’re quick or you’re dead in this game”
I use this one to respond to a variety of situations. Sometimes I use this when I rush to get to the front of the line at the airport when a flight in cancelled. Ok, so a situation like this is not life or death but if you are going to secure a seat on the next flight you have to act fast. I’ll also use this when I am the first to get a second serving to food, similar to survival of the fittest.

quick

“Do not judge by the problem, judge by how the problem is solved”
I love this quote. A while back the hotel laundry shredded the sleeve of one of my very favorite shirts when it got caught in the machine. This could have been a horrible situation but the hotel handled the problem very well. First they found a store that sold the very same shirts, unfortunately the store did not have my size so the hotel was unable to directly replace. They then offered to pay for a new shirt, regardless of the type, when I purchased a new one. As it happens that shirt was purchased in London’s Heathrow airport and while on a business trip I purchased a replacement. 6 months later I return to the hotel which had shredded my shirt and handed them the receipt for the new shirt. The hotel gave me the cash value. My shirt could have been destroyed at any hotel, that stuff happens. Judge by how the problem is solved and not by the problem itself. The problem solving is what sets everybody apart.

problem

“Who needs products when you have PowerPoint”
I don’t actually say this but my R&D team has used it with me when the presentation I created is 12 months ahead of the product deliverables. Marketing at its finest is what I say and linked to the “Don’t let the technical details get in the way of a good story” quote as seen earlier. Also used in the TV Series “Better off Ted” which IMO was one of the funniest TV shows around and I highly recommend it.

better-off-ted

And finally, “You don’t buy a dog and bark yourself”
I rarely use this one anymore as to be honest it annoys pretty much everyone you use it with but it does communicate a very powerful message across so use the power wisely. This states, without directly saying it, is this is not my job. I have used this with select individuals when they expect me to do something when clearly I do not have the matching skill set and they do but are just too lazy to do it themselves. This quote is highly abusive so don’t expect the person you use it on to ever speak to you again. (Which is some cases is exactly why I use it)

Do you have other quotes you use day to day in your life? If they are PG rated then please share via comments…

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Humor | 1 Comment »

B2B for Accelerated Time to First Prototype and Assembly

Posted by Michael Posner on June 27th, 2014

holding-hands

This week Synopsys announced the HAPS Connect Program. The HAPS Connect Program is an eco-system of third-party daughter board and services partners for HAPS systems. The HAPS Connect Program expands the choice of HapsTrak and Multi-Gigabit board and service offerings available for HAPS systems. The first members include Fidus, eInfoChips, Sarokal, Gigafirm, Back9 Designs, HDLabs and Zoro. Synopsys is helping connect business to business to accelerate prototype assembly which I have blogged about before here. The HAPS Connect Program helps customers to:

  • Develop HAPS prototypes faster by leveraging compatible daughter boards from leading industry hardware vendors
  • Reduce project risk by taking advantage of hardware and services from vendors with HAPS system expertise
  • Save on prototype development costs and resources by using products and services tailored for HAPS systems

HAPS-Connect-banner

You can see a full list of participating vendors here.

I personally wanted to launch a program like this as I’ve been working with vendors individually for many years. The HAPS Connect Program formalizes the process making it easier to connect HAPS FPGA-based Prototyping customers with vendors with HAPS expertise. Really what I am saying is this program makes my work easier and as we all know it’s all about me J

I think by now all my readers know that I race cars as a hobby but you probably don’t know that I also love to off-road my Toyota FJ. I was out last weekend and for once managed to get some good pictures of the play. The first two don’t make the trail look that hard but just know that by the end of the day I had beaten up the undercarriage of my truck more than ever before and left me limping home with a blown shock absorber and destroyed right front suspension.

Note that the front tire is floating off the ground

Tire-Lift

I love how compressed the rear tire is, shows the articulation you can get with this Toyota.

Tire-Compression

It’s not all about the off road play, the view from this mountain range is beautiful.

View

Finally the crew

Mound-Climb

It’s the July 4th USA week next week so I am not sure if I am going to blog yet. I do have LOADS to blog about but wanted to spread it over a couple of blogs as I’ve noticed that my long blogs bore people to death. Over the next couple of weeks I’m going to talk about PCIe Gen3 prototyping at full speed,  more on the Synopsys IP Accelerated Initiative, my video from DAC and information on building vertical daughter boards, yes vertical!! I have also been asked to write up “Mick’s Quotes” these are a set of quotes I use around Synopsys when interacting with my team, peers and other groups within Synopsys. These quotes are deep and you will be able to use them to wow other with your insight.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in HAPS Connect Program, Man Hours Savings, Milestones | Comments Off

Zoro delivers Hybrid Prototype for Early Software development

Posted by Michael Posner on June 20th, 2014

Zorro

No not that Zorro, but Zoro, http://zoro-sw.com/

First I should note that I just traveled back from Israel and have been awake for over 40 hours at this point, I wonder if this blog will make any sense at all. I was in Israel to present at SNUG, which was very well attended again this year. One of the papers presented was by a company called Zoro Software and they presented the success they had with deploying Hybrid Prototyping for one of their customers. If you remember Hybrid Prototyping is the combination of HAPS FPGA-Based Prototypes with Virtualizer Virtual Prototypes.

The goal of Hybrid Prototyping is to reduce the time and effort to create a prototyping environment  enabling software development to start earlier as well as HW/SW validation. Zoro was able to deliver on this goal and the details with results of the project are posted in their presentation found in the SNUG proceedings. I took the liberty to take a snapshot of the summary slide as I think it does a great job of expanding on all the benefits of Hybrid Prototypes.

benefits

The even more cool thing was that Zoro Software was also demonstrating the Hybrid Prototype at the SNUG event. Below is a picture of Uri Shkolnik, CEO of Zoro software standing next to the Hybrid Prototyping demonstration. In the demo the USB 3.0 controller was implemented on the HAPS system and an ARM based subsystem is running within a virtual development kit in Virtualizer

Zoro-Hybrid

Another amazing thing was that someone managed to capture me smiling, look….

Mick-at-SNUG

I have no idea why I was that happy, just look at the view I had from my hotel room.

photo

(For those who didn’t get it, that was sarcasm above)

I know Israel is a country at war but it’s pretty beautiful and this was by far the most fun I’ve ever had on a business trip. Of course I did celebrate my birthday (29 again) while on this trip and that was simply amazing. I’m looking forward to getting back to Israel again soon and hanging out with new friends.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation | Comments Off

DAC is Dead!

Posted by Michael Posner on June 13th, 2014

Ok, so I used my blog title for the shock and horror effect in an effort to drive up my readership…… In reality DAC is still flourishing and well worth the trip.

My main two takeaways from the event was that #1 IP is everywhere and #2 FPGA-based prototyping is the best way to demo your capabilities be that design, IP or other.

I’m not going to talk too much about the IP mainly as this is a blog on FPGA-based prototyping. I will say that there were many IP providers at DAC and of course Synopsys announced our IP Accelerated Initiative which I blogged about last week. The amount of IP, 3rd party, in-house developed and other is exploding as seen in the Semicon estimations below. This is why so many companies are jumping on the IP bandwagon

IP-in-SOCs

From last week’s blog I got lots of comments on my top secret testing video which I posted. Comments like “Synopsys (and you) have far too much time and money on your hands if you can go off and shoot a video like that”. Or “Who was actually driving the race car” or “that’s some fancy CGI”. Well believe it or not that was a 100% selfie shot video. It is my race car, that is me driving and I shot the video in my own vacation time. I built that race car myself, including many engines over the years and another little secret is that I used to be quite a big name in the aftermarket and dark world of Subaru tuning. Check out this video of me tuning the antilag turbo system on a dynamometer : https://www.youtube.com/watch?v=Ppv3EMGlITY Now that’s fast and furious style but in real life. No, I don’t drive this car on the streets, it’s a pure race car. The only remaining question that I’ve leave open is if the HAPS-DX system was in fact electrically connected into my car’s ECU……..

HAPS-DAC

At DAC FPGA-based prototyping was being used by many vendors to demonstrate their wares. I think the main reason for this is, and as I have stated before, FPGA-based prototyping makes a great way to showcase a design. Just look at how pretty the HAPS booth display looked (pictured above). How can you resist coming to have a look. FPGA-based prototyping is also a perfect development and validation platform for interface IP, the predominant type of IP after embedded CPUs. Early software development, real world IO for interoperability and pre-silicon compliance testing are just some of the values FPGA-based prototyping brings to IP. This is exactly why Synopsys developed the HAPS-DX IP development system and why it’s an integral part of the DesignWare IP Prototyping Kits.

Finally please join me in wishing Yvette Huygen continued speedy recovery from hip replacement surgery.

Yvette-DAC

I hope Yvette does not mind me posting this picture. The Synopsys DAC event crew reserved a chair just for Yvette which was nice. I can relate to Yvette’s pain as I went through similar hip replacement surgery a couple of years back. Wishing you all the best!!!

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in IP Validation, Real Time Prototyping, System Validation | Comments Off

Top Secret IP Accelerated Testing

Posted by Michael Posner on June 6th, 2014

IP-Accelerated

Synopsys’ big press this week from DAC was the announcement of the IP Accelerated initiative. As this initiative combines Synopsys’ leading interface IP, DesignWare, HAPS FPGA-Based Prototyping systems and Virtual Development Kits as you might guess I have been very involved in this evolutionary development. I executed my own personal top secret testing of the deliverables, more on that later in this blog. I’m so happy that we have finally made this initiative public as I have really wanted to talk about it.

Highlights from the press along with my personal comments on each of the bullets

  • The IP Accelerated initiative augments Synopsys’ leading IP portfolio with new IP prototyping kits, software development kits and customized IP subsystems

Synopsys has taken an evolutionary step and will be delivering packaged subsystems for DesignWare IP with HAPS FPGA-based systems for immediate prototyping productivity, virtual development kits enabling pre-RTL early software development. These DesignWare IP reference subsystems also enabling rapid customization for application specific needs. Customers demand high quality IP where the digital RTL controller has been validated against the mixed signal PHY and Synopsys has always delivered this value. The IP Accelerated initiative delivers the DesignWare IP packed up in a reference subsystem. The subsystem enables Linux to be booted immediately, no effort from the user, and includes the DesignWare IP software drivers. These subsystem references enable the IP users to be immediately productive with either early software development for the select IP. For the hardware or prototyping engineers these subsystems deliver a fully operational prototyping reference which can be used to explore the IP capabilities and accelerate the bring-up of an SoC level prototype.

  • The DesignWare IP Prototyping Kits include a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers

Wow, it’s like the Synopsys R&D engineers have been reading my blog and have implemented a hugely scalable IP prototyping subsystem enabling immediate productivity and a flow for streamlining IP to SoC prototype bring up.  I urge you to watch the videos, especially the demo as it’s amazing to see Linux boot so fast and see the IP operating under a real OS.

  • The DesignWare IP Virtual Development Kits are SDKs that include a processor subsystem reference design, a configurable model of the DesignWare IP as well as a Linux software stack and reference drivers

These deliverables are targeted at the software engineers who want to start there customization of the DesignWare IP drivers targeting their specific application. The advantage of the SDK is that they do not require RTL, they are highly portable and very fast. The advantage of the hardware based DesignWare IP prototyping kits is that they include the prototyping model of the DesignWare IP RTL so cycle accurate and physical real world IO enabling compliance and interoperability testing. Software drivers developed on the SDK can be executed on the real hardware to validate their operation in real world scenarios.

  • For hardware engineers, the IP Prototyping Kits provide a validated IP configuration that can be easily modified to explore design tradeoffs for the target application
  • For software developers, both the IP Virtual Development Kits and IP Prototyping Kits can be used as proven targets for early software development, bring-up, debug and test

These are self-explanatory, basically you are productive immediately. Even an engineer with no previous IP, FPGA-based or virtual prototyping experience can use them.

  • To reduce risk and accelerate time to market, Synopsys experts can assist designers in creating and customizing IP subsystems for their specific application requirements as well as integrating the subsystems into their SoC

The deliverables are packaged as a reference but as the IP is highly configurable enabling it to be tailored to application specific needs it’s expected that the deliverables will be modified for specific project usage. Some of this customization is enabled directly in the kits and the Synopsys experts are there to help with this task.

As mentioned above, I have been personally involved and took on a top secret project as a test pilot. You can see the summary of the top secret testing here: https://www.youtube.com/watch?v=WN-ZsLK_IZw

IP_Accelerated_Initiative_test_pilot

Do you have a question on the IP Accelerated Initiative? If yes, post me a comment and I promise to respond.

I was at DAC this week, I’ll write up that fun next week

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Debug, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation, Real Time Prototyping, System Validation, Use Modes | 2 Comments »

Go Faster Stripes

Posted by Michael Posner on May 31st, 2014

It’s was a short week for me with Memorial day on Monday and the I took Thursday off to play at the race track. Next week is DAC so if you happen to be visiting make sure you drop past the Synopsys booth and say hello. I’m only attending DAC on Monday so don’t miss out, maybe I’ll buy you a cup of coffee or something.

My track time this week was tough, I coach for a company called Hooked on Driving and this time I had a novice student who had never been on the track before as well as being the Group D lead. A group lead manages the group ensuring they are safe and controlled. Group D are the top advanced driver group, many of them long time racers, but Hooked on Driving is not a racing event. This group was very hard to control so on top of a novice student I was running around way more than usual. I actually only drove myself in the morning sessions. Here is a link to one lap following one of the Group D drivers. https://www.youtube.com/watch?v=W9eXJ6M2wY4 The good news was that my novice student was very easy going and did a great job on track as well as off track picking me up so I didn’t have to run around too much.

With DAC coming up I promise that I’ll have a lot to write about next week.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Mick's Projects | Comments Off