I liked the interview style and the whole interview was shot in one take, no breaks and was completed in less than 5 minutes. I think you will find the video informative so please watch it. Let me know if you liked it as well by posting a comment below.

While I would like to also claim the prestigious recognition as the best dressed presenter out of all the DAC interviews that EDACafe did I am afraid I cannot. Dr. Johannes Stahl, Director of System Solutions at Synopsys takes that award. http://www10.edacafe.com/video/Synopsys-Dr.-Johannes-Stahl-Director/39970/media.html . That’s a bold and smart look with the red tie, nicely done Johannes.

Off topic, after I posted pictures of my track race car a couple of months back I got a lot of questions on the specifics of the engine. A stock Subaru makes around 200 wheel horse power and my car measured on a rolling road is over 450 wheel horse power and I was asked if it’s the same engine. Well the answer is yes and no. The engine block is based on the stock Subaru horizontally apposed setup but highly modified. Basically the only stock item is the engine case itself and even that is sleeved to strengthen the cylinder walls. I also replace the crank shaft, rods, pistons, valves, cams, fuel system and most importantly the turbo. I run a huge turbo so large that squirrels get sucked into the intake manifold if they happen to get too close.

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No squirrels have ever been hurt while I have been driving.

HAPS was prominently displayed as part of the Synopsys booth and staffed by the highest quality Synopsys personnel. Below you can see a picture of the HAPS stand and booth babes

L-R – Andrew Dauman – VP of HAPS R&D, Mick Posner – Director of Marketing HAPS, Ed Bard – Senior Director of Marketing

Andrew and Ed attended Monday through Wednesday and also reflected that they had many great interactions with attendees.

DAC size wise if far smaller than the Japanese ET/EDS Fair which I attended last year. Of course ET/EDS Fair is a combination of many design fields not just EDA. I have to wonder if DAC would benefit from a scope increase.

If you have not already done so I suggest you check out Eric’s USB blog with his video interviews, funny and informative. http://blogs.synopsys.com/tousbornottousb/

And thanks for asking, Hawaii was a great vacation just far too short. It was tough leaving this view each morning.

Oh, one more thing, THANKS. I’ll be honest, I don’t get many comments on my blogs so it was nice to meet so many people that actually read this blog. This really made my day and it makes the blog effort very worthwhile. I’ve got some great technical posts in the works and some ideas on videos so stay tuned.

While not directly shown in the video this setup is running on the HAPS-50 series systems. The HAPS-50 series was first launched in May of 2007, that’s 6 years ago. One of the key benefits of HAPS is the ability to reconfigure and tailor the system to multiple uses across multiple projects. The return on investment increases each time the systems are reused.

Reuse ROI is one of the factors that should be considered when you look to either build your own FPGA board or invest in Synopsys’ HAPS systems. Typically this reuse ROI is forgotten when calculating the cost of ownership of each solution. An in-house board is typically designed with a specific project in mind and its reuse to the next project or with another group in the same company is very limited due to this specific functionality. The generic nature of the HAPS systems mean they can be reused over and over and over again across multiple projects and teams.

I’m out on vacation for a week so unless I find a guest blogger I won’t be posting for two weeks. Don’t forget about me!

What topics would you like to see me blog about? Comment below and provide me some ideas.

The HapsTrak specification and the right to purchase Hapstrack connectors is open to all HAPS system users enabling them to quickly build custom daughter boards tailoring the HAPS systems to their desired function. The Hapstrak specification and connector design was developed by Synopsys specifically for use with the HAPS systems.

This is the picture of the original Hapstrak 1 connectors mounted on the HAPS-50 systems

This is a picture of the Hapstrak 2 connectors (with pcb riser) mounted on the HAPS-60 systems

Finally a picture of the Hapstrak 3 connectors mounted on the new HAPS-70 systems

The Hapstrak 3 connector is an off the shelf connector with a customized pin out to meet the specific requirements of FPGA-Based Prototyping. If you are a HAPS user then Synopsys is happy to provide you the Hapstrak specification. We also provide a complementary review service for HAPS customers designing their own daughter boards. This courtesy service includes a review of the form factor, design of HAPS specific capabilities and general checking of PCB design for high performance.

As a reminder the Hapstrak connectors mounted on the HAPS-70 systems are bank and Xilinx Super Logic Region (SLR) matched enabling high performance from the daughter board to the Xilinx part or interconnect flexibility when connecting multiple FPGA’s. Hapstrak 2 was 119 IO’s per connector while Hapstrak 3 is 50 IO’s per connector, higher granularity means less IO waste. The new Hapstrak 3 has over double the performance of the previous connector making it easy to interface at high speed to daughter boards and other connectors via the HAPS interconnect intelligent cables.

Let me know if you want more information on Hapstrak or anything HAPS based.

Kirk Saban of Xilinx answered my question of why the line rate of the -2 2000T silicon is 10.3125. Kirk states:

10.3125 Gb/s is the line rate required to support 10 Gb Ethernet which requires 64b/66b encoding. (10Gb x 66)/64 = 10.3125 Gb

I would have been surprised if Kirk got this wrong as he is the Product Manager for the V7 FPGA’s. Kirk then goes on to challenge us with a follow question:

I will follow up my answer with an additional question… what speed grade of 7V2000T is required to support 12.5 Gbps!?

You would have thought the answer is the “-3 part” but you would be wrong as there isn’t a -3 part. The correct answer is the -2G part. I found the following text in one of the Xilinx datasheets which confirms the -2G part

Thanks to Kirk for answer the question and enlightening us on the -2G part. For this honor Kirk gets to buy me dinner and drinks the next time I’m in CA.

USB is everywhere; even my fridge has a USB port. Last week I asked a non-tech-savvy person if they knew what USB actually stood for. They didn’t know, they just knew that it’s everywhere and mostly works out of the box. (Universal Serial Bus for the non-tech-savvy readers). While USB is everywhere it still presents a challenge to FPGA-based prototypers as the various interfaces have minimum frequency requirements and timing constraints between RTL controller and mixed signal PHY. I ran across a great write up by John Kuhns, Design Consultant, Synopsys Professional Services, in this month’s DesignWare Technical Bulletin, http://www.synopsys.com/Company/Publications/DWTB/Pages/default.aspx

Here is a link directly to the article: http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-usb-prototyping-2013Q2.aspx

John provides insight on how to get your HAPS-based prototype up and running in a short period of time by taking advantage of solutions such as a implementing a simple USB device driver written in C and a WINUSB-based host driver to facilitate testing. Nice work John!

Coincidently Synopsys just launched the USB University, http://www.synopsys.com/IP/Pages/usb-university.aspx If you are new to designing with USB, or looking for tips on implementing USB 3.0 IP, Synopsys’ USB 3.0 University has a session for you. From a basic USB overview, to implementing USB on FPGAs, to top-level synthesis, you’ll find the information you need in this instructional video series.

Off subject does anyone know which year Pacman the video game was launched?

Yes, last week someone drove into my car hauling fully enclosed trailer. Ouch. No one was injured but I was spooked by what the other drive said when I asked what happened, their response

I didn’t see you

Come on now, it’s a 25 foot long fully enclosed trailer that blocks out the sun. Maybe that’s the issue, maybe it’s really a black hole in disguise and the other driver was sucked into it !!!!

Last week I was asked if the Xilinx transceivers, the high speed serdes capable pins, were available on the HAPS-70. The answer is yes, we make 16 lanes of the transceivers available per FPGA across two multi-gigabit (MGB) connectors. The MGB is a generic connector meaning that the user of the HAPS system can either use an off-the-shelf MGB daughter board from Synopsys or build a custom MGB style daughter board to access the transceivers. Synopsys provides off-the-shelf MGB daughter boards for PCI E, SATA and Ethernet. The transceivers support a wide range of different protocols.

Here is an example of the Synopsys PCI MGB daughter board

Here is an example of the MGB access riser. A user would build a MGB daughter board to either plug into this of bypass it and go straight into the MGB connector itself.

Different from the previous “T” Xilinx FPGA variants the Virtex-7 2000T’s speed grade changes the max speed of the transceivers. The -1 part supports up to 6.6 Gb/s while the -2 part supports up to 10.3125 Gb/s. Does anyone know why it’s 10.3125 Gb/s? I do but if you know the answer make a comment below and I’ll ensure you are written up as a star in my next blog.

So what has this got to do with Jim Hogan you all ask….. well read on and find out.

The cloak of invisibility must be an undocumented feature of the HAPS product line as Jim Hogan wrote a complete article on emulation with mention of prototyping and managed not to mention HAPS once (well ok, once but that was in a table and that was the only mention). I should state that I do not know Jim personally and hold nothing against him. Jim’s article was pretty good but I am afraid I have to personally doubt the credibility of the data when the highest quality and most well-known FPGA-Based Prototyping product, HAPS, didn’t get a proper mention. Jim what were you thinking!!!!  Jim’s article focused on emulation but draws reference to FPGA-Based prototyping a number of times which is why I think HAPS should have been included in the article.

I have to believe that this omission was due to the undocumented HAPS cloak of invisibility. Jim; contact me and let’s solve this mystery.

What also got me all riled up was the following;

• All FPGA-based solutions are “Emulators”

Not so! Jim included FPGA-based prototypes in the discussion – referring to them as “low-capacity emulators” (and never mentioned HAPS). Emulators focus on Verification providing a high level of automation and debug.  FPGA-based prototypes focus on Validation providing the high performance needed for software development and system validation with real world IO. I’ve blogged about the differences in the past (here).  Below is a recap of that incredible blog with simple graphics

I love the above analogy. You own both but depending on the task at hand you pick the right tool for the job.

The following simplifies the difference between Verification and Validation. While they both start with the letter V the goals are very difference which is why both emulation and prototyping play an important part of an SoC’s development.

Oh, I should also apologize for being tardy on my blog post this time around. I’ve been traveling a lot and when weighing up either writing a blog or sleeping, sleep always won.

I was challenged this week to explain why HAPS systems don’t have DDR memory hard wired directly on the FPGA but rather support them via a daughter board. The assertion from the person (they work at Synopsys) was that you couldn’t support the DDR3 speeds via a connector and DDR3 had to be hard wired.

First of all, this person obviously does not read my blog otherwise they would have read me UFC Cables vs. PCB Traces blog a while back: http://blogs.synopsys.com/breakingthethreelaws/2013/03/ufc-cables-vs-pcb-traces/ It includes information on the high speed HapsTrak 3 connectors. Just from this post they should have worked out that the Hapstrak connectors has the performance capable of supporting DDR3 interface speed. Another give away that DDR across a connector on a daughter board is not a problem is that we supported DDR2 on the classic HAPS-50 systems and support DDR3-800 (400MHz interface) on the HAPS-60 system.

With the HAPS-70 systems and the move to the new Hapstrak 3 connector we raised the bar again and support DDR3-1066 (533Mhz interface) and have even been testing at DDR3-1333 (666 MHz interface).

So you say argument done, Mick wins, case closed…….. NO. Challenge me and prepare to go down. Now it’s my turn, I’m on a mission to show that not only does HAPS support DDR3 but because of the flexible daughter board implementation that the prototypers get additional value. Some people would call this the double punch, I like to call it the punch while holding a brick (yay, finally I tie the title of this blog into the post).

The brick held punch; Simply put, if you hard wire DDR3 or any interface to the FPGA of a prototype you are reducing your IO count available for interconnect or other daughter boards. If you read my post on interconnect flexibility and signal mux ratio: http://blogs.synopsys.com/breakingthethreelaws/2013/02/how-io-interconnect-flexibility-and-signal-mux-ratios-affect-system-performance/ you understand the importance of available IO. Lets say your design does not use DDR3 memory, with a board that has DDR hard wired those IO’s are wasted, you are not using the DDR but you can’t use the IOs because they are hard wired. On the HAPS system if you are not using the DDR you have no wasted IO.

If you are using DDR memory you might think that at that point a solution with hard wired DDR and the HAPS flexible solution are the same. If you thought this you would be mistaken. With a hard wired solution you are forced to place your memory controller in the SLR where the DDR3 is hard wire connected. This pretty much ties your implementation hands which could also force a sub-optimal interconnect topology. With the HAPS system you are free to move the DDR between any of the Xilinx Virtex-7 2000T’s SLR’s. Way more flexible and you get to choose the best location for the memory controller which makes sense to your system. Of course you should always bank and SLR match as that’s the requirement of the FPGA and DDR operation.

So at this point I have proved that DDR on a daughter board is possible, you don’t waste IO’s and the additional flexibility of placement results in a prototype implementation optimized to your design requirements. But I’m not finished…… (I know, I bet you were wishing I was)

Lets look at a block diagram of a typical prototyping board. This board has one DDR3 SODIMM connectors hard wired per FPGA. Tell me, how many SoC’s have you seen with multiple DDR controllers? None, that’s how many I’ve seen.

You are forced to implement your DDR controller in one of the FPGA’s and then you have 372 wasted IO’s.

Now look at the HAPS-70 S48 with the memory controller implemented. NO WASTED IO. If for some crazy reason you did want to implement four (or more) DDR controllers on the HAPS-70 S48 you can do that and you still have the flexibility to implement those where you want to. Just plug in a DDR daughter board.

Now that’s what I call the brick held punch! Anyone else want to challenge me

This week I’m going to go way off topic as basically I am getting bored writing about FPGA-based prototyping. Last week my son wanted to do some painting so I thought it would be fun to paint some fish models and hang them on our fence in the yard. First I cut out the fish shapes from some left over ½” plywood.

Then we painted them. The below ones turned out very well, these are stars and stripes fish, regularly seen swimming off the coast of Texas.

It’s also coming up to track season in Oregon, not many people know that I track race a highly modified Subaru.

Yes it’s an ugly yellow wagon……. An ugly yellow wagon with over 440 wheel horse power… I built a new engine for the car over the winter but didn’t get time to tune it until now. The goal of the build this year was more low end torque so that I could out accelerate everyone else coming out of the corners. I modified the engine heads and cams as well as selecting a smaller faster spooling turbo. The result, 460 ft-lbs of torque at 4400 RPM, oh yes… All this power from a 2.5L engine.

I tune the car on a dyno, a rolling road, so it’s nice and safe and you get a measure of the power at the wheels.

When I say race car I really mean it. Its fully caged and one seat.

The engine setup is a nightmare, 10 years of modifications to either enable more power or to try and secure higher reliability at these huge horse power levels. A stock engine makes ~220 Wheel Horse Power…. So when I say that my Subaru wagon grocery getting is faster than your car, I really mean it.

The funny thing is it’s not my car that surprises people the most, it’s the fact that a Marketing person built it. Imagine that, a marketing person who can do more than powerpoint

Virtual prototypes are not reliant on the availability of RTL so can be used far, far, far earlier in the design cycle. Much software is independent of physical implementation so you get a huge advantage from developing a virtual prototype enabling software development to start early. Because you model the system at a higher level of abstraction you get high performance as well.

On the flip side, virtual prototypes don’t use the physical RTL so it’s only a close representation of the target system, not the system itself. This is the value of FPGA-based prototypes, such as HAPS, they utilize as much of the actual RTL as humanly possible. The FPGA-based prototype is as close as you can get to the real system. Some say (incorrectly) that partitioning and pin multiplexing adds a level of complexity and error. The fact is with new automated techniques offered by tools like Synopsys’ Certify the partitioning and insertion of pin multiplexing logic is transparent to the user and error free.

Then sitting in the middle is Hybrid Prototyping, merging the best attributes of both technologies.

Both technologies play a critical part of the design cycle.