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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'Project management' Category

Addressing the Dark Fibre of FPGA-Based Prototyping, Lighting the Dark FPGA’s

Posted by Michael Posner on 16th October 2015

The term “Dark Fibre (Fiber) refers to the additional lines/capacity of optical connections a carrier would install when they laid a new pipeline. These unlit optical connections were built in assuming the need for additional capacity in the future. The thinking was that it’s cheaper to do it all at once vs. adding lines/pipelines later. The problem is that this extra capacity is going to waste and while the main carrier was not using it, someone else could have.

(There is no difference in meaning between the word fiber and fibre. Fiber is the preferred spelling in American English, and fibre is preferred in all the other main varieties of English and as I am originally from the UK I’m ignoring spell check and using the fibre spelling)

We are seeing more and more users move their FPGA-based prototype hardware off their desks and into a shared resource location. HAPS with ProtoCompiler fully supports this emerging use model. The flexible Synopsys solution can be tailored (highest performance) to individual prototyping projects needs or configured in a more generic fashion for greater flexibility when there are many different teams accessing the system.

HAPS-80 with ProtoCompiler supports IP, Block, Subsystem and SoC level prototyping

Typically customers are building these installations using a standard form factor building block, the HAPS-70 S48 or the HAPS-80 S104. Thanks to the HAPS with ProtoCompiler modularity and scalability it’s easy to chain these to support SoC designs of not up to 1.6 Billion ASIC gates.

The HAPS-80 S104, 104 Million ASIC Gate, 4-FPGA form factor, modular and scalable prototyping system

The problem is that prototyped designs don’t always use up all of the FPGA’s available and you end up with Dark FPGA’s. Dark FPGA’s is capacity that is going to waste within the large array of resources, just like Dark Fibre. But let there be LIGHT,  enter HAPS with ProtoCompiler Multi-Design Mode

HAPS-80 with ProtoCompiler Multi-Design Mode

HAPS with ProtoCompiler Multi-Design Mode allows you to use up this extra capacity by sharing the HAPS Prototyping resources across multiple users and multiple designs. In the example below there are three users exercising four design utilizing a total of seven FPGA’s. The designs range from smaller IP or block level prototypes to larger subsystem or SoC level prototypes. No Dark FPGA’s. ProtoCompiler for HAPS manages most of the complexity to create these portable prototyping images in addition to the user following a documented methodology and best practices.

HAPS-80 with ProtoCompiler Multi-Design Mode Example. No Dark FPGA's

The HAPS systems were designed for desktop usage as well as rack mount as seen in the setup below.

HAPS-80's installed into a server rack. Hey, nice rack!

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Posted in FPGA-Based Prototyping, HAPS-80, Man Hours Savings, Milestones, Project management, Tips and Traps, UltraScale, Use Modes | No Comments »

Customer experiences with ProtoCompiler for HAPS

Posted by Michael Posner on 4th September 2015

Censorship is ............

Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.

So just in case you missed the data the first time around, here it is again, this time just the data points. These two examples are from existing HAPS and Certify users and I define both customers as experienced in FPGA-based prototyping. Results of ProtoCompiler run on their designs.

I can't tell you who this customer was

This first case you can see that ProtoCompiler identified a partition solution in an automated fashion which resulted in a more optimized prototype. In this case shrinking the design from three FPGA’s to two. It’s typically understood that as you consolidate a design into less FPGA’s you can achieve higher performance. The customer will realize the effect of this performance with a reduction in test runtime.

Now the second case below is an example of how ProtoCompiler can be used again to identify more optimum prototype. In this case the solution was not to shrink the design into less FPGA’s but to partition the design at other points in the design spreading it out to four FPGA’s vs. the original three FPGA version. ProtoCompiler was able to utilize HSTDM, high speed pin-multiplexing to improve the overall system performance. A byproduct of the new partition was that compile, synthesis and Xilinx place and route times were halved.

Different customer but I still can't tell you who this is either

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I’ve been dropping “easter eggs” all through my blogs for the last couple of months. If you noticed them drop me a note or comment below on where you found the easter egg. If you don’t know what the term easter egg is then look here: https://en.wikipedia.org/wiki/Easter_egg_(media)

Posted in ASIC Verification, Early Software Development, In-System Software Validation, Man Hours Savings, Performance Optimization, Project management | Comments Off

Would you like 2X Performance AND Reduced Tool Runtime (Turn-around-Time)?

Posted by Michael Posner on 29th August 2015

HAPS HSTDM Testing between HAPS-70 and HAPS-80

Above is a picture of HAPS High Speed Time Domain Multiplexing (HAPS HSTSM) being tested across the current HAPS-70 and the new HAPS systems based on Xilinx UltraScale FPGA devices.

This week I’ve been busy presenting our next generation HAPS Solution, based on Xilinx UltraScale VU440 FPGA’s, to a number of key customers. First of all they love it, the benefit of the co-designed solution combining HAPS and ProtoCompiler are easily recognized. In many cases it’s highly possible that the new solution could increase performance by as much as 2X with a tool flow with reduced runtime. I’m personally confident that the new generation solution will be the most successful HAPS product to date. Each generation of HAPS has been more successful, dollar wise and sales unit volume wise, than the generation before it.

The customers I’ve been presenting to are all existing HAPS-70 users so one of the focus points was to ensure they understood that the HAPS-70 and this new generation are interoperable with each other. Not only does the hardware seamlessly chain, one cable between systems is all that is needed for the system to look like a single setup, but the design tool of choice, ProtoCompiler, supports mixing both Xilinx Virtex-7 and Xilinx UltraScale systems in one project. Of course when you mix systems don’t expect the older system to support the new capabilities. In a mixed setup the feature set supported between the two is dictated by the older generation.

I’ve seen many users get caught when they develop their own capabilities on one of their in-house developed FPGA boards. They tune the capability to the piece of hardware they are running only to find out that it does not run on any of the other FPGA boards they have. This is not an issue with HAPS and ProtoCompiler as they are co-designed and co-tested.

HAPS and ProtoCompiler Co-Designed

Co-design is the term we use for the parallel development of capabilities which require both hardware and tool support. The HAPS High Speed Time-Domain multiplexing and HAPS Deep Trace Debug are great examples of co-designed capabilities. The hardware has to be designed to support the capability and the ProtoCompiler tool has to include the feature to insert and deploy it. The advantage of co-designed capabilities is that the HAPS hardware characterization data is built into the ProtoCompiler tool ensuring that the feature is correct constrained. A version of this constrained feature is then used as part of the production test for the HAPS hardware ensuring that when the capability is used it always runs in a reliable and highest performance fashion. We continuously test the production implementation against the production HAPS systems ensuring backward compatibility in addition to reliable operation you can trust. If your prototype is acting funny you can be assured that it’s a legitimate issue in YOUR RTL or YOUR software and not an artifact of the HAPS capabilities.

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I’m presenting at SNUG Taiwan in a couple of weeks. If you happen to be around the SNUG location, drop in and say hello to me. I’ll be presenting the new HAPS systems and will have a live demo running on the new Xilinx UltraScale based system as well.

Posted in Bug Hunting, Man Hours Savings, Performance Optimization, Project management, UltraScale | Comments Off

Prototyping a PowerVR Series6XT GPU using an optimized flow from Synopsys

Posted by Michael Posner on 24th July 2015

Block diagram on Imagination PowerVR Series6XT GPU

I ran across this blog on Imaginations website which covers details on prototyping the PowerVR Series6XT on HAPS: http://blog.imgtec.com/powervr/prototyping-a-powervr-series6xt-gpu-using-an-optimized-flow-from-synopsys

I highly recommend reviewing the material as it provides insight into not only how to prototype large GPU’s but also how to quickly scale multi-FPGA prototypes.

Short blog this week as I’m off to do a little camping and when I camp I like to camp in style.

Tepui tent installed on top of my Toyota truck

I love my little retro-style teardrop camper and my tent on top of my truck. Enjoy.

Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off

Intel’s FPGA-Based Prototyping presentations from SNUG Israel

Posted by Michael Posner on 27th June 2015

Recently at  SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology guide so I highly recommend you review the material.


Intel presentation from SNUG Israel on FPGA-based Prototyping of SoC's

The second paper titles  “Large Scale IP Prototyping” is a great example of multi-FPGA designs using Synopsys’ HAPS/ProtoCompiler solution and specifically the HAPS High Speed Time Domain Multiplexing to pass ~25K signals between FPGA’s. The material presents Intel’s usage and results and again I recommend downloading and reviewing the material.


Intel presentation on Large IP Prototyping using HAPS and ProtoCompiler

Oh, you need to have a Synopsys SolvNet ID to download….. Oh#2, I just noticed the proceedings are not posted yet. I am reliably informed that they will be posted shortly.

Many of you know that I travel internationally on business on a regular basis and have asked how I cope with the constant time changes. I employ two simply methods to manage jet lag, #1 No alcohol while traveling at all. This helps when you are only getting 3-5 hours of sleep and #2 Coffee

Best jet lag #2 Coffeeeeee

Luckily while in the UK they serve up vats/buckets of coffee that require two handles to hold the weight. This is a six shot “eye opener”

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Posted in ASIC Verification, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Project management, System Validation, Technical, Tips and Traps, Use Modes | Comments Off

Reduce WNS by up to 60%, sometime more

Posted by Michael Posner on 17th April 2015

Bats with White Nose Syndrome. Please help reduce the spread of this and wash boots, clothes and equipment between caves

The WNS I am talking about is Worst Case Negative Slack and not White Nose Syndrome, a disease in North American bats which, as of 2012, was associated with at least 5.7 million to 6.7 million bat deaths. Please help and stop the spread of this nasty disease. Poor little bats have no defense against it. The WNS I’m going to talk about is Worst Case Negative Slack of a prototyping design, reduce WNS and prototype execution performance increases.

A couple of weeks back I blogged on Timing Biased Partitioning and received a number of follow up questions and comments. This blog is to hopefully answer those and provide more information on the Synopsys capabilities to optimize for the highest system performance on your HAPS-based prototype.

The first question, actually statement was from one of the Synopsys engineers who correctly pointed out that my blog title only covers a fraction of what HAPS ProtoCompiler does in the area of prototype performance optimization. In addition to reducing the number of multi-hop paths during the automated partition stage, ProtoCompiler can also reduce the path length and automatically use a lower pin mux ration on multi-hop paths. The combination of these result in the highest performance prototype. In essence timing biased capabilities cross the partition, system route and system generate stages of the prototyping design flow.

Something that I did not mention in the previous blog was the recommendations for pin mux ratios for optimized performance, so here they are.

  • All paths are not critical
    • Some paths don’t need to be fast
    • False paths and asynchronous clock crossing
    • Slow clocks and debug paths
  • Some paths are just fast, pipeline paths with little logic
  • Don’t use one HAPS HSTDM ratio everywhere
    • Lower ratios on critical paths
    • Higher ratios on non-critical path
    • HAPS ProtoCompiler supports ratios up to 128:1
  • HAPS Hardware Traces are precious
    • High ratios on non-critical paths, frees up traces for critical paths (HAPS flexible interconnect)
  • No cost to mixing ratios with HAPS HSTDM
    • Source sync clock is shared across ratios
    • No overhead of mixing ratios

Much of this is automated in HAPS ProtoCompiler but the 2nd question was why these timing biased capabilities are not default “ON”. The answer is that typically the goal at the start of the project is Time to First Prototype (TTFP), and you sacrifice performance optimization to get a valid solution in the least amount of time. Optimization for performance, while automated, increases the runtime of the tool. The recommendation is that you utilize the HAPS ProtoCompiler TTFP mode to generate a feasible solution and hand this off to your developers. While it might not be performance optimized your developers will thank you as you delivered it very quickly. They can be very productive debugging the initial HW/SW integration, board support software and completing initial OS boot procedures. With your developers busy and happy you have an extra day or so to optimize the platform for performance. Now you turn on timing biased capabilities as you can afford the slightly longer runtime to a feasible solution. This is an iterative process as you play with partition, route and physical interconnect on the HAPS systems.

The results of HAPS ProtoCompiler timing biased capabilities are astonishing and I was able to get my hands on the results of these capabilities from a suite of test designs. This suite of designs consist of real customer designs which we have gather over time (with permission). The goal of this testing was to judge the automated capabilities of the tools.

HAPS & ProtoCompiler test suite of designs for timing bias optimization benchmarks

First the “hop” reduction with multi_hop_path optimization enabled is amazing. It’s hard to see in the picture but all designs yielded multi-hop path reduction with the capability enabled.

HAPS ProtoCompiler multi-hop reduction. Less hops = higher system execution performance

Second, the effect to worse case negative slack showed up to 60% reduction. Reduce WNS and performance is improved !!!!

HAPS ProtoCompiler timing bias optimization WNS reduction yields up to 60% execution performance improvement

The funny thing is that the effect on runtime is not huge so while above we recommend a TTFP flow first and then a timing optimized flow you can be successful in generating a timing optimized solution right out of the starting gate. Well at least a version where you have enabled the capabilities but spend no time analyzing the output. Remember, to get the most out of the HAPS solution you should tailor the HAPS hardware flexible interconnect to the SoC partition needs.

I’ve not had much time for projects recently and the next couple of months are busy, busy, busy with business stuff but I have been making slow progress on my new gaming console in a briefcase. Below you can see pictures of the custom controllers, I had to make them small to ensure they fit inside a briefcase. The second picture is a mock up of the monitor and controllers in the briefcase. You open the case and the monitor pulls up and can be rotated for vertical and horizontal play. The whole system is powered by two 7 ah 12v sealed batteries which based on the current draw should enable 5 hours of play before needing to be charged. There are 912 games installed, all the old school favorites like pacman, donkey kong, street fighter, 1945 etc…

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Mick Built Toys, new gaming console in a briefcase controllers

Mick Built Toys, prototype of monitor and controllers in a briefcase

Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Performance Optimization, Project management, System Validation, Use Modes | Comments Off

Prototyping Over 700 Million ASIC Gates Using Xilinx Virtex-7 2000T FPGAs

Posted by Michael Posner on 10th April 2015

HAPS Super Chain Testing at Synopsys HAPS Lab, 64 FPGA's operating together

You read the title correctly, this blog discusses prototyping over 700 Million ASIC gates using the Xilinx Virtex-7 2000T FPGA’s. To get to this capacity you need to utilize sixty four (64) FPGA’s. The picture above was taken in the Synopsys HAPS lab and shows part of our Super Chain testing. As noted previously, HAPS documented seamless deployable capacity is 288 Million ASIC gates, which is six HAPS-70 (four) FPGA systems chained together, a total of twenty four (24) FPGA’s. However we have customers where this is not enough. The HAPS solution is modular and scalable with base building blocks of x1, x2 and x4 FPGA systems and supported with a HAPS-Aware design tool flow.

The HAPS capabilities and software infrastructure enables the solution to scale with ease but Synopsys does not claim support for capabilities until they have been tested and validated. Once the HAPS systems are configured in the Super Chain they act as one unified massive prototyping system. Thanks to our synchronized clocking capabilities the prototyped design still utilizes the HAPS High Speed Time-Domain Pin Multiplexing, HSTDM, which enables the highest system performance. The above picture super chain models sixty four FPGA’s operating synchronously with HSTDM between all FPGA’s ensuring the highest system performance. That’s over 700 Million ASIC gates (12 million ASIC gates per FPGA)…

While HAPS can scale to these huge systems that does not mean that users of just x1, x2, x4 or x8 FPGA’s do not benefit from this testing. Testing of such large systems ensures that the communication, clock synchronization, HSTDM and other capabilities are bullet proof which benefits the smaller system usage ensuring maximum reliability and uptime when used in server farms or on the user’s desk.

Off subject, while visiting Mountain View CA I noticed that one of our creative R&D engineers had come in over the weekend and decorated their Cube space for Easter

Easter Cube decoration

Absolutely amazing don’t you think! Anyway I introduced myself to the R&D engineer and congratulated them. Apparently they do this once in a while and shared a couple of pictures of their previous cube creations.

Cube decoration Cube2 Cube3 Cube4

Crazy cool right!!! I also think that this R&D engineer might have just a little too much time on their hands. Or maybe they are just like me and maximizes every second or every day. I personally think there is a business here, cubicle decoration in a box…. Would you buy a box of decorations to jazz up your cube?

Posted in ASIC Verification, Debug, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, Man Hours Savings, Project management, Support | Comments Off

Success Prototyping with UltraScale VU440 devices

Posted by Michael Posner on 3rd April 2015

UltraScale based HAPS system operation in Synopsys lab

It’s been a while since Xilinx shipped the first UltraScale VU440 engineering sample devices to Synopsys so I thought it time to deliver a short update on development progress. It might be hard to see in the above but that is a picture of one of the new development HAPS systems for the UltraScale VU440 devices. I say hard to see not only as the picture quality is low but also because we have the system completely configured with intelligent interconnect as part of our stringent characterization and functional validation process.

Each module is individually tested, see picture below as an example, this is the controller module in standalone test. The controller module hosts the HAPS supervisor which controls the system and manages advanced capabilities such as the Universal Multi-Resource Bus, UMRBus for short. Once all individual modules are signed-off they are assembled and the system is validated.

New HAPS Control module in standalone test jig

So far both the Xilinx VU440 devices and the new systems are functioning well. Xilinx has posted an errata on the engineering sample VU440 devices but these issues do not preclude the devices from being useful for system development or actual usage as part of a production prototyping project. All IO’s are operational as well as the transceiver GTH links. We have been filling the devices with high speed toggle designs as part of the performance and power characterization and smaller IP designs for other test purposes so we have not compared the utilization between V7 and UltraScale devices yet. We still predict that the UltraScale VU440 devices will deliver ~26 Million ASIC gate capacity, about 2.2X increase over the V7 2000T devices.

As a teaser for future blogs, the new integrated solution is expected to deliver

  • Highest performance w/superior partitioning & new time domain pin-multiplexing schemes
  • Always available debug with deep trace storage
  • Fastest time-to-first-prototype with HAPS aware prototyping software
  • Rapid Turn-around Time from RTL to Bit file with incremental flows
  • Native integration for regression farm & remote accessibility
  • Both HW and SW tool flow is Modular & scalable to over 24 FPGA’s (Over 600 Million ASIC Gate capacity)
  • Hybrid Prototyping ready

Preserves existing HAPS investment

  • Interoperable with HAPS-70 & HAPS-DX, (mix and match HAPS V7-based systems with UltraScale systems) same form factor, I/O voltages, HT3 connectors, daughter boards, cables

In the coming months I’ll post more information on these new and unique capabilities.

HAPS Integrated solution

Posted in Admin and General, ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Project management, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off

Want it all? Capacity, TTFP, Performance, Debug and More

Posted by Michael Posner on 16th March 2015

Possibly inspired my one of my blogs, Troy Scott, wrote a new whitepaper to help dispel the myths of physical FPGA-based prototyping. TTFP = Time To First Prototype

New Whitepaper, Busting the Myths Prototyping

I highly recommend this whitepaper as unlike my blogs, which I write mostly on the fly, this whitepaper obviously had a lot of thought put into it.

That’s it for the blog this week. I was traveling in the UK last week so I am a little jet lagged. While there I picked up a little UK history


It’s a ceramic poppy from the Tower of London remembers exhibit. It’s an amazing piece of history and I feel honored to be able to buy one.

I received another honor, this time from the hotel I stayed at

Mick is Mr Bacon

Yes, I am still known as Mr Bacon. This has a little to do with the fact that I love bacon and more so because I always seem to wear a T-Shirt that says BACON on the front of it.

I also had some fun with the rental car while trying to find parking one day. Below you can see my parking spot halfway up a hillside.

Mick gets crazy with parking spots

I’m not sure if you can see it or not but the back wheel is floating in the air. Fun, fun, fun.

Posted in FPGA-Based Prototyping, FPMM Methods, Humor, Milestones, Project management, Technical, Tips and Traps | Comments Off

Fight Club: Automated vs. Hand Crafted Pin Multiplexing

Posted by Michael Posner on 27th February 2015

HAPS HT3 connectors and cables

This week a prototyping engineer challenged me that “his” customized and hand crafted pin multiplexing capability was “better” than the HAPS High Speed Time-Domain Multiplexing, HSTDM. My response, “Faster, maybe, better NO”. This blog explains why the HAPS HSTDM capability will beat out a custom coded multiplexing capability hands down every time.

First let’s list of the positives and negatives of a custom coded pin multiplexing capability


  • It’s tailored to the exact design requirements
  • It’s tuned for a specific set of FPGA pins and inter-FPGA connections to push performance to the limits


  • It’s hand crafted meaning effort to develop
  • It has to be manually inserted into the design
  • It breaks if the design requirements change
  • It’s tuned so will need to be customized to different FPGA pins and inter-FPGA connections
  • Might be unreliable leading to mystery ghost bugs to chase down

I am sure the list of negatives is longer but I would bet that you already get the idea. While it’s possible to craft a pin-multiplexing block that eeks out every possible drip of performance the overhead of insertion, modification to different design and hardware requirements and testing makes it inferior to the HAPS HSTDM capability.


HAPS HSTDM was designed to deliver an automated, cycle accurate, highest performance, reliable, modular and scalable pin multiplexing solution for the HAPS systems. Automated insertion through ProtoCompiler ensures that the usage is as unobtrusive as possible. HAPS HSTDM is tested to run on every qualified IO pin across the HAPS-70 system. It will reliably run on any HAPS platform, we can claim this as the HAPS hardware itself is performance tested as part of the production manufacturing tests ensuring that all systems and interconnects meet the minimum required performance for HSTDM operation. It supports multiple ratios meeting the need of many different design requirements. It is very high performance using the latest differential signaling and training techniques with built in error detection. Just looking at this list it’s clear that HAPS HSTDM has many advantages over custom.

But wait, there is more…. I would challenge that using the flexible capabilities of the HAPS hardware interconnect combined with the HAPS HSTDM capabilities that the overall HAPS prototype will run at a higher system performance. I’ve talked about this capabilities a couple of times. The HAPS systems do not have any dedicated PCB traces between FPGA’s. All interconnect is done via intelligent cabling. This method enables the HAPS hardware to be customized to better match the DUT’s interconnect needs. This means you can create more interconnect density where the DUT needs it. More dense interconnect can help reduce the overall pin multiplexing ratio required resulting in higher performance system operation. Remember your prototype is only as fast as the slowest link.

HAPS Flexible Interconnect for increased performance with HSTDM

This HAPS flexible interconnect combined with the HAPS HSTDM automated and deployed by ProtoCompiler is a very powerful solution and this is why I claim that it’s “better” than a hand crafted scheme.

More HAPS and HSTDM results

Do you agree?

Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, Project management, Support, Use Modes | Comments Off