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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'In-System Software Validation' Category

Prototyping enables worlds first PCIe Gen4 (16 Gb/s) demonstration

Posted by Michael Posner on 1st April 2016

While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:

DesignWare PCIe Gen4 (16Gb/s) demo on HAPS-DX

This is the demo setup for the DesignWare IP for PCIe Gen4 which is the latest and fast 16 Gb/s PCIe transfer solution. (Sorry for the low quality mobile phone pic). This is the platform which we have been using around the world to demonstrate our hardware validated PCIe Gen4 solution.

At the top of the pic is the ARC platform which is used to execute software to manage the DesignWare PCIe controller core which is modeled in the HAPS-DX system in the center of the pic. The large daughter board at the bottom houses the testchip of the mixed signal PHY. It connects to a simple PCIe backplane which is the card right at the bottom under the PHY daughter board, almost out of sight. The backplane connects up to an almost identical setup on the backside. One side is the root complex, other is the device, both using DesignWare IP as at this time their is practically no PCIe Gen4 hosts on the market.

This reminded me of a key value of FPGA-based prototyping…. EARLY…. This HAPS-based prototyping setup enables validation of hardware and software for a cutting edge protocol. Below you can see a video of the DesignWare PCIe Gen4 setup in action

Can’t embed the video so please click this: https://www.youtube.com/watch?v=P2G2nGqgf2E

You can also find out more about the DesignWare PCIe Gen4 solution on the Express yourself blog, https://blogs.synopsys.com/expressyourself/2015/11/13/the-worlds-second-pcie-gen4-system-arm-beats-intel/ and here: https://blogs.synopsys.com/expressyourself/2016/03/04/the-long-lost-video-the-worlds-2nd-pcie-gen4-system/ and Synopsys webpages here.

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Posted in DWC IP Prototyping Kits, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | Comments Off

It’s not too late to attend SNUG Silicon valley

Posted by Michael Posner on 28th March 2016

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

Prototyping topics:

  • Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System
  • FPGA Debug: Improving Debug Turnaround Time in High Speed Designs
  • Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution
  • Adapt, Port, and Integrate Quickly – Prototyping the Right Way
  • Address TTM by Prototyping and Validating SoC Design Using HAPS-70 System
  • Reduce Overall TAT and Increase System Performance of Prototype Using ProtoCompiler

Many of these are user presentations so not to be missed.

More details here: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/Documents/snug-sv-2016-schedule3.pdf

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes | 1 Comment »

What’s in it for me? The market shift to integrated Physical Prototyping

Posted by Michael Posner on 11th March 2016

What's in it for me

FPGA-based physical prototyping is the go-to standard for high-performance, high-productivity verification, debug, and software development on many electronic systems today. But, it is becoming increasingly difficult to put together an ad-hoc prototype mixing pieces from various vendors with home-grown components. With the complexity of today’s systems, an integrated prototyping system can bring significant advantages.

Learn about these advantages (the answer to the question “what’s in it for me”) in this Electronic Engineering Journal chalk talk http://www.eejournal.com/index.php?cID=35861 hosted by Amelia Dalton.

EE Journal

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Over the last weekend I coached teens how to handle unpredictable and potentially dangerous driving situations. You can find a short story on the Tire Rack Street Survival School here: http://www.kgw.com/news/local/street-survival-school-helps-teens-become-better-drivers/70835667 At the end of the clip you will see a silver car pass behind the person being interviewed, that was one of my students and I’m in the passenger seat.

The primary emphasis of the Tire Rack Street Survival is a “hands-on” driving experience in real-world situations! We use your own car to teach you about its handling limits and how you can control them. The students will become more observant of the traffic situation they find themselves in. They will learn to look far enough ahead to anticipate unwise actions of other drivers. As the students master the application of physics to drive their cars, they will make fewer unwise driving actions themselves. They will understand why they should always wear their own seatbelts, and why they should insist that their passengers wear seatbelts, too.

I enjoy volunteering for this school as I hope that the skills the teens learn could help save their lives in the future. It’s about more than driving – it’s about LIVING!

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off

Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Posted by Michael Posner on 4th March 2016

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

A recent web seminar presented the various debug scenarios and maps which debug capabilities to use for the particular scenario.

HAPS Debug Visibility Web Seminar

https://webinar.techonline.com/1674?keycode=CAA1BC&cmp=WEBR-fpgabp100503-HPW

I highly recommend you take the time and watch the seminar as it covers not only the traditional physical prototype debug capability but also introduces the new capabilities such as HAPS Deep Trace Debug, the ability to capture huge amounts of debug data as well as HAPS Global State Visibility. Global State Visibility has always been seen as the Holy Grail of FPGA-based prototyping, the ability to trace the state of all design registers, dynamically, without the need to pre-define of instrument.

HAPS & ProtoCompiler Debug Visibility Solutions

The web seminar also includes a mention of utilizing the other capabilities such as HAPS Real Time Debug enabling a debug connection to a Logic Analyzer and cross triggering to aid in HW/SW debug.

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Do you think that the wireless megatrend, data transfer and charging will replace wired USB? Read this: https://blogs.synopsys.com/tousbornottousb/2016/02/26/will-wireless-data-charging-replace-usb/ and post your views.

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale | 2 Comments »

Q&A Using FPGA Prototypes for Software Development & More

Posted by Michael Posner on 26th February 2016

Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.

http://electronicdesign.com/fpgas/qa-using-fpga-prototypes-software-development

Click here for the full article

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off

Prototyping Low Power Functions Using UPF

Posted by Michael Posner on 19th December 2015

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

UPF (IEEE 1801-2009 ― Unified Power Format) is the industry standard for design and verification of low power integrated circuits. As noted above, these low power modes are a mix of hardware capabilities under software control and to verify the operation the two must be run together which poses a challenge for the verification and software engineers. Physical, FPGA-based prototyping would seem like the logical solution to this problem as you are running a high performance, cycle accurate model of the design against the real software. But there is a problem, FPGA’s are not ASIC’s .

FPGA’s are volatile

  • No power islands or partial turn off
  • Configuration file loaded from external memory

Multi-voltage cells are not present

  • Only user configurable cells

A single power and single ground

  • VCC, GND for user mapping

Click picture for full size render.

Low power intent view in ASIC

But will you cannot test the exact power domain capabilities of your design there are still many capabilities which can be modeled in the Physical Prototype which will result in higher test coverage of the designs low power capabilities. To make this process easy the Synopsys ProtoCompiler tool can read your UPF and implement a number of lower power capabilities as part of the HAPS physical prototype. This enables the software that controls these lower power modes to be more fully verified pre-silicon.

Some of the key low power capabilities which can be inferred directly from the UPF through the ProtoCompiler for HAPS flow are:-

Verify/validate logical of the islands and control manager

  • Isolation behavior
  • Retention behavior
  • Power Management Unit (PMU) connections and control

Click picture for full size render

Low power modes modeled through ProtoCompiler for HAPS

With this low power logic modeled in HAPS the design’s low power modes can be more extensively tested. The isolation and retention behavior is a mix of hardware functions controlled by software which can now both be tested together. ProtoCompiler’s implementation of the UPF directives modeled in the HAPS systems the designs inferred low power modes enables the hardware and software engineers to expand the low power mode verification resulting in lower rick risk of post-silicon issues.

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I’m taking a personal break over this holiday period so no blog for a couple of weeks. I would hope that no one is around or bored enough to want to read this blog over the break period anyway so no one will really notice.

I grew a beard for the winter break, (see below) not because I’m hip and trendy but because I like to ski/snowboard/mountain climb during the break and a beard protects your face from the wind. I’ll shave it off in January and then post a comparison picture. I like a beard for the technical reasons listed but I really don’t think it suits me.

Mick grew a beard

Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes | Comments Off

Fastest Time to Productivity using DesignWare IP, HAPS with ProtoCompiler & Hybrid Prototyping

Posted by Michael Posner on 12th December 2015

Hybrid IP Prototyping Kit

While traveling this week I found myself explaining the value of Hybrid Prototyping when used with DesignWare IP or your own IP blocks and RTL code. Simply put, using Hybrid Prototyping you can immerse the IP in the context of the SoC without needing to have RTL for the whole SoC. Hybrid Prototyping enables a Pre-RTL SoC representation to be rapidly created (using off the shelf Virtualizer Development kits as a starting point) and incorporating the block(s) under test modeled in HAPS Physical Prototype. This Hybrid Prototype is used for early software development in the case of the DesignWare IP and can be used in the same way for your own blocks in addition to increasing the verification of the design(s) under test.

Rather than writing an lengthy explanation I suggest you watch the Hybrid IP Prototyping Kits video which explains the key benefits of Hybrid Prototyping. Watch how the DesignWare Hybrid IP Prototyping Kits combine the benefits of virtual prototyping (Virtualizer) and FPGA-based prototyping (HAPS with ProtoCompiler) to speed development of DesignWare IP in 64-bit ARM-based designs

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Can you guess where I was last week from this picture?

What Was Mick Last Week?

This is a picture explaining the perils of business travel

This explains my weight gain

Happy Holidays!

Posted in Debug, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Use Modes | Comments Off

Customer experiences with ProtoCompiler for HAPS

Posted by Michael Posner on 4th September 2015

Censorship is ............

Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.

So just in case you missed the data the first time around, here it is again, this time just the data points. These two examples are from existing HAPS and Certify users and I define both customers as experienced in FPGA-based prototyping. Results of ProtoCompiler run on their designs.

I can't tell you who this customer was

This first case you can see that ProtoCompiler identified a partition solution in an automated fashion which resulted in a more optimized prototype. In this case shrinking the design from three FPGA’s to two. It’s typically understood that as you consolidate a design into less FPGA’s you can achieve higher performance. The customer will realize the effect of this performance with a reduction in test runtime.

Now the second case below is an example of how ProtoCompiler can be used again to identify more optimum prototype. In this case the solution was not to shrink the design into less FPGA’s but to partition the design at other points in the design spreading it out to four FPGA’s vs. the original three FPGA version. ProtoCompiler was able to utilize HSTDM, high speed pin-multiplexing to improve the overall system performance. A byproduct of the new partition was that compile, synthesis and Xilinx place and route times were halved.

Different customer but I still can't tell you who this is either

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I’ve been dropping “easter eggs” all through my blogs for the last couple of months. If you noticed them drop me a note or comment below on where you found the easter egg. If you don’t know what the term easter egg is then look here: https://en.wikipedia.org/wiki/Easter_egg_(media)

Posted in ASIC Verification, Early Software Development, In-System Software Validation, Man Hours Savings, Performance Optimization, Project management | Comments Off

Prototype ready IP for immediate productivity

Posted by Michael Posner on 7th August 2015

MIPI CSI DWC IP Prototyping Kit as seen at SNUG Israel. Hi, thats me, Mick

Back in 2011 I had a vision, a vision for how users of both IP and FPGA-Based Prototypes could be more productive. The problems these users faced was not to do with bugs or lack of capabilities in the products but from the fact that the usage crossed between the two products. IP users traditionally are not experienced prototypers and prototypers lacked IP specific knowledge. Of course this was not helped by the fact that the IP did not document it’s prototyping specific needs. For example, the IP is optimized for ASIC deployment and when you prototype it the clocking, reset and rams sometimes need to be modified to fit into a FPGA environment. Another issue is that as it’s ASIC IP not all configurations can be physically supported in FPGA. For example while the IP might support up to 16 IO ports on the prototype you might only be physically implement up to 4.

So back in 2011 I presented this slide as part of a larger proposal. (Don’t worry, it’s not confidential at this point)

DesignWare IP on HAPS for the Win presentation back from 2011

Eventually this proposal turned into part of Synopsys’ IP Accelerated initiative, the DesignWare IP Prototyping kits. Well I like to think that this was the source of inspiration which lead to the DesignWare IP Prototyping kits. Others “claim” the idea and I’m happy for them to have the glory as they put far more effort taking a vision to reality that I did. It’s still a nice feeling to know that I identified the original need.

Fast forward and there are eight IP protocols supported with over seventeen different configuration varieties including Hybrid IP Prototyping Kit versions.

While at SNUG in Israel recently, the technical marketing manager and I met in front of the MIPI CSI DesignWare IP Prototyping Kit. The picture at the top of the blog is me in front of the demonstration, below is the TMM in front of it.

Hi from the TMM for DesignWare IP Prototyping kits

The funny thing is that this is not really a demo, it’s the actual execution of the DesignWare IP Prototyping kit. This highlights the huge benefit the kits bring to it’s users.

The DesignWare IP Prototyping Kits include the following:

  • Synopsys’ HAPS-DX FPGA-based prototyping system with pre-configured IP and SoC integration logic
  • PHY daughter board
  • Simulation testbench DesignWare ARC-based software development platform running Linux, or PCI Express connection to PC, or Virtualizer Development Kit
  • Reference drivers Application examples

Finally, below is a picture of my favorite coffee mug. Trust me when I say you don’t want to talk to be before I reach the bottom of the mug. I like to say never talk to Mick B.C, Before Coffee. Others within Synopsys have worked out that this is very true but have reduced the quote to “Never talk to Mick”………………. You folks are soooooo funny……

How fast do you run your prototypes? Make a comment and let me know.

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I love coffee

Posted in DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | Comments Off

Prototyping a PowerVR Series6XT GPU using an optimized flow from Synopsys

Posted by Michael Posner on 24th July 2015

Block diagram on Imagination PowerVR Series6XT GPU

I ran across this blog on Imaginations website which covers details on prototyping the PowerVR Series6XT on HAPS: http://blog.imgtec.com/powervr/prototyping-a-powervr-series6xt-gpu-using-an-optimized-flow-from-synopsys

I highly recommend reviewing the material as it provides insight into not only how to prototype large GPU’s but also how to quickly scale multi-FPGA prototypes.

Short blog this week as I’m off to do a little camping and when I camp I like to camp in style.

Tepui tent installed on top of my Toyota truck

I love my little retro-style teardrop camper and my tent on top of my truck. Enjoy.

Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off