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Archive for the 'In-System Software Validation' Category
Posted by Michael Posner on 16th January 2015
In late 2013 I blogged about the newly announced Xilinx UltraScale devices, the VU440 specifically that will be the largest FPGA device on the market: http://blogs.synopsys.com/breakingthethreelaws/2013/12/xilinx-fpga%E2%80%99s-for-fpga-based-prototyping/
Well this week Xilinx officially announced that they have shipped the first samples of the VU440 devices: http://press.xilinx.com/2015-01-15-Xilinx-Delivers-the-Industrys-First-4M-Logic-Cell-Device-Offering-50M-Equivalent-ASIC-Gates-and-4X-More-Capacity-than-Competitive-Alternatives
And check out who received the first of these samples…………………………… ok, you don’t need to read it, Synopsys did…….. We have optimized every generation of our HAPS prototyping systems for the highest system performance, greatest capacity while adding significant capabilities on top delivering prototyping specific features. We all know the FPGA device is a required component within the FPGA-based prototyping hardware but it’s not what defines or makes the solution useful. Anyone can slap an FPGA on a board but this does not help a prototyper as the device alone does not deliver the capabilities they require. Prototypers rely on a solution which includes a software implementation tool flow, integration between hardware and software accelerating time to operation, built in capabilities such as high speed pin multiplexing and high visibility debug to ease bug hunting while being modular and scalable. (side note: Synopsys offers exactly this…. just in case you didn’t know)
I recommend you also check out the VU440 demo video. It stars my friend Kirk from Xilinx who introduces the new device and the demo running ten ARM Cortex-A9 CPU’s, pretty impressive. http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html#uniquePlayer1
Over the coming weeks I’m going to focus my blogs on the capabilities that the new Xilinx UltraScale devices deliver and the impact they have to prototypers. As noted above, an FPGA alone does not deliver FPGA-based prototyping so I will discuss how the device capabilities are expected to be integrated and leveraged delivering a solution.
Oh, and just because Synopsys has received Xilinx sample devices don’t expect a new HAPS next week. Delivering a solution requires hardware development, software development and a huge amount of validation. But I’m confident that when you are ready to adopt, Synopsys will be ready to deliver…..
Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, Man Hours Savings, Milestones, Technical, Tips and Traps | No Comments »
Posted by Michael Posner on 19th September 2014
This week at SNUG Japan I presented on how you can utilize FPGA-based prototyping to differentiate your products. Basically the theme of the presentation was earliest, fastest and highest debug. The earlier a prototype is made available the more productive you can be with it translating into accelerated time to market. The faster the prototype the more tests or complex scenarios could be run translating into higher quality products. With earlier prototype availability and more complex software being run you need better debug capabilities to rapidly track down bugs. The presentation seemed to be very well received and if you have a SolvNet ID you should be able to find the presentation within the SNUG proceedings soon.
Another of the presentations was “Successful Complex GPU IP Implementation on Synopsys HAPS Platforms using ProtoCompiler” which covers the details on the implementation of Imagination’ PowerVR 6XT Dual core GPU on HAPS. There was a live demonstration of the system during the social event after the technical track. Below you can see Andy, one of the Synopsys Application Consultants standing behind the demo booth.
The GPU partitioned across four Xilinx Virtex-7 FPGA’s using ProtoCompiler and is running at over 12 MHz. A fifth FPGA is used as the testbench and interface to the host PC. DriverLive OpenGL is executing on the platform with real time video output. Andy helped setup this same demonstration at SNUG in Taiwan. He seems happier in Taiwan, I wonder why?
There were some other interesting demos, the first was by Fujitsu Semiconductor who was showing off their development platform for the S70 and S73 SoC’s. The Fujitsu S70 development board is connected to a HAPS system via a PCIe Gen2 link. The HAPS extends the development platform and enables customers of the Fujitsu S70 to test their own IP and subsystems.
Another demo was of the DesignWare PCIe Gen3 solution. The PHY test chip board is HUGE. I’m not sure if you can see it but there is a HAPS system attached to the top of it.
Finally there was a demo of the DesignWare IP Prototyping Kit for USB 3.0, part of the IP Accelerated Initiative. The demo was pretty nifty, it starts with all the hardware turned off, the system is then switched on and you watch Linux boot up in a matter of seconds right in front of you. This shows the power of the setup to enable immediate productivity for either early software development for the IP, IP configuration and HW/SW validation
Finally a question, what is the nearest planet to the Sun? Post a comment to respond.
Posted in Bug Hunting, DWC IP Prototyping Kits, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation | 2 Comments »
Posted by Michael Posner on 20th June 2014
No not that Zorro, but Zoro, http://zoro-sw.com/
First I should note that I just traveled back from Israel and have been awake for over 40 hours at this point, I wonder if this blog will make any sense at all. I was in Israel to present at SNUG, which was very well attended again this year. One of the papers presented was by a company called Zoro Software and they presented the success they had with deploying Hybrid Prototyping for one of their customers. If you remember Hybrid Prototyping is the combination of HAPS FPGA-Based Prototypes with Virtualizer Virtual Prototypes.
The goal of Hybrid Prototyping is to reduce the time and effort to create a prototyping environment enabling software development to start earlier as well as HW/SW validation. Zoro was able to deliver on this goal and the details with results of the project are posted in their presentation found in the SNUG proceedings. I took the liberty to take a snapshot of the summary slide as I think it does a great job of expanding on all the benefits of Hybrid Prototypes.
The even more cool thing was that Zoro Software was also demonstrating the Hybrid Prototype at the SNUG event. Below is a picture of Uri Shkolnik, CEO of Zoro software standing next to the Hybrid Prototyping demonstration. In the demo the USB 3.0 controller was implemented on the HAPS system and an ARM based subsystem is running within a virtual development kit in Virtualizer
Another amazing thing was that someone managed to capture me smiling, look….
I have no idea why I was that happy, just look at the view I had from my hotel room.
(For those who didn’t get it, that was sarcasm above)
I know Israel is a country at war but it’s pretty beautiful and this was by far the most fun I’ve ever had on a business trip. Of course I did celebrate my birthday (29 again) while on this trip and that was simply amazing. I’m looking forward to getting back to Israel again soon and hanging out with new friends.
Posted in Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation | Comments Off
Posted by Michael Posner on 6th June 2014
Synopsys’ big press this week from DAC was the announcement of the IP Accelerated initiative. As this initiative combines Synopsys’ leading interface IP, DesignWare, HAPS FPGA-Based Prototyping systems and Virtual Development Kits as you might guess I have been very involved in this evolutionary development. I executed my own personal top secret testing of the deliverables, more on that later in this blog. I’m so happy that we have finally made this initiative public as I have really wanted to talk about it.
Highlights from the press along with my personal comments on each of the bullets
- The IP Accelerated initiative augments Synopsys’ leading IP portfolio with new IP prototyping kits, software development kits and customized IP subsystems
Synopsys has taken an evolutionary step and will be delivering packaged subsystems for DesignWare IP with HAPS FPGA-based systems for immediate prototyping productivity, virtual development kits enabling pre-RTL early software development. These DesignWare IP reference subsystems also enabling rapid customization for application specific needs. Customers demand high quality IP where the digital RTL controller has been validated against the mixed signal PHY and Synopsys has always delivered this value. The IP Accelerated initiative delivers the DesignWare IP packed up in a reference subsystem. The subsystem enables Linux to be booted immediately, no effort from the user, and includes the DesignWare IP software drivers. These subsystem references enable the IP users to be immediately productive with either early software development for the select IP. For the hardware or prototyping engineers these subsystems deliver a fully operational prototyping reference which can be used to explore the IP capabilities and accelerate the bring-up of an SoC level prototype.
- The DesignWare IP Prototyping Kits include a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers
Wow, it’s like the Synopsys R&D engineers have been reading my blog and have implemented a hugely scalable IP prototyping subsystem enabling immediate productivity and a flow for streamlining IP to SoC prototype bring up. I urge you to watch the videos, especially the demo as it’s amazing to see Linux boot so fast and see the IP operating under a real OS.
- The DesignWare IP Virtual Development Kits are SDKs that include a processor subsystem reference design, a configurable model of the DesignWare IP as well as a Linux software stack and reference drivers
These deliverables are targeted at the software engineers who want to start there customization of the DesignWare IP drivers targeting their specific application. The advantage of the SDK is that they do not require RTL, they are highly portable and very fast. The advantage of the hardware based DesignWare IP prototyping kits is that they include the prototyping model of the DesignWare IP RTL so cycle accurate and physical real world IO enabling compliance and interoperability testing. Software drivers developed on the SDK can be executed on the real hardware to validate their operation in real world scenarios.
- For hardware engineers, the IP Prototyping Kits provide a validated IP configuration that can be easily modified to explore design tradeoffs for the target application
- For software developers, both the IP Virtual Development Kits and IP Prototyping Kits can be used as proven targets for early software development, bring-up, debug and test
These are self-explanatory, basically you are productive immediately. Even an engineer with no previous IP, FPGA-based or virtual prototyping experience can use them.
- To reduce risk and accelerate time to market, Synopsys experts can assist designers in creating and customizing IP subsystems for their specific application requirements as well as integrating the subsystems into their SoC
The deliverables are packaged as a reference but as the IP is highly configurable enabling it to be tailored to application specific needs it’s expected that the deliverables will be modified for specific project usage. Some of this customization is enabled directly in the kits and the Synopsys experts are there to help with this task.
As mentioned above, I have been personally involved and took on a top secret project as a test pilot. You can see the summary of the top secret testing here: https://www.youtube.com/watch?v=WN-ZsLK_IZw
Do you have a question on the IP Accelerated Initiative? If yes, post me a comment and I promise to respond.
I was at DAC this week, I’ll write up that fun next week
Posted in Debug, Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation, Real Time Prototyping, System Validation, Use Modes | 2 Comments »
Posted by Michael Posner on 24th May 2014
While at SNUG in England I had the pleasure of being one of the first people on the planet, yes planet, to see the demonstration of the Imagination PowerVR Series 6XT running at speed on HAPS. The demonstration streamed video data from a host to DDR3 on the HAPS system via a PCIe connection. This video data is then manipulated via the GPU and output in real time to DVI for display on a monitor. The demonstration was very impressive and eye catching to anyone who reviewed it. Imagination internally developed this setup to do what they call DriverLive software development as well as be able to run the 1000’s of GPU compliance tests in a matter of hours thanks to the high performance operation.
For the longest time FPGA-based prototypers would be forced to remove the GPU from the prototype as it used to be too complex to model or the platform did not have the scalability and modularity to handle the size (gate counts) of the GPU. In the above setup the IMG PowerVR Series 6XT is partitioned across four Xilinx Virtex-7 2000T FPGA’s using Synopsys’ prototyping tools. One of the keys to being able to do this is the use of high speed signal multiplexing between the FPGA’s handling the very large number of signals that cross between the FPGA’s. There is also an FPGA being used to manage the interfacing to the host PC, DDR3 and DVI real time connection. This design is over 50 Million ASIC gates but even at this size it’s still one of the smaller GPU configurations.
Imagination’s Colin McKellar presented their use of HAPS at SNUG UK and very shortly the paper will be uploaded to the SNUG Proceedings website found here http://www.synopsys.com/community/snug/pages/proceedings.aspx
Imagination commented in the presentation that they intend to continue to improve this setup expanding the configuration of the GPU as well as implementing the design with ProtoCompiler using HAPS High Speed Time-Domain Pin Multiplexing to increase the performance of the setup. I’m excited by this and promise to blog again as I get more information and am approved to talk about it.
Is there something else you would like to know about this setup? If yes then leave me a comment and I’ll follow up
While I was staying at the Hilton Hotel in Reading the staff decided to give me a nick name, see the food slip below
Yes, Mr. Bacon, I have no idea why they picked this name for me but it’s perfect for me as I love BACON. The hotel offers what I think is the best British Breakfast and of course I use the opportunity to get my fill. I took this picture of one of the courses of my breakfast. I didn’t plan this but I think it looks like a Bacon Cookie Monster
What do you think?
Posted in Early Software Development, Humor, HW/SW Integration, In-System Software Validation, IP Validation, Real Time Prototyping, System Validation, Use Modes | Comments Off
Posted by Michael Posner on 16th May 2014
Achieving first pass silicon success is always the goal of the project. While a company may plan for a second chip spin they really want first pass silicon success enabling reduced cost and earlier time to market. I ran across this video featuring Peraso and Eric from the DesignWare USB team, http://youtu.be/DyNyZP8Ysj4 . Now while Peraso do not claim first pass success bringing up a chip in the lab in 24 hours is amazing. Peraso used HAPS FPGA-based prototypes for system validation enabling them to test their software with their RTL implementation before they taped out. As you can tell from the video, Peraso were very, very happy with the fact that they had the silicon up and running in such a short period.
While we are on the subject of videos, here is another featuring the DesignWare HDMI IP and the HAPS-60 series systems. http://youtu.be/Ao-JeWz9g0A
These examples show the power of HAPS for reducing project risk, achieving first pass silicon success and exhibit high performance enabling the validation of very high speed real world interface.
Honestly I’m a little tired this week so I’m going to keep this blog short. A couple of weeks ago I did get the chance to take out one of the best off-road vehicles on the market. While I am used to far more horse power, this one horse power proved sufficient for the activity and we climbed some terrain that not many other modes of transport could reach. Unlike my other hobbies this trek was very relaxing. In addition I did not burn any fossil fuels in the process.
Do you want to meet me in person? Are you going to DAC? If the answer is yes to both drop me a comment and let me know and I’ll be happy to meet.
Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, Milestones, Project management, Real Time Prototyping, System Validation | Comments Off
Posted by Michael Posner on 28th April 2014
Synopsys just announced ProtoCompiler which is automation and debug software for HAPS FPGA-Based Prototyping Systems. ProtoCompiler is the result of years of R&D effort to generate a tool that addresses prototypers challenges today and built on top of an architecture which can support the needs of prototypers long into the future. ProtoCompiler focuses on the needs of prototypers specifically addressing the need for accelerated bring up as well as providing capabilities which result in higher system performance as compared to existing solutions. In this blog I’ll discuss some of the technical details behind the main tool highlights. Below are the detailed highlihts.
Integrated HAPS hardware and ProtoCompiler software accelerate time to prototype bring-up and improves prototype performance
Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs
Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance
Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility
(Read to the end of the blog if you also want an update on Mick’s Projects)
Highlight: Integrated HAPS hardware and ProtoCompiler software accelerate time to first prototype bring-up and improves prototype performance
As noted above the goal of ProtoCompiler is to accelerate the bring up of a prototype as well as providing a path to the fastest possible operating performance. ProtoCompiler is unique as it combines hardware/software expertise with intimate knowledge to deliver superior results. Think of it as delivering a HAPS hardware expert packaged up into a format that anyone using the tool can access. ProtoCompiler has deep technical knowledge of the HAPS hardware including configuration, clocking structures, interconnect architecture, pin multiplexing expertise and more. ProtoCompiler is not only a hardware expert, it’s also a software expert. ProtoCompiler is built on top of a state of the art Synopsys proprietary prototyping database that means RTL is effectively processed and incremental and multi-processing techniques can be deployed with ease.
All this results in blazingly fast processing speeds. As an example ProtoCompiler’s area estimation, essential for automated partitioning, can processed 36 Million ASIC gates in less than 4 hours as compared to 22 hours in existing solutions. Now that’s fast!. Thanks to the new data model and incremental modes all subsequent compiles are even quicker.
Highlight: Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs
So there are actually two announcements packaged up in this highlight. Starting in reverse ProtoCompiler supports 250 Million ASIC gate and larger designs. Humm, this sounds a little suspect as when HAPS-70 was launched it only supported 144 Million ASIC gates, what does ProtoCompiler know that we don’t? Luckily I know, HAPS-70 can now be scaled to support 288 Million ASIC gates, 2x the capacity. HAPS-70 now supports chaining of any six systems so if you chain six HAPS-70 S48’s you get a total of 288 Million ASIC gates supported which is 24 Xilinx Virtex-7 2000T FPGA’s. All working in one synchronous system.
Any 3 HAPS systems can be chained via our standard control and data exchange cabling, when you go above 3 systems you utilize a synchronization module that manages the system synchronization. Managing clock skew, reset distribution and configuration is all handled automatically. ProtoCompiler understands the hardware capabilities thus making deployment of such a system a snap. No longer do your engineers have to worry about how to distribute clocking, we have done the hard work so you don’t have to. Other vendors “claim” scalability and modularity but if all they are delivering is boards then it’s nothing more than a wild claim. To deploy a scalable and modular system you need a complete solution of software and hardware. You can now prototype SoC designs you thought never possible
The first part of the highlight introduces the new partition technology deployed in ProtoCompiler. ASIC’s are bigger than a single FPGA so you need to quickly partition the design across multiple FPGA’s. Historically this has been a challenge but with ProtoCompiler that challenge has been overcome. The partition engine in ProtoCompiler requires minimal setup before you can apply it to your design. There are four simple steps to setup the partition engine #1 Create target system, basically which system(s) you are compiling to. #2 Establish basic constraints which are things like blocks of IO. #3 Define the design clocks. #4 Propose an interconnect structure. Actually #4 can either be defined telling the partition engine to use a set interconnect architecture or leave it open and let the tool do it. There are advantages of both. By letting the tool pick the needed architecture the resulting system should be higher performance as ProtoCompiler will maximize interconnect to reduce pin multiplexing ratio. In a previously deployed system you may have already set the interconnect and then want the tool to use the available resources so you don’t make any changes to the hardware in the field. ProtoCompiler has the flexibility to do both meeting the needs of new prototype creation and image re-spin after a new RTL code drop.
ProtoCompiler partition engine is FAST, using the same example as above, 36 Million ASIC gates, ProtoCompiler was able to come to an automated solution is 4 minutes!!! WOW. ProtoCompiler provides a huge amount of information as to what it automatically did so that the engineer can quickly review the results and maybe provide ProtoCompiler more guidance to optimize the partition. For example after the first run you might want to lock down select parts of the design and then incrementally run the engine to push it to find a better solution for the rest of the design. As it runs so fast you can do multiple of these optimization iterations in a matter of hours. I’ve played with the tool as I was interested in this particular capability and have to say it’s amazing. I’ve tried the open method and let the tool find a solution for itself, in this mode ProtoCompiler pretty much finds a solution every time. I also played with challenging the tool for example locking the tool to use only 100 IO’s (two HT3 connectors) between FPGA’s. ProtoCompiler quickly finishes and told me that I was crazy and that the design could never be partitioned with my selected interconnect architecture.
Highlight: Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance
OK, this is simple, this basically says that ProtoCompiler can automatically deploy the HAPS High Speed Time-Domain Multiplexing (HSTDM). HSTDM is developed and optimized on HAPS and ProtoCompiler packages up this expertize and automated the deployment. The partition engine will automatically select HSTDM and instance it into the prototype design. HSTDM delivers high performance pin multiplexing between multiple FPGA’s. The signals are packaged up, sent across a high performance link and unpacked at the other side. This all happens within one system clock and is completely transparent to the user. No manual intervention, no additional latency, and it’s stable and reliable as HSTDM is tested as part f the HAPS production testing and every system has to pass the minimum HSTDM performance tests. This ensures that when you deploy am image with HSTDM that it runs on every system the image is loaded on. No need to tailor the pin multiplexing implementation for each board like you have to do with other vendors.
Highlight: Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility
ProtoCompiler expands the debug capabilities and grows the HAPS Deep Trace Debug capability which utilizes off-FPGA memory to store debug data. ProtoCompiler provides seamless multi-FPGA debug capabilities on top of a set of other debug capabilities tailored to delivering visibility at the right level of the debug cycle.
In debug one size does not fit all, you need to deploy the right level of debug visibility capability dependent on what you are trying to debug and the specific point you are in the project cycle. Sometimes you want very wide debug visibility with fast incremental turn-around. Later in the design cycle you typically want very, very deep debug windows. ProtoCompiler delivers both, fully automated through the flow, seamless and transparent to the users. And when I say deep, I mean deep, the example below is very typical of the debug window where you can easily capture seconds of debug data.
As usual my blogs got really long. I wrote it in the car while driving from Portland to Eugene. Amazing that I could type all of this and drive at the same time (LOL, only joking I was in the passenger seat)
Anyway, ProtoCompiler is the bees knees and I personally think it revolutionizes FPGA-based prototyping using HAPS. What do you think of ProtoCompiler?
If you have managed to get this far into my blog then congratulations. I’ve been taking it easy this week while I recover from the pneumonia that I came down with. In the evenings I finished off the two mini RC tracked vehicles I had been working on. The basis of both are simple kits which I then modified and added RC receivers and motor controllers to. While I am a grown adult I must admit they are fun to play with. The first is a basic platform RC tracked vehicle which I attached a Lego sheet to. Little did I know that this would be so popular with my son. He has been building towers and all types of structures on top of it.
Why drive your car to a car park when the car park can come to you. No joke that’s what my son said.
Mobile tire store
Bulldozer and sweeper
At the same time I also built a kit that has a shovel that moves on the front. Again I modified it to be radio controlled, including the shovel. This vehicle is a HUGE hit with my son and he has been busy building towers, knocking them down, then tidying them up with the shovel.
There are a couple of video’s of these little things in action on my You Tube page: https://www.youtube.com/user/MrMickPosner (and a video of my chicken food winch system)
Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Project management, System Validation, Technical | Comments Off
Posted by Michael Posner on 21st April 2014
We just published a new success story on Peraso’s use of a number of the Synopsys IP, Tools and HAPS which is why I added the little call out to note this. https://www.synopsys.com/dw/doc.php/ss/peraso_usb_arc_amba_ss.pdf
Feel free to read the whole thing but I’ll focus on what HAPS and prototyping enabled for Peraso. This is what Peraso had to say about it.
Prototyping for Fast System Bring-Up
While working with Synopsys Professional Services, Peraso discussed their need for early software development and Synopsys Professional Services demonstrated how Synopsys’ Virtualizer virtual prototyping tool and HAPS FPGA-based prototyping system could help. Peraso used Virtualizer to start their software development tasks before RTL availability and seamlessly transitioned to their hardware/software integration tasks and system validation with the HAPS FPGA-based prototyping system. “Including Virtualizer and the HAPS system in the suite of Synopsys products we used on this project easily saved us three to six months in development time,” said Lynch.
That summarizes it nicely. As I have noted before, prototype enables earlier, earlier software development, earlier HW/SW validation and earlier system validation. Peraso was able to benefit from all this by utilizing Virtualizer for pre-RTL software development and then smoothly transitioned that to FPGA-based prototyping with HAPS and ran that same software directly on the RTL representation of the design. I’ve reached out to the team at Peraso to see if I can get a couple of pictures of their HAPS setup. Maybe I can get them to guess blog on their usage as well.
It’s been a rather tough couple of weeks for me. Before I went on my trip last week I was feeling a little drained but of course didn’t think it was anything special. While on my trip I felt worse and as soon as I returned to USA I ended up in Hospital, Pneumonia was the diagnosis. Yuck, lack of breath, no strength, drenched in sweat from fever and coughing up some horrible stuff. I was prescribed some antibiotics which cheered me up other than the fact that these same antibiotics are used to treat plague and anthrax victims.
It’s day three after starting the antibiotics and I still feel drained, I’m looking forward to turning the corner and feeling better again soon.
Extra kudos for anyone who comments with the name of the movie the title of this blog draws from?
Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, System Validation | Comments Off
Posted by Michael Posner on 27th March 2014
It was the Synopsys Users Group, SNUG in San Jose this week and on top of the Synopsys announcement on ICC 2.0 with the Powar (I know this is a typo but I enjoy saying the word like this, you try it Powarrrrrr) of 10x there was a whole track dedicated to FPGA-Based prototyping. Knowing that the whole world does not revolve around California I thought I would provide you with an overview of the days FPGA-base prototyping sessions. As a reminder if you have an active Synopsys SolvNet account you can download the session presentations and papers shortly after the event ends
The day started with : Automating SoC RTL to Operational Prototype – Synopsys R&D Presentation
This session delivered technical information on new Synopsys prototyping software that increases the level of automation and streamlines RTL to operational HAPS FPGA-based prototyping including ultrafast partitioning. I personally think this session might have been a little too technical (is there such a thing) as it jumped into how the software solved the problems but seemed to skip the explanation of the problem itself. Now for experienced prototypers they immediately saw the benefits being delivered but I think some of the more in-experienced prototypers were in over their heads. Even with this in mind I highly recommend this presentation. Using this software the user can see up to a 50% reduction in time to prototype, achieve on average 2X or more performance improvement in system performance and get greater debug visibility.
Next up: Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System – SanDisk use of HAPS-70 for an enterprise SSD SoC
Two words, killer presentation. I love seeing real users present their experience with FPGA-based prototyping systems. This presentation included the various steps that SanDisk used to bring up the HAPS-70 FPGA-based prototype of their enterprise SSD design and then optimize it for the highest system performance possible within the limitation of the SoC design constraints. It was very interesting and I recommend the presentation as it includes lots of great real world information on what it takes to create a full SoC FPGA-based prototype. The picture above was snuck off without anyone noticing (until now) pictures/videos within the sessions is prohibited. (whoops)
Final presentation of the day was: Putting IP and Subsystem Prototyping on the Fast Track – Synopsys Mick Posner (yes that’s me) and Antonio Costa from the DesignWare IP R&D team.
I came prepared with giveaway’s to bribe the audience for good feedback, we will have to wait and see if that worked. I introduced HAPS-DX for complex IP and Subsystem prototyping and tried to explain the various validation use modes and best practices for IP prototyping to streamline hand-off to the SoC team streamlining their prototyping efforts. I then handed over to Antonio who provided details on how the DesignWare IP R&D utilize the many generations of HAPS systems to validate the IP. I think the bits that resonated the best with the audience was Antonio’s explanation of the validation scenarios that could only be reached using FPGA-based prototyping. Antonio also introduced the IP R&D teams use of HAPS Deep Trace Debug to capture seconds of debug visibility enabling long protocol scenarios to be successfully debugged.
I highly recommend that you download these SNUG presentations on FPGA-based prototyping from SolvNet.
Progress on my latest garage project has been slowed by business travel and sickness. But I have made some progress and am happy to say that basic functionally has been validated.
If you can’t recognize what it is from this picture then let me tell you that it’s a custom designed remote control tracked vehicle with full suspension tracks. I designed the track runner system and this picture is of revision 2.0. It’s not perfect but it does the job and I can see a 3.0 revision to get better articulation. When finished I’ll take a little video if it in action, it’s a lot of fun. Here is a preview of the vehicle in action: https://www.youtube.com/watch?v=yF4uRSzL5qQ
Some has asked me where I find time to do projects like this, the answer is I don’t find time but I manage to fit in a little here and there at the expense of other things like family time, house projects, eating…. I’m going to slow down on the project as family time, house projects and eating should really take priority.
Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, System Validation, Use Modes | Comments Off
Posted by Michael Posner on 28th February 2014
Recently All Winner announced that their new UltraOcta A80 Mobile application processor utilizing the Imagination PowerVR 6230 64-core GPU would be coming to mobile devices very soon. (I call this the Super UltraOcta just for the effect)
Maybe not many people know this but All Winner utilized HAPS-70, the Xilinx Virtex-7 2000T based systems as part of the development and validation cycle for the A80 Octa SoC
The All Winner SoC features eight ARM(R) processor cores in a big.LITTLE(tm) processing configuration as well as the Imagination PowerVR GPU core. With both CPU and GPU you end up with a lot of hardware/software interaction which we know requires extensive validation to ensure that both the hardware and software are bug free. The high performance of the HAPS FPGA-based prototype enabled a huge volume of tests to be run which are needed to flush out those hard to find bugs.
All Winner’s eight core-based SoC demanded a high performance validation solution to speed validation of their this SoC design. HAPS FPGA-based prototypes are the proven and essential methodology to perform large SoC validation tasks. HAPS delivered the performance needed to validate Allwinner’s A80 Octa SoC. The complexity of Allwinner’s SoC increased both cost and schedule risks due to the need to verify real-world scenarios early in the development cycle. HAPS mitigated those challenges as a cost effective solution that achieved the performance required to validate Allwinner’s SoC, while reducing ASIC design time and cutting months off their development schedule
I went looking on the WWW for a block diagram of this chip but as it’s so new I could not find anything, what I did find on the following link was an different multi-media design from MediaTek http://www.engadget.com/2013/07/29/mediatek-mt8135-biglittle-mp-powervr-series6-g6200/
I’m sure the All Winner and MediaTek designs are different in various ways but we can use this block diagram (on the linked page) to talk about the main componets. You have the ARM CPU and Imagination GPU but you can see all the other standard interfaces such as MIPI, DDR3, LPDDR, USB and a whole bunch of sensor interfaces. The strength of FPGA-based prototyping as mentioned above is perfromance and real world IO. Mobile multi-media designs like this are a perfect fit for FPGA-based prototyping due to the real world interface testing need as well as the challenge to validate the CPU to GPU connectivity. CPUs can be abstrated and run at incredible high performance as virtualized models but GPUs are not a goot fit for abstraction like this. GPUs require full cycle accuracy which is why FPGA-based prototyping is perfect fit for modeling them.
One problem of modeling GPUs on FPGA-based prototypes is the fact that the GPU is typically far bigger than a single FPGA (Hey, that’s one of the Breaking the Three Law’s for FPGA-Based Prototyping). This is where the HAPS Multi-FPGA systems step in and help solve the problem. First the HAPS software tools are used to partition the GPU design across multiple FPGA’s. Belows block diagram is an abstracted diagram of a typical GPU partition. Note the 1000’s of signals between FPGA’s. FPGA’s don’t have this many physical pins so the HAPS High Speed Time Domain multiplexing needs to be used to package up the signals and send them between FPGA’s using a high speed 1Gb/s link.
The HAPS-70 flexible interconnect architecture (Blog on this capability) is utilized to create an interconnect that has increased density where needed to help reduce the overall mux ratio. (Lower mux ratio, higher the system performance) Between this capability and the HAPS HSTDM the resulting platform is optimized and high performance. A GPU partition like the above on HAPS can run in the range of up to 15 MHz which is amazing.
How fast are you running your GPU cores?
Off subject, last week my son was asked to draw a picture of one of their parents hobbies. Finn decided to draw a picture of me and my race car hobby, one of the drawings is below.
I’m not sure where he got the idea that my car racing included using a fire extinguisher to put out engine fires Click the idea link to see a short video of just one case which might have lead him to think this.
Posted in ASIC Verification, Bug Hunting, Early Software Development, In-System Software Validation, System Validation | Comments Off
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