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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'In-System Software Validation' Category

The Prototyping Rub from SNUG San Jose

Posted by Michael Posner on 27th March 2014


It was the Synopsys Users Group, SNUG in San Jose this week and on top of the Synopsys announcement on ICC 2.0 with the Powar (I know this is a typo but I enjoy saying the word like this, you try it Powarrrrrr) of 10x there was a whole track dedicated to FPGA-Based prototyping. Knowing that the whole world does not revolve around California I thought I would provide you with an overview of the days FPGA-base prototyping sessions. As a reminder if you have an active Synopsys SolvNet account you can download the session presentations and papers shortly after the event ends

The day started with : Automating SoC RTL to Operational Prototype – Synopsys R&D Presentation

This session delivered technical information on new Synopsys prototyping software that increases the level of automation and streamlines RTL to operational HAPS FPGA-based prototyping including ultrafast partitioning. I personally think this session might have been a little too technical (is there such a thing) as it jumped into how the software solved the problems but seemed to skip the explanation of the problem itself. Now for experienced prototypers they immediately saw the benefits being delivered but I think some of the more in-experienced prototypers were in over their heads. Even with this in mind I highly recommend this presentation. Using this software the user can see up to a 50% reduction in time to prototype, achieve on average 2X or more performance improvement in system performance and get greater debug visibility.

Next up: Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System – SanDisk use of HAPS-70 for an enterprise SSD SoC

Two words, killer presentation. I love seeing real users present their experience with FPGA-based prototyping systems. This presentation included the various steps that SanDisk used to bring up the HAPS-70 FPGA-based prototype of their enterprise SSD design and then optimize it for the highest system performance possible within the limitation of the SoC design constraints. It was very interesting and I recommend the presentation as it includes lots of great real world information on what it takes to create a full SoC FPGA-based prototype. The picture above was snuck off without anyone noticing (until now) pictures/videos within the sessions is prohibited. (whoops)

Final presentation of the day was: Putting IP and Subsystem Prototyping on the Fast Track – Synopsys Mick Posner (yes that’s me) and Antonio Costa from the DesignWare IP R&D team.

I came prepared with giveaway’s to bribe the audience for good feedback, we will have to wait and see if that worked. I introduced HAPS-DX for complex IP and Subsystem prototyping and tried to explain the various validation use modes and best practices for IP prototyping to streamline hand-off to the SoC team streamlining their prototyping efforts. I then handed over to Antonio who provided details on how the DesignWare IP R&D utilize the many generations of HAPS systems to validate the IP. I think the bits that resonated the best with the audience was Antonio’s explanation of the validation scenarios that could only be reached using FPGA-based prototyping. Antonio also introduced the IP R&D teams use of HAPS Deep Trace Debug to capture seconds of debug visibility enabling long protocol scenarios to be successfully debugged.

I highly recommend that you download these SNUG presentations on FPGA-based prototyping from SolvNet.

Progress on my latest garage project has been slowed by business travel and sickness. But I have made some progress and am happy to say that basic functionally has been validated.

If you can’t recognize what it is from this picture then let me tell you that it’s a custom designed remote control tracked vehicle with full suspension tracks. I designed the track runner system and this picture is of revision 2.0. It’s not perfect but it does the job and I can see a 3.0 revision to get better articulation. When finished I’ll take a little video if it in action, it’s a lot of fun. Here is a preview of the vehicle in action: https://www.youtube.com/watch?v=yF4uRSzL5qQ 

Some has asked me where I find time to do projects like this, the answer is I don’t find time but I manage to fit in a little here and there at the expense of other things like family time, house projects, eating…. I’m going to slow down on the project as family time, house projects and eating should really take priority.

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, System Validation, Use Modes | No Comments »

Super UltraOcta cores with ARM CPU and Imagination GPU’s boosted with FPGA-Based Prototypes

Posted by Michael Posner on 28th February 2014

Recently All Winner announced that their new UltraOcta A80 Mobile application processor utilizing the Imagination PowerVR 6230 64-core GPU would be coming to mobile devices very soon. (I call this the Super UltraOcta just for the effect)


Maybe not many people know this but All Winner utilized HAPS-70, the Xilinx Virtex-7 2000T based systems as part of the development and validation cycle for the A80 Octa SoC


The All Winner SoC features eight ARM(R) processor cores in a big.LITTLE(tm) processing configuration as well as the Imagination PowerVR GPU core. With both CPU and GPU you end up with a lot of hardware/software interaction which we know requires extensive validation to ensure that both the hardware and software are bug free. The high performance of the HAPS FPGA-based prototype enabled a huge volume of tests to be run which are needed to flush out those hard to find bugs.  

All Winner’s eight core-based SoC demanded a high performance validation solution to speed validation of their this SoC design. HAPS FPGA-based prototypes are the proven and essential methodology to perform large SoC validation tasks. HAPS delivered the performance needed to validate Allwinner’s A80 Octa SoC. The complexity of Allwinner’s SoC increased both cost and schedule risks due to the need to verify real-world scenarios early in the development cycle. HAPS mitigated those challenges as a cost effective solution that achieved the performance required to validate Allwinner’s SoC, while reducing ASIC design time and cutting months off their development schedule

I went looking on the WWW for a block diagram of this chip but as it’s so new I could not find anything, what I did find on the following link was an different multi-media design from MediaTek http://www.engadget.com/2013/07/29/mediatek-mt8135-biglittle-mp-powervr-series6-g6200/

I’m sure the All Winner and MediaTek designs are different in various ways but we can use this block diagram (on the linked page) to talk about the main componets. You have the ARM CPU and Imagination GPU but you can see all the other standard interfaces such as MIPI, DDR3, LPDDR, USB and a whole bunch of sensor interfaces. The strength of FPGA-based prototyping as mentioned above is perfromance and real world IO. Mobile multi-media designs like this are a perfect fit for FPGA-based prototyping due to the real world interface testing need as well as the challenge to validate the CPU to GPU connectivity. CPUs can be abstrated and run at incredible high performance as virtualized models but GPUs are not a goot fit for abstraction like this. GPUs require full cycle accuracy which is why FPGA-based prototyping is perfect fit for modeling them.

One problem of modeling GPUs on FPGA-based prototypes is the fact that the GPU is typically far bigger than a single FPGA (Hey, that’s one of the Breaking the Three Law’s for FPGA-Based Prototyping). This is where the HAPS Multi-FPGA systems step in and help solve the problem. First the HAPS software tools are used to partition the GPU design across multiple FPGA’s. Belows block diagram is an abstracted diagram of a typical GPU partition. Note the 1000’s of signals between FPGA’s. FPGA’s don’t have this many physical pins so the HAPS High Speed Time Domain multiplexing needs to be used to package up the signals and send them between FPGA’s using a high speed 1Gb/s link.

The HAPS-70 flexible interconnect architecture (Blog on this capability) is utilized to create an interconnect that has increased density where needed to help reduce the overall mux ratio. (Lower mux ratio, higher the system performance) Between this capability and the HAPS HSTDM the resulting platform is optimized and high performance. A GPU partition like the above on HAPS can run in the range of up to 15 MHz which is amazing.

How fast are you running your GPU cores?

Off subject, last week my son was asked to draw a picture of one of their parents hobbies. Finn decided to draw a picture of me and my race car hobby, one of the drawings is below.

I’m not sure where he got the idea that my car racing included using a fire extinguisher to put out engine fires ;) Click the idea link to see a short video of just one case which might have lead him to think this.

Posted in ASIC Verification, Bug Hunting, Early Software Development, In-System Software Validation, System Validation | Comments Off

FPGA-Based Prototyping in Real Time

Posted by Michael Posner on 2nd February 2014

In a recent customer meeting they described how they used FPGA-Based prototyping and explained the two use models. It was an interesting exchange which I thought would also benefit the blog readers. The two use modes were described as “real time” and “functional” prototyping.

In reverse order, functional prototyping is what I think of as traditional prototyping. The clocks are scaled but still the highest performance model of the SoC with the goal of early software development and ensuring the hardware is validated against the software. HW/SW integration and System Validation are all possible with the FPGA-based prototype.

The other use model, real time, is the one that promoted me to discuss this on the blog as I sometimes forget this usage model. The customer has a very specific need to tune an analog circuit which requires high performance real time operation to get accurate results. The part of the SoC modeled for this purpose is cut down to the bare necessities. This design then utilized the high speed transceivers of the FPGA to interface with the analog logic. The RTL would be tuned to reach the highest performance, in this case over 450 MHz, enabling the real time operation required. This design is a perfect fit for the new HAPS-DX systems which offers a small high performance FPGA with plenty of high speed transceiver links to connect the system to the analog circuit.

We sometimes forget the high speed analog portions of SoCs and real time FPGA-based prototyping is essential to aid the validation of the digital/analog interface. Along the same theme, one of Synopsys’ DesignWare PHY validation engineers popped into my office and explained that he had complete simulation across the HAPS-DX HT3 connectors, across 4” of FR4 then a model of a new DWC PHY board which included another 4” of FR4. After a discussion on crosstalk, reflections he drew some wiggle lines showing the wide open eye diagram at 700 MHz. Now I’m technical but after that discussion I know that while I’m comfortable with digital 0’s and 1’s I am not with analog wiggly lines.

Off-subject here is a summary of my recent car purchase experience

  • First of all I stated upfront that this is a luxury purchase with a set cash spending limit (I informed them the exact amount). I had already done my research and a used 2012 is all I could afford. After telling me the dealer had no 2012’s they started to upsell me on a 2013. Again I reminded them of my spend limit and that I was pretty sure that I cannot afford a 2013. They insisted they would work with me on the price. We walk around the car lot and then moved inside to start negotiation.
  • The car sales person lead with the standard ploy and offered a significant discounting off MSRP. I’m sorry but MSRP is “suggested” retail price engineered to provide car dealers with a starting point for negotiation. The problem was that even with the discount the price was significantly over my spending limit. I declined the offer and the sales person went off to talk to their manager.
  • The sales manager came in and said they wanted to “meet the person who would walk away from such a great deal”. Well buddy now you have, what now? I don’t fall for that one either, it’s not a good deal as it’s not within my budget. While that strategy might work with others it does not work with me.
  • Then the sales manager says, “How about you finance the extra?” Why in the world would I do that!!! I don’t “need” this car, do you people not understand that. I cannot afford this 2013, I knew that going into this but the sales person said they would work with me. This is not working with me, this is a plain old upsell.
  • Finally the sales manager shows me the “dealer” invoice stating this is what we paid for the car. The dealer invoice showed the value of this 2013 being more than they are offering to sell it to me. Give me a break, they would be out of business in if they sell cars at a loss. The dealer invoice is just another way to make the customer think they are getting a great deal. I told them that if they were really willing to sell the car at a loss then they would accept my price limit and sell me the car at that price point. They did not accept my offer.

I did not buy a car this day. The funny thing is that a day later I found a used 2012 at another dealer but it was listed at a price higher than the other dealer wanted for the 2013. I thought this fact would help me negotiate on the 2012 price…. I was wrong, they were firm on the price point. Oh well, no new track car for me.

Talking of track cars I was struggling with not having a project to work on at home. Saturday morning  I pulled together an old remote control kit with two servos, some micro switches, a dual motor gearbox and a track vehicle chassis. (Tamiya makes great kits perfect for home projects like this) Here is a picture of the electronics. Note the popsicle sticks glued to the servos with the micro switches. These operate the two motors on the dual gearbox. Very simple setup, one set controls forward and backward and the other set cut the power to one or the other motor giving the vehicle steering capabilities.

Here is the “finished” tracked vehicle. It looks like a mad scientist project. Whatever you think, it’s a lot of fun to drive around the house.

And finally a little video of it in action: http://www.youtube.com/watch?v=TPxulAEQbg0 and another with the cardboard bulldozer attachment: http://www.youtube.com/watch?v=rCh-tgi3uh8

What fun things have you built recently? Send me a comment and let me know.

Posted in Early Software Development, HW/SW Integration, In-System Software Validation, Mick's Projects, Real Time Prototyping, System Validation | Comments Off

How To: Enable Early Software Development, Find Critical Bugs and Save Up To 6 Staff Months of Effort

Posted by Michael Posner on 25th January 2014

Enabling early software development, finding critical bugs while saving up to 6 staff months of effort sounds like the holy grail of the design and validation. The funny thing is that it’s not a mythical creature, this is the reality of FPGA-based prototyping, specifically HAPS FPGA-based prototyping solution.

Synopsys surveyed it’s HAPS customers (Using a 3rd party called TechValidate) and asked them to describe the value they get from using HAPS. The results in my opinion were pretty overwhelmingly positive. Here is a snippet of the results.

HAPS enables early software development

HAPS helped discover critical bugs

HAPS saves up to 6 months of development effort

All the other results can be found here:


These results show why so many companies utilize HAPS. I’m feeling lonely, please comment on the value you get from HAPS so that I have something to blog about next week

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, In-System Software Validation, Man Hours Savings | Comments Off

FPGA-Based Prototyping Best of the Best

Posted by Michael Posner on 10th January 2014

As it’s my first blog of 2014 (Happy New year and all that) I wanted to reflect back on 2013 and what better way to do that than review the best of the best of my blog postings from 2013. So drum roll please… here is my short list of cracking blog posts from 2013 in chronological order. This is not a list of all the blogs (but it did turn out to be a big list) just the ones that I personally think have the most valuable FPGA-based prototyping information.

Also, check out my new Blog Bio Photo –> 007 Style !!

How IO Interconnect Flexibility and Signal Mux Ratios Affect System Performance

One of the “Breaking The Three Laws” is that your SoC partitioned blocks typically have more signals than physical IO’s on the FPGA. Technically this is not one of the three laws but it should have been and as I own this blog I can make one more up. Welcome to the Breaking The Four [...]

Direct Route or Take the Bus?

Last week’s blog was on direct interconnect density and the effect it has on pin mux ratios. The example focused on using HSTDM but one of the readers correctly pointed out that interconnect density effects any pin muxing scheme, not only HSTDM. The rule of thumb is the greater the density of interconnect routes the [...]

UFC: Cables Vs. PCB Traces

UFC: Cables Vs. PCB Traces With the new HAPS-70 all cable based interconnect architecture we often get asked about overall raw performance of the cables vs. PCB traces. Below is the data on the raw cable and new HapsTrak 3 connector performance. This in itself shows that the cable and connector architecture are cable of running [...]

Jim Hogan falls prey to HAPS cloak of invisibility

I used to own a Ford F350 truck and it was huge with the long wheel base, full bed, extended crew cab measuring a length of about 25 feet (8 meters). The problem was that it came installed with a cloak of invisibility. I didn’t know it had a cloak of invisibility when I purchased [...]

EDACafe Video’s and the best dressed presenter

While at DAC, EDACafe video interviewed me discussing the HAPS-70 FPGA-based prototyping solutions. You can find the video here: http://www10.edacafe.com/video/Synopsys-Mick-Posner-Director-Product-Marketing/40055/media.html I liked the interview style and the whole interview was shot in one take, no breaks and was completed in less than 5 minutes. I think you will find the video informative so please watch [...]

Complex SoC Prototyping using Xilinx Virtex-7 based HAPS-70 Systems

At the recent SNUG UK Paul Robertson from Broadcom presented a paper on their use of FPGA-Based Prototyping for their current generation of SoC’s. For those with Synopsys SolvNet access the paper can be found by following this link: http://www.synopsys.com/Community/SNUG/UK/Pages/Abstracts.aspx?loc=UK&locy=2013#C1 Based on participant votes Paul was awarded with the prestigious “Best of SNUG” award. Congratulations [...]

Understanding IP and IP to SoC Prototyping

I’m presenting at the quarterly GSA Intellectual Property (IP) Working Group Meeting this morning and while reviewing my slides I thought I would blog on a couple of aspects of IP (RTL blocks) and IP to SoC Prototyping. I’ve blogged on this topic before but it was ages ago and even I’ve forgotten what I spoke [...]

Do you use a hammer to put in a screw?

This week I was asked to compare the Synopsys HAPS systems to FPGA vendor evaluation boards. I only have good things to say about the FPGA vendor evaluation boards but when comparing these evaluation boards to HAPS for serious FPGA-Based Prototyping I just said, “That’s like using a hammer to put in a screw”. A [...]

Designing an Electrochemical Cell

A couple of folks complained that my last blogs have been a bit long and boring. (Boring! Me?) So I would like to start this week and apologize to all my 5th Grade readers, I’ll try harder in the future to use smaller words and more pictures. The good news is that this week is [...]

Accelerating Prototyping Hardware Assembly

This week I wanted to focus on a discussion around prototyping hardware assembly. Prototype hardware assembly is the process to tailor FPGA-prototyping hardware to meet the needs of the project. The first type of prototype assembly would be to build a custom platform directly matching the projects requirements. The building of prototyping hardware is the [...]

Xilinx FPGA’s for FPGA-Based Prototyping

If we look at the FPMM survey respondent data it’s clear to see that the favored FPGA device for FPGA-based prototyping is Xilinx devices This week Xilinx announced the Virtex® UltraScale™ VU440 3D IC. http://press.xilinx.com/2013-12-10-Xilinx-Doubles-Industrys-Highest-Capacity-Device-to-4-4M-Logic-Cells-Delivering-Density-Advantage-that-is-a-Full-Generation-Ahead This is the device that Xilinx wants the future generation of FPGA-based prototyping hardware to make use of. Rather than [...]

Tear down of the new HAPS-DX FPGA-based prototyping system

I’ve talked about streamlining IP to SoC prototyping and the use modes that prototypers use for IP validation. This week Synopsys announced the new HAPS Developer eXpress (HAPS-DX) prototyping system. This new HAPS-DX system is perfect for complex IP and subsystem prototyping and ties in nicely with the flow that I have been blogging about [...]


Posted in Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Technical, Tips and Traps | Comments Off

Accelerating Prototyping Hardware Assembly

Posted by Michael Posner on 23rd November 2013

This week I wanted to focus on a discussion around prototyping hardware assembly.

Prototype hardware assembly is the process to tailor FPGA-prototyping hardware to meet the needs of the project. The first type of prototype assembly would be to build a custom platform directly matching the projects requirements. The building of prototyping hardware is the alternative to buying an off-the-shelf solution. The advantage of building the hardware is that you can tailor it to exactly meet the projects requirements. The disadvantage is this process is time consuming due to the long development timeline and bring-up debug process. I’ve also run into many customers who got burnt at the last minute when marketing made a last minute spec change which the custom platform does not support. Whoops, back to square one to do a frantic redesign which typically results in project delays

This is why off-the-shelf prototyping hardware is so popular. Off-the-shelf prototyping hardware, like HAPS, offers the stability of a pre-designed and validated platform but has the disadvantage of requiring the user to tailor the platform to meet the project’s needs. Some hardware vendors offers interfaces such as Ethernet directly on the prototyping board. The problem with fixed interfaces is that if the project needs them great, if the project does not then the hardware is just wasting IO resources which could be used for other purposes. HAPS is a generic reusable platform which you tailor to meet the needs of the project. There are lots of off-the-shelf daughter boards for this purpose such as DDR3, SRAM, PCIe, Ethernet, SATA, Flash, Lab. However it’s impossible for Synopsys to design and build all types of daughter boards to meet every projects need (but we try hard to). While in Japan last week I visited the Embedded Technology (ET) show in Yokahama and met with a company called Gigafirm. Gigafirm (http://www.gigafirm.com/)  has designed a set of HAPS daughter boards supporting the HAPS-70 series of products delivering daughter board support for V-by-One and embedded DisplayPort (eDP)

Above you can see Gigafirms daughter boards installed on a HAPS-70 S24 platform, the HAPS system with two Virtex-7 2000T devices. V-by-One and eDP are used for image and video designs of which there are many design starts at Japanese based customers.The V-By-One Hapstrak 3 (HT3) daughter board enables the THine (http://www3.thine.co.jp)

V-By-One evaluation boards to be connected directly the HAPS platform and supports both RX and TX capabilities.

The eDP daughter boards are designed for the HAPS Multi-Gigabit (MGB) connector interface. These high speed daughter boards enable both RX and TX eDP capabilities on the HAPS-70 systems.

I was very impressed with the quality of the Gigafirm deliverables. Gigafrm is helping customers accelerate prototype assembly by providing off-the-shelf high quality daughter boards enabling the HAPS systems to be tailored to meet the designs validation needs.

While at ET in Japan I also say the Fujitsu evaluation and development platform showcase connection to the HAPS-70

The Fujitsu development platform enables customers to evaluate the Fujitsu products and jump starts their software development tasks. The Fujitsu platform interfaces to the HAPS system via a transparent PCIe interface. The connection to HAPS enables customers to extend the platform with the capacity to model their own design blocks and validate them operating against the Fujitsu subsystem.

The Fujitsu evaluation platform is called the Phoenix. What a great name IMO.

It’s great to see the eco-system that has built up around the HAPS FPGA-based prototyping solution.

Finally, thanks to everyone who sent me a note about my allergic reaction that I suffered last week. The good news is that since that time I have only suffered a single smaller reaction which resulted in a fat lip and swollen cheek. I have not pin-pointed what is triggering the reaction but by the process of elimination I am narrowing down the suspect foods.

Posted in Debug, FPGA-Based Prototyping, In-System Software Validation, Project management | Comments Off

Prototyping Cutting Edge Standards – 10G USB 3.1 Host and Device

Posted by Michael Posner on 8th November 2013

As we all know FPGA-based prototyping enables early software development, HW/SW integration and system validation but did you also know that HAPS FPGA-based prototyping is also designed to make Eric Huang, PMM for USB IP at Synopsys famous? I’ll be honest, when we designed the HAPS-70 systems we did not highlight this as part of the MRD which shows that sometimes capabilities evolve on their own.

The HAPS-70 is making Eric famous as it’s being used by his R&D team to validate and demonstrate the new 10G USB 3.1 standard. Eric recently published a video documenting the first platform to platform demonstration of 10G USB 3.1 and it’s powered by HAPS-70’s. (Eric-Hollywood-Huang we call him in the office now). There are some very pretty models in the video, HAPS-70 based prototyping models that is. The HAPS-70′s are the real star’s of this video :)

Eric and his R&D team have been working on 10G USB 3.1 for a while now and a couple of weeks back I cornered Eric in the lab to quiz him on the HAPS-70 usage. The HAPS-70 FPGA-base prototyping solution enabled this team to rapidly develop a validation platform and enabled this demonstration. I’ve mention this before but FPGA-based prototyping is the single best way to wow a customer with functionality implemented in hardware giving the demonstration high credibility.

The Synopsys DesignWare USB R&D team (the stars behind the scenes) were able to prototype both the 10G USB 3.1 Host and 10G USB 3.1 Device using the HAPS-70 platforms. The flexibility and capabilities of the HAPS-70 enables the USB R&D to quickly customize the platforms to meet the designs needs. One of the key parts of the development was a way to connect the two separate platforms together using a standard USB cable while transmitting and receiving at the new higher 10G rates. For this the DesignWare USB R&D developed a custom HAPS Multi-GigaBit daughter boards, MGB for short.

HAPS has had an MGB interface implemented for a number of generations now and there are available off the shelf daughter boards for it such as PCIe, Ethernet and SATA. It’s a very well documented simple daughter board interface with reference designs and the DWC USB R&D team were able to develop this custom USB 3.1 MGB in about two weeks. Now that’s rapid prototyping.

In the 10G USB 3.1 demo you can see that the demonstration uses host machines to run the software that is executing on the USB 3.1 cores. The DesignWare USB 3.1 IP team use the PCIe connected IP validation mode. If you remember I blogged about this IP validation usage mode a couple of months back. The PCIe connection is also hosted via the MGB, this time using the off-the-shelf HAPS PCIe MGB. It can be seen in the picture below, it’s the thick cable sticking out of the HAPS-70 and then connected into the host via a host adapter card. This connection is an off-the-shelf offering for Synopsys so it’s easy to deploy in your designs as well.

I’m going to visit Eric next week and see if I can encroach on his stardom and get myself into one of his videos.

I can’t wait for 10G USB 3.1 to go mainstream. USB 2.0 was revolutionary at the time and USB 3.0 at 5Gb/s was a huge leap forward. Copying files which took minutes with USB 2.0 then took mere seconds with USB 3.0. But then the files got bigger and the copy times started to increase. Hey presto… along comes 10G USB 3.1 to the rescue, yay. Super fast copy, sweet.

Posted in ASIC Verification, FPGA-Based Prototyping, In-System Software Validation, Tips and Traps | Comments Off

Do you have what it takes to be a prototyping super hero?

Posted by Michael Posner on 30th September 2013

I was recently talking to a customer who found that deploying FPGA-based prototyping was a challenge. This was a customer who had only every done simulation for verification purposes. Their last chip incorporated dual embedded processors and unfortunately they had to re-spin the silicon due to a hardware bug that they found only when running the real software. This bug was devastating, the cost was huge as it included the physical costs of the re-spin but worst was the revenue hit from being late to market. This company knew it had to adopt FPGA-Based Prototyping to enable early software development, HW/SW integration and System Validation all PRE-SILICON. The goal was to run the actual software against the hardware and identify HW/SW bugs before code freeze and tape-out.

The process to bring up a prototype was not smooth, they made a couple of key mistakes which I will share with you in an effort to help you avoid these in the future.

#1 – ASIC Code is not FPGA friendly
This is #1 rule from the FPGA-based Prototyping methodology Manual. Their code was full of ASIC specific instances that challenged the initial bring up. One of the problems was that the customer *thought* they could use the FPGA vendor tools for the synthesis. While the FPGA vendors tools seem attractive as they are close to free they do not offer any in-depth prototyping capabilities such as gated clock conversion, DesignWare support and ASIC block conversion. The customer is now looking at utilizing the Synopsys prototyping software tools that provide these capabilities in addition to offering many automated multi-FPGA prototyping capabilities.

#2 Wasted time developing in-house FPGA Boards
The customer thought that as they can design multi-million ASIC gate SoC’s of course they can design a PCB with a couple of FPGA’s on it. Sadly this choice delayed the start of the prototyping project as developing a PCB like this and managing clocking, configuration and debug is not as easy as it seems. The customer spun the PCB twice before getting a platform which provided basic function. After all this the platform stilled lacked specific debug capabilities which limited the customers productivity. The customer will not make this mistake again and is looking to deploy a commercially available FPGA-based prototyping system such as HAPS for their next project.

#3 Tried to bring up the whole SoC prototype at once
Classic mistake. The funny thing is that within simulation the customer brings up individual design blocks and only when each has past it’s hello world and basic functionality tests does it get integrated into a larger SoC verification environment. This is exactly the same as what you should be doing for FPGA-based prototyping. Bring up individual blocks and only when they are operational do you instantiate them into the SoC level. This way you are not debugging multiple issues at once that everybody knows is a very time consuming process.

The customer made other mistakes but the above ones were the worst offenders. In general the customer lacked FPGA expertise and could have really benefited from expert assistance. This is exactly where Synopsys can help, we offer expert services, expert support and expert local application experts.

The one thing that this customer stated that I 100% agree with was that it will be easier the 2nd time around. Exactly, they have built up internal expertise and plan on utilizing available products to improve the flow and the designers productivity. What the customer wishes they had done was to involve Synopsys from the start and utilized our services team to provide FPGA-based prototyping assistance at the start of the project. This would have jump started their effort. By using the Synopsys prototyping software and HAPS system the customer would not have wasted valuable time in creating a flow and designing and debugging hardware. The bonus to using the Synopsys tools and hardware is that the customer could have leveraged the extensive support infrastructure of Synopsys FPGA R&D and CAE experts as well as the globally located Application Consultant experts. Synopsys, the home of the Prototyping Super hero’s :)

Don’t make the same mistake as this customer!

Did your company have a similar experience, let me know about it.

Below is my favorite spam message of the week. Spammers, work out what the blog is talking about before bothering to spam it. Hot tubs, come on, that has nothing to do with FPGA-based prototypes. And nobody wants a “used” hot tub, that’s just gross….

Posted in ASIC Verification, Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Project management, Technical, Tips and Traps | Comments Off

Mind The Gap

Posted by Michael Posner on 13th September 2013

Over the last two weeks I’ve been traveling in China and Taiwan talking to FPGA-Based Prototyping users at the two Synopsys User Group, SNUG, events. FPGA-based prototypes in these regions are used to validate all types of designs from smaller RTL blocks to video cores and mobile application processors. The engineers face the same challenges as engineers in the rest of the world, mainly in the area of converting ASIC RTL to FPGA images.

This is what the Great Wall Of China looks like over a busy weekend…..

I was a little surprised to find so many engineers manually converting gated clocks for example rather than using vendor tools such as Synopsys’ Certify which do this automatically. After understanding which tools were used it was not a surprise to hear the complaint that the synthesis for the huge FPGA devices such as the Xilinx Virtex-7 2000T takes a very long time. Almost all the engineers use the FPGA vendor tools which do a great job but lack key capabilities targeted at FPGA-based prototypers. The engineers found it hard to believe that there are tools available to not only do automated gated clock conversion but also include “fast” prototyping modes reducing the time to operational prototype. This is why I titled this blog, mind the gap, as I felt that there was a knowledge gap. The engineers were very intelligent but lacked the industry knowledge of what tools were available to them. I am sure it will not be long before these engineers expand and make better use of the tools as their disposal.

At the SNUG events we took the opportunity to show and tell the HAPS-70 systems. Below is a picture from SNUG Taiwan of me holding the HAPS-70 S48, our 48 million ASIC gate capacity system.

Yes, business travel is hard work but someone has to do it……

We were also demonstrating the Embedded Vision Development System. For more information on this solution and a video click this link. http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/Pages/Videos.aspx

The demonstration was running live on a HAPS-62 system. The demo design operates at close to real speed and it was pretty cool to see the live images.

A webcam is used to capture video which is streamed onto the HAPS-62 where the Application Specific Processor created by Synopsys’ Processor Designer operates on the image. The mode above was some outline capture function. Of course now I see my outline it highlights just how big my ears are, why did no one tell me this !!!

Posted in ASIC Verification, FPGA-Based Prototyping, In-System Software Validation | Comments Off

Standalone Validation & the Wow Factor of Turbo Antilag

Posted by Michael Posner on 24th July 2013

Continuing on my theme of RTL Block/IP validation I wanted to discuss the most popular and typically the most well understood usage mode, Standalone.

The characteristics of a setup with define usage as standalone is well….. it’s standalone…… In a typical standalone setup the DUT is being stimulated by real world input and it’s generating some type of real world output. A good example of a standalone prototyping setup is the DesignWare MIPI demo of CSI/DSI. (Video: http://www.synopsys.com/dw/ipdir.php?ds=mipi_csi2 ) The real world input is a MIP camera and the real world output is a MIPI compliant display. The design under test in this case is both the DesignWare CSI and DSI digital controllers implemented on the HAPS FPGA. The DesignWare DPHY is being validated as part of this setup as well as they are utilized to facilitate the physical electrical interface with the test chips mounted on HAPS daughter boards.

Within the standalone setup a processor may or may not be used depending on the DUT. In many cases a processor is implemented as part of the prototype that controls the configuration of the DUT. In the case of the above example I remember that a processor is used which executes a light software layer enabling software control of the IP’s dynamic configurations. The code is controlled and debugged via a simple JTAG connection.

The DUT is being immersed in real world stimuli identical to how it would be when utilized in a full SoC design. This is why it’s validation! you confirm that the DUT does what it’s supposed to do and that it meets user requirements. In the case of our example video in and video out, you see the results.

A requirement of a standalone prototype platform like this is that it has to be high performance to support the real world interfaces which typically have minimum clock frequencies.

The standalone setup can be used for HW validation in addition to HW/SW integration and or course as a platform for continued SW development. These usage modes make the standalone prototype highly useful across hardware, software and system design teams. This is why the standalone use mode is by far the most popular and well understood usage mode.

Next week I’ll discuss the PCIe connected modes and introduce the “Loop Concept” exciting right!

And for those of you who only read my blog for the “non” FPGA stuff here is a link to a video of me having a little fun at The Ridge Motorsports Park in my 450 WHP Subaru: http://www.youtube.com/watch?v=1Cn79GSTfXc (This was why last weeks blog update was on Thursday, I was doing this on the Friday) You will have to take my word on it that in fact it’s more fun to do than watch on video. Here is another video from a while back of me tuning what is known as the “Turbo Anti-lag” system on my Subaru: http://www.youtube.com/watch?v=Ppv3EMGlITY  

I don’t use the antilag system very much as it’s pretty hard on the engine components but when I do it certainly brings a smile to my face and shock and awe to onlookers. Fast n Furious yo….

Posted in ASIC Verification, FPGA-Based Prototyping, Getting Started, Humor, In-System Software Validation, Technical, Tips and Traps | Comments Off