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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'ASIC Verification' Category

Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

Posted by Michael Posner on 29th April 2016

I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)

The new release includes capabilities which reduce the time to first prototype even more than we do today, greater design visibility with new and automated debug features, automated performance boosting methods and many more like support for UPF 2.1 as blogged about a while back.

The two capabilities which caught my eye were the new HAPS Global State Visibility and the performance improving HAPS Timing Aware System Route.

HAPS Global State Visibibility

HAPS Global State Visibility, HAPS GSV, delivers a method to capture all register values in a non-intrusive fashion, meaning no instrumentation needed. This is an on-demand design visibility capability which is incredibly valuable to help debug issues immediately. Even better, you are not debugging complex FPGA specific register names, the HAPS ProtoCompiler flow maps the data back into the original RTL golden source namespace. So cool.

HAPS Timing Aware System Route

One of the other capabilities which impressed me (well done R&D), is the enhanced HAPS timing aware system route. The HAPS system route phase automatically selects the optimal multiplexing (HSTDM) ratios based on the over design and specific path’s slack. In most cases this new level of automation is delivering ~10% increase in the HAPS prototypes performance.

Look out for a new blog starting soon: https://blogs.synopsys.com/hittingthemark/

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Posted in ASIC Verification, Bug Hunting, Debug, FPGA-Based Prototyping, HAPS-70, HAPS-80, Man Hours Savings, Performance Optimization, Real Time Prototyping, Tips and Traps, UltraScale | No Comments »

Verifying Power Management Modes, both Software and Hardware

Posted by Michael Posner on 14th April 2016

Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!”

Raspberry PI image

BTW: This blog was inspired by a true story of a challenge that Achim Nohl, Technical Marketing Manager for HAPS Physical Prototyping recently experienced: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=51543

Power management is an increasingly complex function provided by hardware and controlled by a large extent by software. The software is orchestrating the power-up and power-down sequence of the SoC’s subsystems and peripherals in various scenarios such as cold boot, warm boot, resume, hibernate etc. These scenarios involve multiple software layers such as firmware, boot loader, operations system and user space software. The interaction between those layers, which often reside in different privilege modes (aka exception levels), is complex and prone to errors due to the variety of scenarios, conditions and distributed ownership of the software modules in different teams and 3rd party or open source.

Testing this software power management prior to silicon is a huge concern but, the same concern is with the hardware designers as it’s the software that controls most of the hardware operation. The complexity of software power management is mirrored in the hardware through complex clock-/power-management units, a growing number of power domains and the required logic for retention and isolation functions. While the power-off sequence in software is a coarse grain level for the power domains, the power gating (PG) sequence in hardware is a complex fine grain control of isolation, retention, voltage and clocking. Before a power domain can be powered off after shutting down the clock, the outputs need to be isolated to prevent floating signals to propagate to neutral power domains. Certain flops may need to keep their state during power gating using retention cells after isolation has happened. Only then, the voltage VDD can be safely removed, keeping the lower retention voltage VSS, which levels have been programmed via software using a PMIC (Power Management IC). A lot can go wrong here and a flaw may just be exposed under very specific conditions during field operation. That is why we are seeing so many answers like this in user forums. “It Works!! Disabling the power management of my Wifi chipset solved my instability problem”. Whoops, a bug got through somewhere, could be software, could be hardware but we don’t know for sure. What we do know is that the bug only showed itself when power management is active.

In order to address the important and urgent need to verify and validate hardware and software power management functions prior to silicon designers have turned to physical prototyping. The power management software can be executed against the power management hardware before you commit to silicon. Of course you can only do this if your physical prototyping solution supports modeling of the power management hardware. The HAPS physical prototyping solution enables support for those power management use-cases. Compared to traditional FPGA synthesis targeting FPGA as the final product, HAPS ProtoCompiler is able to understand the hardware power intent from UPF (Universal Power Format) specification and translate this into the required logic for prototyping power management. UPF is the IEEE standard for describing the power supplies, power states, retention etc. and separated from the RTL description of the design.

Low power intent view in ASIC

Typically, this is not something you are concerned as an FPGA implementer and that is why synthesis tools for FPGA implementation do not support it and provide power management solutions very different than the ones for ASIC implementation. Since HAPS ProtoCompiler has a different objective, which is the validation of ASIC hardware and software under real world conditions, UPF is an integral part of the HAPS prototyping flow. For this purpose HAPS ProtoCompiler goes beyond translating UPF into a neltlist for the FPGA and enables new techniques which allow more and targeted testing of power management functions. Fro example the flow enables the isolation and retention logic to be prototyped, in addition, dedicated capabilities enable corruption of sequential elements when the power domain is shut off to better reflect what the final SoC would experience. This way, HAPS ProtoCompiler increases the test coverage for the crucial isolation and retention logic.

Low power modes modeled through ProtoCompiler for HAPS

Not testing power management software and hardware is risky as it leaves a gap in the pre-silicon validation. HAPS with HAPS ProtoCompiler enables power management capabilities to be verified based on a standard UPF flow.

Look out for a new blog starting soon: https://blogs.synopsys.com/hittingthemark/ This blog will discuss both Virtual and FPGA-based Prototyping

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation, UltraScale, UPF, Use Modes | No Comments »

It’s not too late to attend SNUG Silicon valley

Posted by Michael Posner on 28th March 2016

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

Prototyping topics:

  • Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System
  • FPGA Debug: Improving Debug Turnaround Time in High Speed Designs
  • Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution
  • Adapt, Port, and Integrate Quickly – Prototyping the Right Way
  • Address TTM by Prototyping and Validating SoC Design Using HAPS-70 System
  • Reduce Overall TAT and Increase System Performance of Prototype Using ProtoCompiler

Many of these are user presentations so not to be missed.

More details here: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/Documents/snug-sv-2016-schedule3.pdf

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes | 1 Comment »

What’s in it for me? The market shift to integrated Physical Prototyping

Posted by Michael Posner on 11th March 2016

What's in it for me

FPGA-based physical prototyping is the go-to standard for high-performance, high-productivity verification, debug, and software development on many electronic systems today. But, it is becoming increasingly difficult to put together an ad-hoc prototype mixing pieces from various vendors with home-grown components. With the complexity of today’s systems, an integrated prototyping system can bring significant advantages.

Learn about these advantages (the answer to the question “what’s in it for me”) in this Electronic Engineering Journal chalk talk http://www.eejournal.com/index.php?cID=35861 hosted by Amelia Dalton.

EE Journal

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Over the last weekend I coached teens how to handle unpredictable and potentially dangerous driving situations. You can find a short story on the Tire Rack Street Survival School here: http://www.kgw.com/news/local/street-survival-school-helps-teens-become-better-drivers/70835667 At the end of the clip you will see a silver car pass behind the person being interviewed, that was one of my students and I’m in the passenger seat.

The primary emphasis of the Tire Rack Street Survival is a “hands-on” driving experience in real-world situations! We use your own car to teach you about its handling limits and how you can control them. The students will become more observant of the traffic situation they find themselves in. They will learn to look far enough ahead to anticipate unwise actions of other drivers. As the students master the application of physics to drive their cars, they will make fewer unwise driving actions themselves. They will understand why they should always wear their own seatbelts, and why they should insist that their passengers wear seatbelts, too.

I enjoy volunteering for this school as I hope that the skills the teens learn could help save their lives in the future. It’s about more than driving – it’s about LIVING!

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off

Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Posted by Michael Posner on 4th March 2016

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

A recent web seminar presented the various debug scenarios and maps which debug capabilities to use for the particular scenario.

HAPS Debug Visibility Web Seminar

https://webinar.techonline.com/1674?keycode=CAA1BC&cmp=WEBR-fpgabp100503-HPW

I highly recommend you take the time and watch the seminar as it covers not only the traditional physical prototype debug capability but also introduces the new capabilities such as HAPS Deep Trace Debug, the ability to capture huge amounts of debug data as well as HAPS Global State Visibility. Global State Visibility has always been seen as the Holy Grail of FPGA-based prototyping, the ability to trace the state of all design registers, dynamically, without the need to pre-define of instrument.

HAPS & ProtoCompiler Debug Visibility Solutions

The web seminar also includes a mention of utilizing the other capabilities such as HAPS Real Time Debug enabling a debug connection to a Logic Analyzer and cross triggering to aid in HW/SW debug.

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Do you think that the wireless megatrend, data transfer and charging will replace wired USB? Read this: https://blogs.synopsys.com/tousbornottousb/2016/02/26/will-wireless-data-charging-replace-usb/ and post your views.

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale | 2 Comments »

Q&A Using FPGA Prototypes for Software Development & More

Posted by Michael Posner on 26th February 2016

Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.

http://electronicdesign.com/fpgas/qa-using-fpga-prototypes-software-development

Click here for the full article

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off

What to use first, Emulation or Physical Prototype?

Posted by Michael Posner on 19th February 2016

I ran into the article below titled Emulation vs. Prototyping.

http://www.eetimes.com/author.asp?section_id=36&doc_id=1328736

This article ALMOST got it right (IMO), but not quite. Firstly it should not be “vs.”, the two technologies are complementary and typically used side by side so it should be “&”. Secondly, with todays challenges the trend is that engineering teams start with Prototyping, not Emulation. Here I am not talking about Virtual Prototyping which we all know is designed for very early in the project usage, I am talking about FPGA-based Physical Prototyping.

HAPS-80 with HAPS ProtoCompiler production systems in the lab, picture angle 2

The reason is that early SW development is so important and in addition you need to quickly thrash out system level issues. The only way to capture these issues is to run the software, typically an OS, against the hardware and you want to enable a mass of software engineers with these models. Physical Prototyping with a product such as HAPS enables this. There was a SNUG customer presentation by Realtek in Taiwan on this very subject:

http://www.synopsys.com/Community/SNUG/pages/proceedingLp.aspx?loc=Taiwan&locy=2015 Look for TA5.2 Earliest SW/HW Co-Development for Complex SoCs Using ProtoCompiler Enabled FPGA Prototyping Platforms

The presentation presents the use of HAPS ProtoCompiler with HAPS systems to enable early software development and hardware verification.

Remember you still bring up emulation to debug the HW issues that cannot be resolved with pure prototyping.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development | Comments Off

Validating USB Type-C using Physical Prototyping

Posted by Michael Posner on 29th January 2016

USB Type-C Connector

This week Synopsys Introduced the DesignWare USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection. USB has been continually evolving and USB Type-C is the one cable to connect them all. The USB Type-C is already gaining widespread acceptance and is becoming the most rapidly adopted USB standard in history. The need to rapidly adopt a new standard comes with challenges for the design engineers, verification team and the software developers.

Synopsys has solved the challenges for these three groups. The DesignWare IP solution is fully validated and ready to integrate into your design. The digital controller is validated against the analog PHY portion significantly reducing integration risk. Engineers can reduce the time and effort of integrating the IP into SoCs utilizing the DesignWare USB-C 3.1/DisplayPort 1.3 IP subsystems, IP prototyping kits and IP software development kits supported as part of the IP Accelerated initiative. Design engineers, verification engineers and software developers challenges solved!

Physical Prototyping with HAPS and HAPS ProtoCompiler plays a key part in this validation. The HAPS solution is used as the hardware verification platform of choice for the DesignWare IP development team. The HAPS systems are used as the operation platform as part of USB certification. Below you can see the HAPS-DX IP development platform being used as part of USB Type-C certification.

DesignWare USB Type-C compliance testing on HAPS-DX

Below is a close up of the USB Type-C connector.

HAPS USB Type-C daughter board

This highlights one of the key benefits of the HAPS systems, they are highly flexible, modular and can be rapidly adapted using daughter boards to support the latest and greatest interface needs.

Want to know more about USB Type-C? Just pop over to the “To USB or not to USB” blog. Have a look at the right hand side of the page, you might find something that surprises you.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, IP Validation, Man Hours Savings, Project management, System Validation, Use Modes | Comments Off

Prototyping Low Power Functions Using UPF

Posted by Michael Posner on 19th December 2015

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

UPF (IEEE 1801-2009 ― Unified Power Format) is the industry standard for design and verification of low power integrated circuits. As noted above, these low power modes are a mix of hardware capabilities under software control and to verify the operation the two must be run together which poses a challenge for the verification and software engineers. Physical, FPGA-based prototyping would seem like the logical solution to this problem as you are running a high performance, cycle accurate model of the design against the real software. But there is a problem, FPGA’s are not ASIC’s .

FPGA’s are volatile

  • No power islands or partial turn off
  • Configuration file loaded from external memory

Multi-voltage cells are not present

  • Only user configurable cells

A single power and single ground

  • VCC, GND for user mapping

Click picture for full size render.

Low power intent view in ASIC

But will you cannot test the exact power domain capabilities of your design there are still many capabilities which can be modeled in the Physical Prototype which will result in higher test coverage of the designs low power capabilities. To make this process easy the Synopsys ProtoCompiler tool can read your UPF and implement a number of lower power capabilities as part of the HAPS physical prototype. This enables the software that controls these lower power modes to be more fully verified pre-silicon.

Some of the key low power capabilities which can be inferred directly from the UPF through the ProtoCompiler for HAPS flow are:-

Verify/validate logical of the islands and control manager

  • Isolation behavior
  • Retention behavior
  • Power Management Unit (PMU) connections and control

Click picture for full size render

Low power modes modeled through ProtoCompiler for HAPS

With this low power logic modeled in HAPS the design’s low power modes can be more extensively tested. The isolation and retention behavior is a mix of hardware functions controlled by software which can now both be tested together. ProtoCompiler’s implementation of the UPF directives modeled in the HAPS systems the designs inferred low power modes enables the hardware and software engineers to expand the low power mode verification resulting in lower rick risk of post-silicon issues.

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I’m taking a personal break over this holiday period so no blog for a couple of weeks. I would hope that no one is around or bored enough to want to read this blog over the break period anyway so no one will really notice.

I grew a beard for the winter break, (see below) not because I’m hip and trendy but because I like to ski/snowboard/mountain climb during the break and a beard protects your face from the wind. I’ll shave it off in January and then post a comparison picture. I like a beard for the technical reasons listed but I really don’t think it suits me.

Mick grew a beard

Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes | Comments Off

Customer experiences with ProtoCompiler for HAPS

Posted by Michael Posner on 4th September 2015

Censorship is ............

Last week I posted some anonymous results from ProtoCompiler for HAPS usage on real customer designs. While I had removed the customer names and replace them with names like, consumer electronics company, which in my opinion could have implied hundreds of different HAPS customers across the globe, the greater powers in Synopsys felt the data was still too close to the customer. I should point out that Synopsys treats customer information with the highest confidentiality and I personally did not think any confidential information was being shared. I pulled the data off my blog. Anyway, this is the first and I hope last time that Synopsys has to step in and censor my blog.

So just in case you missed the data the first time around, here it is again, this time just the data points. These two examples are from existing HAPS and Certify users and I define both customers as experienced in FPGA-based prototyping. Results of ProtoCompiler run on their designs.

I can't tell you who this customer was

This first case you can see that ProtoCompiler identified a partition solution in an automated fashion which resulted in a more optimized prototype. In this case shrinking the design from three FPGA’s to two. It’s typically understood that as you consolidate a design into less FPGA’s you can achieve higher performance. The customer will realize the effect of this performance with a reduction in test runtime.

Now the second case below is an example of how ProtoCompiler can be used again to identify more optimum prototype. In this case the solution was not to shrink the design into less FPGA’s but to partition the design at other points in the design spreading it out to four FPGA’s vs. the original three FPGA version. ProtoCompiler was able to utilize HSTDM, high speed pin-multiplexing to improve the overall system performance. A byproduct of the new partition was that compile, synthesis and Xilinx place and route times were halved.

Different customer but I still can't tell you who this is either

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I’ve been dropping “easter eggs” all through my blogs for the last couple of months. If you noticed them drop me a note or comment below on where you found the easter egg. If you don’t know what the term easter egg is then look here: https://en.wikipedia.org/wiki/Easter_egg_(media)

Posted in ASIC Verification, Early Software Development, In-System Software Validation, Man Hours Savings, Performance Optimization, Project management | Comments Off