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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'ASIC Verification' Category

HOW TO: Achieve Fastest Time to Operational Prototype and Highest Performance

Posted by Michael Posner on 24th July 2014

Road runner the bird, not the cartoon

If you didn’t know the above picture is of the greater roadrunner (Geococcyx californianus). Trust me I didn’t just make up the Latin name. The Latin name means “Californian earth-cuckoo”. This blog is about how to achieve the fastest time to operational prototype, accelerating ASIC and SoC verification, speeding validation and the road runner was first image that popped into my mind when I wanted to articulate fast. There has been a lot of talk about Time To First Prototype, TTFP, recently so I thought I would blog a how to on achieving accelerated TTFP. I thought I’d raise the bar and deliver a how to on both achieving this AND get the highest operational performance out of the FPGA-based prototype.

If you have found yourself reading this blog you are looking for the magic solution but I am afraid I have to burst your bubble, there is no black magic solving this problem.

Home made no back magic logo

It’s better, all you need is a fully integrated FPGA-based prototyping solution. Yep, that simple, blog done, thank you :) (What? You want to know why an integrated solution solves all your problems!) To answer this we need to quickly review the challenges to FPGA-based prototyping. The below picture describes the challenges to prototyping, based on a recent survey that Synopsys ran. It also includes on the left the solutions to these individual challenges.

Click on the images to view the whole picture. I made them large so they were easy to read.

Survey results defining the challenges of FPGA-based Prototyping and the combined HW/SW capabilities needed to solve them

Do you spot the common theme? The challenges cannot be solved with hardware or software alone, it’s the combination that solves the problem. An example is performance, I’ve blogged about this is the past that it’s the combination of hardware interconnect flexibility and the ability to deploy a high speed time domain, differential signaling, solution that is the key to achieving the highest performance. In this case the software has to have intimate knowledge of the hardware, it’s electrical and SI characteristics to be able to correctly implement the high speed time domain IP in the multi-FPGA prototype design. At the same time ALL hardware must meet a minimum level of performance across all interconnections to ensure that when the prototype design image is deployed across many systems it always runs reliably.

Summary examples of what integrated capabilities are of the Synopsys solution

Debug is another good example. To deliver the highest debug visibility you need both a software flow that enables instrumentation of the RTL, graphical display AND hardware capabilities to store the physical data. The result of integration reduces your need for expertise as the solution has the expertise. Same for partitioning across multiple FPGA’s, as the software is hardware aware and the hardware can be tailored to the software recommended best interconnect topology the result is optimal.

Lucky for you, Synopsys delivers a fully integrated solution of ProtoCompiler plus HAPS so you don’t have to wait. And… if you call now, not in 5 minutes but now, I’ll personally visit your site to say hello.

Synopsys' integrated FPGA-based prototyping solution including ProtoCompiler software, HAPS FPGA-based hardware, debug, DesignWare IP, Support, HAPS Connect Program

While ProtoCompiler was only recently launched its delivering some fantastic customer results, see below, accelerating time to first prototype and delivering the highest performance. This was a customer design, 48 Million ASIC gates, four Xilinx Virtex-7 FPGAs. ProtoCompiler is fully integrated with HAPS leveraging its strengths. HAPS interconnect can be tailored based on the ProtoCompiler recommendations and ProtoCompiler understands the HAPS architecture and resources such as clocks and resets. ProtoCompiler is built around a stable code base of Synopsys’ mature and unique compilation and synthesis engines delivering the highest QoR for out-of-the-box results.

Synopsys achieves fastest time to prototype and highest performance operation with ProtoCompiler plus HAPS

A fully integrated solution delivers not only accelerated time to first prototype and highest performance but also reduces your effort as it’s doing the hard work for you. Just don’t tell your boss otherwise he will give you more work.

Posted in ASIC Verification, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation | 1 Comment »

First Pass Silicon Success with design up and running in 24 hours!

Posted by Michael Posner on 16th May 2014

Achieving first pass silicon success is always the goal of the project. While a company may plan for a second chip spin they really want first pass silicon success enabling reduced cost and earlier time to market. I ran across this video featuring Peraso and Eric from the DesignWare USB team,  http://youtu.be/DyNyZP8Ysj4 . Now while Peraso do not claim first pass success bringing up a chip in the lab in 24 hours is amazing. Peraso used HAPS FPGA-based prototypes for system validation enabling them to test their software with their RTL implementation before they taped out. As you can tell from the video, Peraso were very, very happy with the fact that they had the silicon up and running in such a short period.

While we are on the subject of videos, here is another featuring the DesignWare HDMI IP and the HAPS-60 series systems. http://youtu.be/Ao-JeWz9g0A

These examples show the power of HAPS for reducing project risk, achieving first pass silicon success and exhibit high performance enabling the validation of very high speed real world interface.

Honestly I’m a little tired this week so I’m going to keep this blog short. A couple of weeks ago I did get the chance to take out one of the best off-road vehicles on the market. While I am used to far more horse power, this one horse power proved sufficient for the activity and we climbed some terrain that not many other modes of transport could reach. Unlike my other hobbies this trek was very relaxing. In addition I did not burn any fossil fuels in the process.

Do you want to meet me in person? Are you going to DAC? If the answer is yes to both drop me a comment and let me know and I’ll be happy to meet.

Posted in ASIC Verification, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, Milestones, Project management, Real Time Prototyping, System Validation | Comments Off

PCIe Gen 3 = 8Gb/s – Prototyping and Protocol expertise

Posted by Michael Posner on 2nd May 2014

This week I was asked to clarify what the PCIe Gen3 protocol speed is, to confirm, PCIe Gen3 speed is 8Gb/s per lane. PCIe Gen 1 is 2.5Gb/s and PCIe Gen2 is 5Gb/s. Yes I know I’m usually seen as the prototyping guy, (Or Mick “I’m not dead yet” Posner thanks to my pneumonia) but I also happen to double up as a protocol expert. One of the key advantages of FPGA-Based prototyping is the ability to model real world interfaces at speed so to be a prototyping expert you basically have to be a protocol expert as well. The above eye diagram (click image to view full size) is measured on the HAPS-70 (-2) speed grade systems running one of the many DesignWare PCIe Gen3 controller validation tests for interoperability and compliance testing. That is a good looking wide open eye!

I sneaked into the lab and snapped off this picture. (Click on image to view full size)

The little HAPS-70 S12 (-2) speed grade system is perched on top and that large black cable sticking out is the PCIe Gen3 capable cable connection. The cable plugs into a PCIe Gen3 host adapter board that in turn plugs into the host machine. In this specific setup I was told that we have the DesignWare PCIe Gen3 End Point controller modeled in a x4 lane configuration. Yes that’s x4 lanes of PCIe Gen3 so x4 lanes of 8Gb/s. I’m going to try and have the R&D engineer do a little video for me of the system in action as it was very impressive.

Oh, when using the Xilinx built in transceivers (Rocket IO) as the physical link the (-2) speed grade systems are required to model PCIe Gen3. The (-1) Xilinx Virtex-7 2000T devices only support up to 6.6 Gb/s while the (-2) support up to 10.3125 Gb/s thus supporting PCIe Gen3 speeds. Looking for PCIe Gen3 expert advice, go check out the Express Yourself blog

Off topic, spring has sprung in Oregon !! Yay, it was here for a whole 4 days and now we are expecting rain again. This is fine, this is what you expect and grow to love when living in Oregon. The mix of sun and rain makes everything really green, just look at how beautiful this little baby fern is. This is growing in my yard along with a huge amount of moss which is also typical across Oregon.

Click on image to view full size

Posted in ASIC Verification, FPGA-Based Prototyping, IP Validation, System Validation, Technical, Use Modes | Comments Off

Synopsys’ New ProtoCompiler Software Speeds Time to Prototype

Posted by Michael Posner on 28th April 2014


Synopsys just announced ProtoCompiler which is automation and debug software for HAPS FPGA-Based Prototyping Systems. ProtoCompiler is the result of years of R&D effort to generate a tool that addresses prototypers challenges today and built on top of an architecture which can support the needs of prototypers long into the future. ProtoCompiler focuses on the needs of prototypers specifically addressing the need for accelerated bring up as well as providing capabilities which result in higher system performance as compared to existing solutions. In this blog I’ll discuss some of the technical details behind the main tool highlights. Below are the detailed highlihts.

  • Integrated HAPS hardware and ProtoCompiler software accelerate time to prototype bring-up and improves prototype performance
  • Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs
  • Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance
  • Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility

(Read to the end of the blog if you also want an update on Mick’s Projects)

Highlight: Integrated HAPS hardware and ProtoCompiler software accelerate time to first prototype bring-up and improves prototype performance

As noted above the goal of ProtoCompiler is to accelerate the bring up of a prototype as well as providing a path to the fastest possible operating performance. ProtoCompiler is unique as it combines hardware/software expertise with intimate knowledge to deliver superior results. Think of it as delivering a HAPS hardware expert packaged up into a format that anyone using the tool can access. ProtoCompiler has deep technical knowledge of the HAPS hardware including configuration, clocking structures, interconnect architecture, pin multiplexing expertise and more. ProtoCompiler is not only a hardware expert, it’s also a software expert. ProtoCompiler is built on top of a state of the art Synopsys proprietary prototyping database that means RTL is effectively processed and incremental and multi-processing techniques can be deployed with ease.

All this results in blazingly fast processing speeds. As an example ProtoCompiler’s area estimation, essential for automated partitioning, can processed 36 Million ASIC gates in less than 4 hours as compared to 22 hours in existing solutions. Now that’s fast!. Thanks to the new data model and incremental modes all subsequent compiles are even quicker.

Highlight: Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs

So there are actually two announcements packaged up in this highlight. Starting in reverse ProtoCompiler supports 250 Million ASIC gate and larger designs. Humm, this sounds a little suspect as when HAPS-70 was launched it only supported 144 Million ASIC gates, what does ProtoCompiler know that we don’t? Luckily I know, HAPS-70 can now be scaled to support 288 Million ASIC gates, 2x the capacity. HAPS-70 now supports chaining of any six systems so if you chain six HAPS-70 S48’s you get a total of 288 Million ASIC gates supported which is 24 Xilinx Virtex-7 2000T FPGA’s. All working in one synchronous system.

Any 3 HAPS systems can be chained via our standard control and data exchange cabling, when you go above 3 systems you utilize a synchronization module that manages the system synchronization. Managing clock skew, reset distribution and configuration is all handled automatically. ProtoCompiler understands the hardware capabilities thus making deployment of such a system a snap. No longer do your engineers have to worry about how to distribute clocking, we have done the hard work so you don’t have to. Other vendors “claim” scalability and modularity but if all they are delivering is boards then it’s nothing more than a wild claim. To deploy a scalable and modular system you need a complete solution of software and hardware. You can now prototype SoC designs you thought never possible

The first part of the highlight introduces the new partition technology deployed in ProtoCompiler. ASIC’s are bigger than a single FPGA so you need to quickly partition the design across multiple FPGA’s. Historically this has been a challenge but with ProtoCompiler that challenge has been overcome. The partition engine in ProtoCompiler requires minimal setup before you can apply it to your design. There are four simple steps to setup the partition engine #1 Create target system, basically which system(s) you are compiling to. #2 Establish basic constraints which are things like blocks of IO. #3 Define the design clocks. #4 Propose an interconnect structure. Actually #4 can either be defined telling the partition engine to use a set interconnect architecture or leave it open and let the tool do it. There are advantages of both. By letting the tool pick the needed architecture the resulting system should be higher performance as ProtoCompiler will maximize interconnect to reduce pin multiplexing ratio. In a previously deployed system you may have already set the interconnect and then want the tool to use the available resources so you don’t make any changes to the hardware in the field. ProtoCompiler has the flexibility to do both meeting the needs of new prototype creation and image re-spin after a new RTL code drop.

ProtoCompiler partition engine is FAST, using the same example as above, 36 Million ASIC gates, ProtoCompiler was able to come to an automated solution is 4 minutes!!! WOW. ProtoCompiler provides a huge amount of information as to what it automatically did so that the engineer can quickly review the results and maybe provide ProtoCompiler more guidance to optimize the partition. For example after the first run you might want to lock down select parts of the design and then incrementally run the engine to push it to find a better solution for the rest of the design. As it runs so fast you can do multiple of these optimization iterations in a matter of hours. I’ve played with the tool as I was interested in this particular capability and have to say it’s amazing. I’ve tried the open method and let the tool find a solution for itself, in this mode ProtoCompiler pretty much finds a solution every time. I also played with challenging the tool for example locking the tool to use only 100 IO’s (two HT3 connectors) between FPGA’s. ProtoCompiler quickly finishes and told me that I was crazy and that the design could never be partitioned with my selected interconnect architecture.

Highlight: Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance

OK, this is simple, this basically says that ProtoCompiler can automatically deploy the HAPS High Speed Time-Domain Multiplexing (HSTDM). HSTDM is developed and optimized on HAPS and ProtoCompiler packages up this expertize and automated the deployment. The partition engine will automatically select HSTDM and instance it into the prototype design. HSTDM delivers high performance pin multiplexing between multiple FPGA’s. The signals are packaged up, sent across a high performance link and unpacked at the other side. This all happens within one system clock and is completely transparent to the user. No manual intervention, no additional latency, and it’s stable and reliable as HSTDM is tested as part f the HAPS production testing and every system has to pass the minimum HSTDM performance tests. This ensures that when you deploy am image with HSTDM that it runs on every system the image is loaded on. No need to tailor the pin multiplexing implementation for each board like you have to do with other vendors.

Highlight: Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility

ProtoCompiler expands the debug capabilities and grows the HAPS Deep Trace Debug capability which utilizes off-FPGA memory to store debug data. ProtoCompiler provides seamless multi-FPGA debug capabilities on top of a set of other debug capabilities tailored to delivering visibility at the right level of the debug cycle.

In debug one size does not fit all, you need to deploy the right level of debug visibility capability dependent on what you are trying to debug and the specific point you are in the project cycle. Sometimes you want very wide debug visibility with fast incremental turn-around. Later in the design cycle you typically want very, very deep debug windows. ProtoCompiler delivers both, fully automated through the flow, seamless and transparent to the users. And when I say deep, I mean deep, the example below is very typical of the debug window where you can easily capture seconds of debug data.

As usual my blogs got really long. I wrote it in the car while driving from Portland to Eugene. Amazing that I could type all of this and drive at the same time (LOL, only joking I was in the passenger seat)

Anyway, ProtoCompiler is the bees knees and I personally think it revolutionizes FPGA-based prototyping using HAPS. What do you think of ProtoCompiler?

If you have managed to get this far into my blog then congratulations. I’ve been taking it easy this week while I recover from the pneumonia that I came down with. In the evenings I finished off the two mini RC tracked vehicles I had been working on. The basis of both are simple kits which I then modified and added RC receivers and motor controllers to. While I am a grown adult I must admit they are fun to play with. The first is a basic platform RC tracked vehicle which I attached a Lego sheet to. Little did I know that this would be so popular with my son. He has been building towers and all types of structures on top of it.

Why drive your car to a car park when the car park can come to you. No joke that’s what my son said.

Mobile tire store

Bulldozer and sweeper

At the same time I also built a kit that has a shovel that moves on the front. Again I modified it to be radio controlled, including the shovel. This vehicle is a HUGE hit with my son and he has been busy building towers, knocking them down, then tidying them up with the shovel.

There are a couple of video’s of these little things in action on my You Tube page: https://www.youtube.com/user/MrMickPosner (and a video of my chicken food winch system)

Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Project management, System Validation, Technical | Comments Off

The Prototyping Rub from SNUG San Jose

Posted by Michael Posner on 27th March 2014


It was the Synopsys Users Group, SNUG in San Jose this week and on top of the Synopsys announcement on ICC 2.0 with the Powar (I know this is a typo but I enjoy saying the word like this, you try it Powarrrrrr) of 10x there was a whole track dedicated to FPGA-Based prototyping. Knowing that the whole world does not revolve around California I thought I would provide you with an overview of the days FPGA-base prototyping sessions. As a reminder if you have an active Synopsys SolvNet account you can download the session presentations and papers shortly after the event ends

The day started with : Automating SoC RTL to Operational Prototype – Synopsys R&D Presentation

This session delivered technical information on new Synopsys prototyping software that increases the level of automation and streamlines RTL to operational HAPS FPGA-based prototyping including ultrafast partitioning. I personally think this session might have been a little too technical (is there such a thing) as it jumped into how the software solved the problems but seemed to skip the explanation of the problem itself. Now for experienced prototypers they immediately saw the benefits being delivered but I think some of the more in-experienced prototypers were in over their heads. Even with this in mind I highly recommend this presentation. Using this software the user can see up to a 50% reduction in time to prototype, achieve on average 2X or more performance improvement in system performance and get greater debug visibility.

Next up: Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System – SanDisk use of HAPS-70 for an enterprise SSD SoC

Two words, killer presentation. I love seeing real users present their experience with FPGA-based prototyping systems. This presentation included the various steps that SanDisk used to bring up the HAPS-70 FPGA-based prototype of their enterprise SSD design and then optimize it for the highest system performance possible within the limitation of the SoC design constraints. It was very interesting and I recommend the presentation as it includes lots of great real world information on what it takes to create a full SoC FPGA-based prototype. The picture above was snuck off without anyone noticing (until now) pictures/videos within the sessions is prohibited. (whoops)

Final presentation of the day was: Putting IP and Subsystem Prototyping on the Fast Track – Synopsys Mick Posner (yes that’s me) and Antonio Costa from the DesignWare IP R&D team.

I came prepared with giveaway’s to bribe the audience for good feedback, we will have to wait and see if that worked. I introduced HAPS-DX for complex IP and Subsystem prototyping and tried to explain the various validation use modes and best practices for IP prototyping to streamline hand-off to the SoC team streamlining their prototyping efforts. I then handed over to Antonio who provided details on how the DesignWare IP R&D utilize the many generations of HAPS systems to validate the IP. I think the bits that resonated the best with the audience was Antonio’s explanation of the validation scenarios that could only be reached using FPGA-based prototyping. Antonio also introduced the IP R&D teams use of HAPS Deep Trace Debug to capture seconds of debug visibility enabling long protocol scenarios to be successfully debugged.

I highly recommend that you download these SNUG presentations on FPGA-based prototyping from SolvNet.

Progress on my latest garage project has been slowed by business travel and sickness. But I have made some progress and am happy to say that basic functionally has been validated.

If you can’t recognize what it is from this picture then let me tell you that it’s a custom designed remote control tracked vehicle with full suspension tracks. I designed the track runner system and this picture is of revision 2.0. It’s not perfect but it does the job and I can see a 3.0 revision to get better articulation. When finished I’ll take a little video if it in action, it’s a lot of fun. Here is a preview of the vehicle in action: https://www.youtube.com/watch?v=yF4uRSzL5qQ 

Some has asked me where I find time to do projects like this, the answer is I don’t find time but I manage to fit in a little here and there at the expense of other things like family time, house projects, eating…. I’m going to slow down on the project as family time, house projects and eating should really take priority.

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, IP Validation, Mick's Projects, System Validation, Use Modes | Comments Off

Prototyping wearables and the Internet of Things (IoT)

Posted by Michael Posner on 16th March 2014

Is this the future of wearable technology?

LOL, no…. well maybe…..

There are lots of questions on if wearables will bring the end of the Smartphone, I personally think these two technologies will co-exist. I like the idea of wearing my technology but there are many people that don’t thus there should be a place for both technologies for a while yet. Of course for anyone who travels a lot like me they will know that the airport security creates a new issue not previously encountered. I use a fitbit which is a small step tracker and I wear this on my trouser (pant) pocket. It pretty much lives in this spot and I’ve almost put it through the washing machine when I’ve forgotten to take it off. The problem is that this little device has become a part of my life and when going through airport security I’ve also forgotten to take it off which leads to an extra search pat down. A simple solution to this would be for me to remember to take it off but it would be nice if these devices are security certified of something like that.

When it comes to prototyping these deeply embedded SoC designs you will find out that while the form factor is small and simple the SoC designs are not. These designs are multi-million ASIC gates so when they are prototyped using FPGA’s the challenges of handling non-FPGA code, multi-FPGA partitioning and prototype assembly must be overcome. I visited a load of customers last week while traveling internationally and the common theme at the meetings was discussion around how to enable complex FPGA-based prototyping without the need for in-depth specific expertise. The first place to start is to put a methodology in place to define a flow supporting FPGA-based prototyping making a part of the larger SoC project. The FPGA-based Prototyping Methodology Manual, FPMM, is the perfect place to start in defining what is needed as part of this flow.  

I had the pleasure of traveling with Rene Richter, one of the co-authors of the FPMM. In the picture above you can see him explaining the basis of multi-FPGA partitioning and how to utilize pin multiplexing. His expertise helped a lot of customers last week but he was the first to say that everything he explained was already documented in the FPMM.

This week’s call to action, download the FPMM if you have not already done so………… and read it.

I was thinking that it might be time to work on the 2nd revision, updating the FPMM with information on how FPGA-based prototyping has evolved over the last couple of years, what do you think? What do you think has changed in FPGA-based prototyping which should be documented?

Posted in ASIC Verification, FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps | Comments Off

Super UltraOcta cores with ARM CPU and Imagination GPU’s boosted with FPGA-Based Prototypes

Posted by Michael Posner on 28th February 2014

Recently All Winner announced that their new UltraOcta A80 Mobile application processor utilizing the Imagination PowerVR 6230 64-core GPU would be coming to mobile devices very soon. (I call this the Super UltraOcta just for the effect)


Maybe not many people know this but All Winner utilized HAPS-70, the Xilinx Virtex-7 2000T based systems as part of the development and validation cycle for the A80 Octa SoC


The All Winner SoC features eight ARM(R) processor cores in a big.LITTLE(tm) processing configuration as well as the Imagination PowerVR GPU core. With both CPU and GPU you end up with a lot of hardware/software interaction which we know requires extensive validation to ensure that both the hardware and software are bug free. The high performance of the HAPS FPGA-based prototype enabled a huge volume of tests to be run which are needed to flush out those hard to find bugs.  

All Winner’s eight core-based SoC demanded a high performance validation solution to speed validation of their this SoC design. HAPS FPGA-based prototypes are the proven and essential methodology to perform large SoC validation tasks. HAPS delivered the performance needed to validate Allwinner’s A80 Octa SoC. The complexity of Allwinner’s SoC increased both cost and schedule risks due to the need to verify real-world scenarios early in the development cycle. HAPS mitigated those challenges as a cost effective solution that achieved the performance required to validate Allwinner’s SoC, while reducing ASIC design time and cutting months off their development schedule

I went looking on the WWW for a block diagram of this chip but as it’s so new I could not find anything, what I did find on the following link was an different multi-media design from MediaTek http://www.engadget.com/2013/07/29/mediatek-mt8135-biglittle-mp-powervr-series6-g6200/

I’m sure the All Winner and MediaTek designs are different in various ways but we can use this block diagram (on the linked page) to talk about the main componets. You have the ARM CPU and Imagination GPU but you can see all the other standard interfaces such as MIPI, DDR3, LPDDR, USB and a whole bunch of sensor interfaces. The strength of FPGA-based prototyping as mentioned above is perfromance and real world IO. Mobile multi-media designs like this are a perfect fit for FPGA-based prototyping due to the real world interface testing need as well as the challenge to validate the CPU to GPU connectivity. CPUs can be abstrated and run at incredible high performance as virtualized models but GPUs are not a goot fit for abstraction like this. GPUs require full cycle accuracy which is why FPGA-based prototyping is perfect fit for modeling them.

One problem of modeling GPUs on FPGA-based prototypes is the fact that the GPU is typically far bigger than a single FPGA (Hey, that’s one of the Breaking the Three Law’s for FPGA-Based Prototyping). This is where the HAPS Multi-FPGA systems step in and help solve the problem. First the HAPS software tools are used to partition the GPU design across multiple FPGA’s. Belows block diagram is an abstracted diagram of a typical GPU partition. Note the 1000’s of signals between FPGA’s. FPGA’s don’t have this many physical pins so the HAPS High Speed Time Domain multiplexing needs to be used to package up the signals and send them between FPGA’s using a high speed 1Gb/s link.

The HAPS-70 flexible interconnect architecture (Blog on this capability) is utilized to create an interconnect that has increased density where needed to help reduce the overall mux ratio. (Lower mux ratio, higher the system performance) Between this capability and the HAPS HSTDM the resulting platform is optimized and high performance. A GPU partition like the above on HAPS can run in the range of up to 15 MHz which is amazing.

How fast are you running your GPU cores?

Off subject, last week my son was asked to draw a picture of one of their parents hobbies. Finn decided to draw a picture of me and my race car hobby, one of the drawings is below.

I’m not sure where he got the idea that my car racing included using a fire extinguisher to put out engine fires ;) Click the idea link to see a short video of just one case which might have lead him to think this.

Posted in ASIC Verification, Bug Hunting, Early Software Development, In-System Software Validation, System Validation | Comments Off


Posted by Michael Posner on 22nd February 2014

I’ve been traveling in Europe popping into see various FPGA-based prototypers. It’s been a good week of lively discussion covering all aspects of prototyping from mapping RTL to prototype, to higher debug visibility and Hybrid Prototyping. At a number of these visits we discussed IP validation using the PCIe connected use model. I’ve discussed this use mode a number of times, in summary an IP block is placed in the FPGA-Based Prototype and then a PCIe end point core is used to memory map the IP across to a host machine. Typically the IP has a standard SoC bus interface such as AMBA so a bridge from AMBA to a PCIe core is used.  

The PCIe connected mode is delivered as part of the HAPS-DX complex IP and subsystem prototyping system. A automated insertion solution is delivered as part of the HAPS-DX prototyping software tools flow. The users can select the PCIe connected use mode and the software tools will insert a PCIe end point into the prototype. Hey presto, it’s easy to deploy the PCIe connected mode. Now while HAPS-DX meets the need for many IP’s I spoke to a number of customers who’s IP blocks were far, far larger than the capacity of the HAPS-DX, 4 Million ASIC gates. The good news is that the PCIe connected mode can be used with any of the HAPS-70 series as well. On the HAPS-70 systems the multi-gigabyte (MGB) connectors are used with a cable based connection to a host machine. With the HAPS-70 capacity scaling to 288 Million ASIC Gates (more on this in a later blog) you have plenty of space for even the biggest IP blocks.

The great thing about the PCIe connected mode is that the IP can be stressed tested in a similar fashion to simulation unit testing, the difference is of course the performance of the FPGA-based prototype enables far more testing to be achieved. This is perfect for the IP developers and the software engineers as they have a high performance realistic model to work against.

Don’t forget that at some point the IP needs to be integrated into the SoC so that the IP can be validated in the context of the SoC infrastructure.

For all the Irish and American Irish readers, the Guinness is better in Ireland, YUM

Posted in ASIC Verification, Debug, Early Software Development, IP Validation, Use Modes | Comments Off

How To: Enable Early Software Development, Find Critical Bugs and Save Up To 6 Staff Months of Effort

Posted by Michael Posner on 25th January 2014

Enabling early software development, finding critical bugs while saving up to 6 staff months of effort sounds like the holy grail of the design and validation. The funny thing is that it’s not a mythical creature, this is the reality of FPGA-based prototyping, specifically HAPS FPGA-based prototyping solution.

Synopsys surveyed it’s HAPS customers (Using a 3rd party called TechValidate) and asked them to describe the value they get from using HAPS. The results in my opinion were pretty overwhelmingly positive. Here is a snippet of the results.

HAPS enables early software development

HAPS helped discover critical bugs

HAPS saves up to 6 months of development effort

All the other results can be found here:


These results show why so many companies utilize HAPS. I’m feeling lonely, please comment on the value you get from HAPS so that I have something to blog about next week

Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, In-System Software Validation, Man Hours Savings | Comments Off

Tear down of the new HAPS-DX FPGA-based prototyping system

Posted by Michael Posner on 20th December 2013

I’ve talked about streamlining IP to SoC prototyping and the use modes that prototypers use for IP validation. This week Synopsys announced the new HAPS Developer eXpress (HAPS-DX) prototyping system. This new HAPS-DX system is perfect for complex IP and subsystem prototyping and ties in nicely with the flow that I have been blogging about for streamlining IP to SoC. Similar to what I did last week with the Xilinx press release I thought I would do a tear down and cut to the chase and detail how HAPS-DX will benefit you.

Oh just so you know, this is a super long blog as I’m going to be on vacation over Christmas and New Year and won’t be blogging for a couple of weeks. With this blog being so long it will take you until 2014 to read. Please, please, please take the time to read it over hot coco and biscuits.

HAPS-DX is targeted at complex IP and subsystem prototyping and its 4 million ASIC gate capacity is perfect for this usage. I know this as Synopsys is the #1 Interface IP provider with DesignWare IP and all these IP’s will fit nicely inside of HAPS-DX. I expect we will see more use of HAPS-DX with DesignWare IP in the future… Using a smaller FPGA with a more basic board form factor means that the price point of HAPS-DX is in line with the expectations of the teams doing complex IP and subsystem prototyping. Complex IP and block design teams are usually more cost sensitive than the wealthy SoC team. Our customers love the HAPS prototyping capabilities but some others think the price of HAPS puts it out of their reach and they have to make do with inferior solutions. Enter HAPS-DX, yay, HAPS premium prototyping capabilities at a price point that satisfies everyone. Contact your local and friendly Synopsys sales person for specific pricing.

A platform like HAPS-DX is essential as more and more IP blocks will be making up the full SoC. To accelerate the time to market of the SoC you need to accelerate all parts of the design and validation tasks starting at the IP level. If you can accelerate the early tasks you can start other SoC activities earlier such as SoC integration and early software development.

Below are the highlights from the press release, which I’ll use these as the main tear down points from this point on.


  1. HAPS Developer eXpress (HAPS-DX) supports up to four million ASIC gates and easily integrates with HAPS-70 systems to enable seamless software development, hardware/software integration and system validation from IP to complete SoCs
  2. HAPS-DX includes optimized software for FPGA synthesis, debug and clock optimization supporting fast prototyping modes to accelerate time-to-first prototype
  3. Superior debug capabilities are built in with HAPS Deep Trace Debug, which can store seconds of signal trace data, and supports Synopsys Verdi, which delivers superior debug visualization
  4. Pre-validated DesignWare IP and access to a broad portfolio of HAPS daughter boards and FPGA Mezzanine Cards (FMCs) enable the quick assembly of prototypes
  5. Included Synopsys Universal Multi-Resource Bus (UMRBus) interface enables hybrid prototyping by providing a seamless connection between HAPS and Synopsys Virtualizer-based virtual prototypes for pre-RTL software development

I numbered the points so it’s easier to refer back to them in the blog. Starting where you would expect me to start, with #1,this point is all about enabling a seamless flow from IP to SoC prototyping. The HAPS-DX is targeted at complex IP and subsystem prototyping but that IP or subsystem usually ends up in an SoC and the last thing you want to do is to repeat the prototyping effort at the SoC level for those same blocks. HAPS-DX was developed with the streamlining of IP to SoC prototyping in mind. HAPS-DX provides reusable hardware and a software flow that is interoperable within a greater SoC project.

As pictured above the HAPS-DX was designed with reuse in mind. The HAPS-DX can be used directly as a daughter board connected to the larger HAPS-70 systems. This means that if IP prototyping is done right the same setup can be quickly incorporated into the SoC level prototype. This translates to reduced effort for the SoC team as the IP team did most of the work for them. The hardware needs to be able to support this usage and a methodology of planning for IP to SoC prototyping needs to be deployed. See here for my previous blog on IP to SoC prototyping. You can use the HAPS High-Speed Time-Domain Multiplexing between HAPS-DX and the HAPS-70 meaning that you are not limited to physical pin connectivity. HAPS HSTDM enables many signals to be packaged up and sent across the high performance link. Value summary: Start software development earlier from SoC prototype being operational earlier.

#2 is going to be a HUGE benefit to the complex IP/Subsystem prototyping teams as well as the SoC teams in the future. Along with HAPS-DX you get prototyping specific software customized for HAPS-DX at extra charge, which is an immediate cost benefit that I know everyone will like. More importantly this software specifically addresses the needs of the ASIC IP and subsystem prototypers, which are a little different than that of pure FPGA synthesis users. As talked about in this blog, the needs of prototypers are different than the needs of a designer targeting an FPGA as part of their final product. This new HAPS software is specifically architected to address the challenges of time to operational prototype, performance, debug and productivity. With this new software you should be able to get the HAPS system up and running faster meaning you get a gain of time to market and as mentioned earlier you can start the SoC integration tasks earlier.

This new HAPS software incorporates the core unique Synopsys technologies along with a new set of capabilities specifically addressing prototyping challenges. At the start of the prototyping project the prototyping engineer is not so worried about squeezing the optimum performance out of the FPGA. They really want to get to a functional prototype as quickly as possible so they have something to hand off to keep the software developers or validation team happy. Once they have handed off that image they can work on optimizing the prototype. The HAPS-DX software delivers on both with capabilities customized for time to first operational prototype and a path to high performance.

What’s not mentioned here directly is that the new software is very ASIC flow like rather than FPGA like. We see a trend that companies no longer have specific “FPGA experts” for prototyping; they use the same validation engineers that are used to working with Design Compiler synthesis scripts and VCS simulators. The HAPS-DX software provides a more ASIC like design flow with bottom up design flow, TCL scripting and multi-processing for improved productivity. FPGA-based prototyping software tools have grown up. Value summary: Start IP validation and software development earlier from earlier prototype availability

#3 is all about debug and the bottom line is that with HAPS-DX you are going to get greater debug visibility, which means you should be able to track down the source of the bug faster and productivity should go up. Debug is a hot topic with respect to FPGA-based prototyping and while there have been point tool solutions trying to solve the problem in the past, the HAPS-DX was designed with the need of debug built right in.

When debugging you want greater visibility and the capability to store more trace data. In a simulator you have almost infinite trace data storage, but in hardware you are limited to the physical storage medium. HAPS-DX delivers software that automates the insertion of debug instrumentation providing a simulator like experience in addition to integrated HAPS Deep Trace Debug built right onto the hardware. This is not a new concept for HAPS, I’ve blogged about these capabilities before, here and here. What is new is that HAPS-DX has it all built-in to both the physical hardware and the included software flow. Now you can quickly add debug capabilities into your prototype right from the get go of the project rather than adding it later when someone is beating on your door for more visibility to find the root cause of a bug.

Here you can see the DDR3 memory directly built into (and supplied with) HAPS-DX. I spoke to the engineer who spearheaded the HAPS Deep Trace Debug capabilities and asked him for an example of the benefit to users. He’s an engineer and answered me in engineering terms. His answer was “Think 128 signals captured at 100 MHz, you have the capability to store 5 seconds of trace data on the 8GB DDR3”. 5 seconds of trace data !!!!! That’s huge in the world of at speed debug. Add to that the fact you can write out FSDB which is the native waveform database for the Verdi debug tool. Verdi is used extensively in the ASIC debug space and now you can use the same capabilities with your HAPS-DX prototype. If you have access to Siloti you can also use the visibility expansion capabilities and get close to 100% visibility of select modules. Value summary: Higher productivity from ability to find and fix bugs faster

#4 is all about easing prototype assembly which I blogged about recently as well (you would almost think I planned all these blogs). I’m won’t comment on the DesignWare IP support, as mentioned above I’ll save that for a future blog. What is important to you is that HAPS-DX supports both the validation modes that you use and enables a huge range of hardware daughter boards so you can tailor the system to your specific project needs. HAPS-DX supports the traditional standalone mode, PCIe connected and the emerging hybrid prototyping use modes. I expect that hybrid is going to be a popular use mode for HAPS-DX as you can immerse the IP in a virtual representation of the SoC without having the actual RTL.

The alternative to buying HAPS-DX would be building a specific FPGA board that meets your project’s needs; it’s the age old make vs. buy. Most engineers think that designing a single FPGA platform is easy, and for an experienced designer it might be. The board can be designed with the needed interfaces built right onto it keeping it cheap to deploy. However, I know many teams that have designed great FPGA boards but still got burnt during the active project. The issue is marketing. Yep, the marketing team comes in with a late change request, the latest example I heard was a shift from USB 2.0 to USB 3.0, and unfortunately the hardware didn’t support the new requirement. The team had to scramble, redesign the boards and the project slipped 3-6 months. Yuck. HAPS-DX’s advantage is that it supports both HapsTrak 3, the same connector standard used with HAPS-70, as well as providing an FMC interface module.

With HT3 you get to pull from the large portfolio of available Synopsys daughter boards and others from 3rd party vendors that provide specialized daughter boards for HAPS systems such as Gigafirm, who I visited while I was in Japan and highlighted in this blog. In addition, the FMC interface module enables you to utilize the HUGE range of FMC style daughter boards available. There are literally 100’s (no joke I counted) of available FMC daughter boards available enabling AD/DA, serial connectivity, imaging processing and many, many more. Basically you get to tailor HAPS-DX the way you like it. It doesn’t get easier than that and even that pesky marketing team can come in and change the requirements on you at the last minute or worse mid project and all it not lost. Simply reconfigure HAPS-DX with a new daughter board expanding its usage to the new requirement. And if that was not enough, when the next project comes along you can reuse HAPS-DX assembled with a new set of daughter boards meeting the requirements of the new project. Value summary: Easy prototype assembly reduces effort and greater reuse increases return on investment

Finally, #5 is all about the more advanced use modes. The HAPS Universal Multi-Resource Bus, UMRBus, is the gateway to connecting the HAPS prototype to host machines. The UMRBus capability is built directly into the HAPS-DX meaning no add-on cost and comes with a set of example designs easing the setup of the prototype. As mentioned above, the hybrid use mode is getting more and more popular especially for IP validation. While it was once fine to validate a block outside of the context of an SoC, the CPU and software have become essential as part of the validation of the IP or subsystem. You actually need to validate the real software against the IP to know that it operates correctly. Enter the PCIe connected modes and hybrid prototyping. These operation modes enable software to be run on a host and executed on the real hardware representation of HAPS-DX. In the hybrid mode you model the system in a virtual prototype such as Virtualizer and then communicate to the HAPS-DX via the UMRBus. Synopsys already provides a library of transactors which act as the translation between the SystemC environment and the signal and pin toggling needed in real hardware. You immerse the IP in a realistic representation of the real SoC ensuring that when the IP is integrated into the larger SoC you already have high confidence that it’s fully operational. Value summary: Greater productivity from rapid deployment of advanced use modes

Oh boy, this blog is huge……. please, please, please take the time to read it. Of course if you are reading this then you have made it to the bottom, congratulations.

So summing up, with HAPS-DX you get a flow from IP to SoC, prototyping software that accelerates the time to first operational prototype, built in debug for greater debug visibility, fast prototyping assembly with HT3 and FMC daughter boards and the support for all expected prototype use modes. Actually the press release bullets nailed the benefits. I still think my tear down of the points will help explain better how each of these benefits affects you more directly.

  • HAPS-DX increases your productivity, making your manager happy
  • HAPS-DX reduces your effort, making you happy
  • HAPS-DX reduces your risk, making everyone happy

Happy Holidays

Posted in ASIC Verification, Debug, FPGA-Based Prototyping, Getting Started, Technical | Comments Off