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Breaking The Three Laws
 
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Archive for the 'Admin and General' Category

Xilinx UltraScale VU440 Integrated Design Implementation and Debug

Posted by Michael Posner on 30th May 2015

HAPS System with Xilinx UltraScale VU440 devices in Synopsys lab

Pictured in the Synopsys lab, above, is one of the fully operational next generation HAPS systems. I was asked multiple times this week why Synopsys has not publically announced the systems when the hardware is fully operational. There are a number of factors which make up the reason with the most important being that hardware is only a fraction of the challenge of FPGA-based prototyping. You cannot be successful without an implementation tool flow and that tool flow must be tested against the real hardware. We will announce when the complete solution is ready to go and can make customers immediately productive. Saying that, if you want early access to the HAPS ProtoCompiler software tool set and HAPS hardware with engineering sample Xilinx FPGA’s then contact me or your local Synopsys representative. We are already collaborating with over 20 customers in preparation for full availability.

Synopsys is ahead of the curve in all areas of product development, hardware functionality, software tool flow and IP. The hardware is ready, we are doing final characterization and integrated feature testing, these are the capabilities that are built into hardware and deployed via the software and IP flow. Of course, just like everyone else this testing is being done using Engineering Sample FPGA silicon as production Xilinx UltraScale VU440 devices are not available until late in the year. HAPS ProtoCompiler is operational with the main focus of testing being again the integrated capabilities such as always available debug, new pin-multiplexing capabilities which can improve system performance by up to 50% or more (I’ll blog on this new feature over the next couple of weeks) and the timing driven flow which is hardware aware and dependable as it’s based on the timing characteristics of the actual hardware and accessories.

Talking about integration, one of the existing HAPS ProtoCompiler capabilities which I’ve never talked about is the simple abstraction from FPGA pins to HAPS capabilities. This abstraction means that the engineer only needs to care about the HAPS hardware specific IO’s and capabilities and does not have to be a FPGA expert. For example:-

1. Top level pins uses HAPS name (applicable to HAPS-70 and HAPS-80)

define_haps_io {p:clk} -haps_io {GCLKP[1]} automatically assigns the port “clK” to HAPS GCLK 1. HAPS ProtoCompiler automatically inserts any required buffers, IO standard and constraints.

2. GPIO/LED Pins can use virtual IO names: (Applicable ONLY to HAPS-80)

define_haps_io {p:red[1:0]} -haps_io {A_LED_RED[2:1]} no need to manually work out where the LED is connected, HAPS ProtoCompiler automatically maps to it.

3. Once you are done, HAPS ProtoCompiler IO Report provides detailed information about RTL Names, HAPs Name and equivalent Xilinx Pin names.

In the below screen shots you can see both the HAPS ProtoCompiler implementation GUI and runtime analysis GUI. In the implementation GUI I have highlighted the HAPS-IO abstraction and the debug instrumentor. You insert debug monitors and watchpoints using the source RTL just like you do with a normal RTL simulator.

HAPS ProtoCompiler for Xilinx UltraScale VU440 design implementation GUI

In the runtime GUI you can view the debug data overlaid on the original RTL source, regardless of partition. In this screen shot we are also exercising the Universal Multi-Resource Bus, UMRBus, capability. (I just noticed that the UMRBus report strings still say HAPS-70, I assure you this design is running on the new systems. Hey, I said we are still developing and testing the software)

HAPS ProtoCompiler for Xilinx UltraScale VU440 Design Analysis GUI

Do you want to talk to me at DAC? If yes, shoot me a note, comment or email and we can setup a time to meet.

Posted in Admin and General, UltraScale | No Comments »

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM

Posted by Michael Posner on 23rd April 2015

SYNOPSYS SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH COMPLETE PROTOTYPING PLATFORM…. Yes, we did this way back in 2010 with the launch of the HAPS-60 complete solution, and then raised the bar in 2012 with the launch of the evolutionary HAPS-70 complete solution. Synopsys HAPS is a proven integrated solution delivering the fastest time to operational prototype, highest system performance, superior debug and advanced capabilities including Hybrid Prototyping and global server farm access.

HAPS Solution

This week I’m feeling feisty so my blog is going to be a little more edgy than normal. The launch of the HAPS-60 series in 2010 delivered the first integrated FPGA-Based prototyping solution with key capabilities such as automated deployment of unique HAPS High Speed Time-Domain Multiplexing (pin-multiplexing) schemes in Synopsys’ Certify. Host connected, globally accessible hardware with the HAPS Universal Multi-Resource Bus, UMRBus, as well as advanced data streaming and platform connectivity. The solution included integrated superior debug visualization for bug hunting. Yes, in 2010, over 5 years ago, Synopsys set the new standard for FPGA-based prototyping with a comprehensive prototyping platform. Since then, our solution has rapidly evolved delivering far greater value.

HAPS-70 hardware, just becuase I like the picture

The HAPS-70 (which, by the way, was selected as Electronic Design http://electronicdesign.com/ “Best of 2012” recipient) with fully integrated HAPS ProtoCompiler, the prototyping implementation environment, accelerated the deployment of prototypes by providing advances in automation including time to first prototyping modes and timing biased partitioning.

HAPS ProtoCompiler, the leading FPGA-based prototyping implementation tool

Synopsys has always been the leader in debug visibility and the HAPS integrated debug capabilities enables at speed debug across multiple-FPGA’s in addition to integration with the leading Synopsys Verdi debug visualization software.

HAPS Debug, superiour debug visualization

The HAPS UMRBus has for multiple generations enabled the hardware to be a globally accessible resource for server farm and multi-user scenarios in addition to enabling data streaming modes and Hybrid Prototyping capabilities.

HAPS UMRBus, global access, farm usage, advanced data streaming modes

At about the same time as the HAPS-70, Synopsys launched the first commercial Hybrid Prototyping solution. HAPS Hybrid Prototyping enables HAPS to be connected with Virtualizer, Virtual Prototype delivering early prototyping capabilities, IP and in context validation scenarios.

HAPS Hybrid Prototyping, accellerating the availability of prototypes

Talking of IP, Synopsys is the leader in interface IP and offers DesignWare IP Prototyping kits for immediate software development and prototyping of key IP titles.

DesignWare IP Prototyping Kits, immediate availability

All this wrapped with the global expert support, eco-system of HAPS Connect partners, professional services. This is how we define a complete solution. What I am trying to illustrate is that Synopsys is now, and will continue to be the technology leader in FPGA-based prototyping. Synopsys continues to invest and the HAPS next generation solution will raise the bar again ensuring that our integrated FPGA-based prototyping products meet your requirements today and way into the future.

Posted in Admin and General, ASIC Verification, Bug Hunting, DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Real Time Prototyping, Support, System Validation, Use Modes | 1 Comment »

Success Prototyping with UltraScale VU440 devices

Posted by Michael Posner on 3rd April 2015

UltraScale based HAPS system operation in Synopsys lab

It’s been a while since Xilinx shipped the first UltraScale VU440 engineering sample devices to Synopsys so I thought it time to deliver a short update on development progress. It might be hard to see in the above but that is a picture of one of the new development HAPS systems for the UltraScale VU440 devices. I say hard to see not only as the picture quality is low but also because we have the system completely configured with intelligent interconnect as part of our stringent characterization and functional validation process.

Each module is individually tested, see picture below as an example, this is the controller module in standalone test. The controller module hosts the HAPS supervisor which controls the system and manages advanced capabilities such as the Universal Multi-Resource Bus, UMRBus for short. Once all individual modules are signed-off they are assembled and the system is validated.

New HAPS Control module in standalone test jig

So far both the Xilinx VU440 devices and the new systems are functioning well. Xilinx has posted an errata on the engineering sample VU440 devices but these issues do not preclude the devices from being useful for system development or actual usage as part of a production prototyping project. All IO’s are operational as well as the transceiver GTH links. We have been filling the devices with high speed toggle designs as part of the performance and power characterization and smaller IP designs for other test purposes so we have not compared the utilization between V7 and UltraScale devices yet. We still predict that the UltraScale VU440 devices will deliver ~26 Million ASIC gate capacity, about 2.2X increase over the V7 2000T devices.

As a teaser for future blogs, the new integrated solution is expected to deliver

  • Highest performance w/superior partitioning & new time domain pin-multiplexing schemes
  • Always available debug with deep trace storage
  • Fastest time-to-first-prototype with HAPS aware prototyping software
  • Rapid Turn-around Time from RTL to Bit file with incremental flows
  • Native integration for regression farm & remote accessibility
  • Both HW and SW tool flow is Modular & scalable to over 24 FPGA’s (Over 600 Million ASIC Gate capacity)
  • Hybrid Prototyping ready

Preserves existing HAPS investment

  • Interoperable with HAPS-70 & HAPS-DX, (mix and match HAPS V7-based systems with UltraScale systems) same form factor, I/O voltages, HT3 connectors, daughter boards, cables

In the coming months I’ll post more information on these new and unique capabilities.

HAPS Integrated solution

Posted in Admin and General, ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Project management, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off

Coming To A Lab Soon: Xilinx VU440 FPGA Devices

Posted by Michael Posner on 16th January 2015

Xilinx Summary of the new UltraScale VU440 FPGA device capabilities for prototypers

In late 2013 I blogged about the newly announced Xilinx UltraScale devices, the VU440 specifically that will be the largest FPGA device on the market: http://blogs.synopsys.com/breakingthethreelaws/2013/12/xilinx-fpga%E2%80%99s-for-fpga-based-prototyping/

Well this week Xilinx officially announced that they have shipped the first samples of the VU440 devices: http://press.xilinx.com/2015-01-15-Xilinx-Delivers-the-Industrys-First-4M-Logic-Cell-Device-Offering-50M-Equivalent-ASIC-Gates-and-4X-More-Capacity-than-Competitive-Alternatives

Snippet from Xilinx Press release on the VU440 device and the fact that Synopsys received the first device samples

And check out who received the first of these samples…………………………… ok, you don’t need to read it, Synopsys did…….. We have optimized every generation of our HAPS prototyping systems for the highest system performance, greatest capacity while adding significant capabilities on top delivering prototyping specific features. We all know the FPGA device is a required component within the FPGA-based prototyping hardware but it’s not what defines or makes the solution useful. Anyone can slap an FPGA on a board but this does not help a prototyper as the device alone does not deliver the capabilities they require. Prototypers rely on a solution which includes a software implementation tool flow, integration between hardware and software accelerating time to operation, built in capabilities such as high speed pin multiplexing and high visibility debug to ease bug hunting while being modular and scalable. (side note: Synopsys offers exactly this…. just in case you didn’t know)

I recommend you also check out the VU440 demo video. It stars my friend Kirk from Xilinx who introduces the new device and the demo running ten ARM Cortex-A9 CPU’s, pretty impressive. http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html#uniquePlayer1

Over the coming weeks I’m going to focus my blogs on the capabilities that the new Xilinx UltraScale devices deliver and the impact they have to prototypers. As noted above, an FPGA alone does not deliver FPGA-based prototyping so I will discuss how the device capabilities are expected to be integrated and leveraged delivering a solution.

Oh, and just because Synopsys has received Xilinx sample devices don’t expect a new HAPS next week. Delivering a solution requires hardware development, software development and a huge amount of validation. But I’m confident that when you are ready to adopt, Synopsys will be ready to deliver…..

Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, Man Hours Savings, Milestones, Technical, Tips and Traps | Comments Off

Synopsys’ New ProtoCompiler Software Speeds Time to Prototype

Posted by Michael Posner on 28th April 2014

 

Synopsys just announced ProtoCompiler which is automation and debug software for HAPS FPGA-Based Prototyping Systems. ProtoCompiler is the result of years of R&D effort to generate a tool that addresses prototypers challenges today and built on top of an architecture which can support the needs of prototypers long into the future. ProtoCompiler focuses on the needs of prototypers specifically addressing the need for accelerated bring up as well as providing capabilities which result in higher system performance as compared to existing solutions. In this blog I’ll discuss some of the technical details behind the main tool highlights. Below are the detailed highlihts.

  • Integrated HAPS hardware and ProtoCompiler software accelerate time to prototype bring-up and improves prototype performance
  • Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs
  • Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance
  • Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility

(Read to the end of the blog if you also want an update on Mick’s Projects)

Highlight: Integrated HAPS hardware and ProtoCompiler software accelerate time to first prototype bring-up and improves prototype performance

As noted above the goal of ProtoCompiler is to accelerate the bring up of a prototype as well as providing a path to the fastest possible operating performance. ProtoCompiler is unique as it combines hardware/software expertise with intimate knowledge to deliver superior results. Think of it as delivering a HAPS hardware expert packaged up into a format that anyone using the tool can access. ProtoCompiler has deep technical knowledge of the HAPS hardware including configuration, clocking structures, interconnect architecture, pin multiplexing expertise and more. ProtoCompiler is not only a hardware expert, it’s also a software expert. ProtoCompiler is built on top of a state of the art Synopsys proprietary prototyping database that means RTL is effectively processed and incremental and multi-processing techniques can be deployed with ease.

All this results in blazingly fast processing speeds. As an example ProtoCompiler’s area estimation, essential for automated partitioning, can processed 36 Million ASIC gates in less than 4 hours as compared to 22 hours in existing solutions. Now that’s fast!. Thanks to the new data model and incremental modes all subsequent compiles are even quicker.

Highlight: Automated partitioning across multiple FPGAs decreases runtime from hours to minutes for up to 250 million ASIC gate designs

So there are actually two announcements packaged up in this highlight. Starting in reverse ProtoCompiler supports 250 Million ASIC gate and larger designs. Humm, this sounds a little suspect as when HAPS-70 was launched it only supported 144 Million ASIC gates, what does ProtoCompiler know that we don’t? Luckily I know, HAPS-70 can now be scaled to support 288 Million ASIC gates, 2x the capacity. HAPS-70 now supports chaining of any six systems so if you chain six HAPS-70 S48’s you get a total of 288 Million ASIC gates supported which is 24 Xilinx Virtex-7 2000T FPGA’s. All working in one synchronous system.

Any 3 HAPS systems can be chained via our standard control and data exchange cabling, when you go above 3 systems you utilize a synchronization module that manages the system synchronization. Managing clock skew, reset distribution and configuration is all handled automatically. ProtoCompiler understands the hardware capabilities thus making deployment of such a system a snap. No longer do your engineers have to worry about how to distribute clocking, we have done the hard work so you don’t have to. Other vendors “claim” scalability and modularity but if all they are delivering is boards then it’s nothing more than a wild claim. To deploy a scalable and modular system you need a complete solution of software and hardware. You can now prototype SoC designs you thought never possible

The first part of the highlight introduces the new partition technology deployed in ProtoCompiler. ASIC’s are bigger than a single FPGA so you need to quickly partition the design across multiple FPGA’s. Historically this has been a challenge but with ProtoCompiler that challenge has been overcome. The partition engine in ProtoCompiler requires minimal setup before you can apply it to your design. There are four simple steps to setup the partition engine #1 Create target system, basically which system(s) you are compiling to. #2 Establish basic constraints which are things like blocks of IO. #3 Define the design clocks. #4 Propose an interconnect structure. Actually #4 can either be defined telling the partition engine to use a set interconnect architecture or leave it open and let the tool do it. There are advantages of both. By letting the tool pick the needed architecture the resulting system should be higher performance as ProtoCompiler will maximize interconnect to reduce pin multiplexing ratio. In a previously deployed system you may have already set the interconnect and then want the tool to use the available resources so you don’t make any changes to the hardware in the field. ProtoCompiler has the flexibility to do both meeting the needs of new prototype creation and image re-spin after a new RTL code drop.

ProtoCompiler partition engine is FAST, using the same example as above, 36 Million ASIC gates, ProtoCompiler was able to come to an automated solution is 4 minutes!!! WOW. ProtoCompiler provides a huge amount of information as to what it automatically did so that the engineer can quickly review the results and maybe provide ProtoCompiler more guidance to optimize the partition. For example after the first run you might want to lock down select parts of the design and then incrementally run the engine to push it to find a better solution for the rest of the design. As it runs so fast you can do multiple of these optimization iterations in a matter of hours. I’ve played with the tool as I was interested in this particular capability and have to say it’s amazing. I’ve tried the open method and let the tool find a solution for itself, in this mode ProtoCompiler pretty much finds a solution every time. I also played with challenging the tool for example locking the tool to use only 100 IO’s (two HT3 connectors) between FPGA’s. ProtoCompiler quickly finishes and told me that I was crazy and that the design could never be partitioned with my selected interconnect architecture.

Highlight: Enables efficient implementation of proprietary pin multiplexing for 2x faster prototype performance

OK, this is simple, this basically says that ProtoCompiler can automatically deploy the HAPS High Speed Time-Domain Multiplexing (HSTDM). HSTDM is developed and optimized on HAPS and ProtoCompiler packages up this expertize and automated the deployment. The partition engine will automatically select HSTDM and instance it into the prototype design. HSTDM delivers high performance pin multiplexing between multiple FPGA’s. The signals are packaged up, sent across a high performance link and unpacked at the other side. This all happens within one system clock and is completely transparent to the user. No manual intervention, no additional latency, and it’s stable and reliable as HSTDM is tested as part f the HAPS production testing and every system has to pass the minimum HSTDM performance tests. This ensures that when you deploy am image with HSTDM that it runs on every system the image is loaded on. No need to tailor the pin multiplexing implementation for each board like you have to do with other vendors.

Highlight: Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility

ProtoCompiler expands the debug capabilities and grows the HAPS Deep Trace Debug capability which utilizes off-FPGA memory to store debug data. ProtoCompiler provides seamless multi-FPGA debug capabilities on top of a set of other debug capabilities tailored to delivering visibility at the right level of the debug cycle.

In debug one size does not fit all, you need to deploy the right level of debug visibility capability dependent on what you are trying to debug and the specific point you are in the project cycle. Sometimes you want very wide debug visibility with fast incremental turn-around. Later in the design cycle you typically want very, very deep debug windows. ProtoCompiler delivers both, fully automated through the flow, seamless and transparent to the users. And when I say deep, I mean deep, the example below is very typical of the debug window where you can easily capture seconds of debug data.

As usual my blogs got really long. I wrote it in the car while driving from Portland to Eugene. Amazing that I could type all of this and drive at the same time (LOL, only joking I was in the passenger seat)

Anyway, ProtoCompiler is the bees knees and I personally think it revolutionizes FPGA-based prototyping using HAPS. What do you think of ProtoCompiler?

If you have managed to get this far into my blog then congratulations. I’ve been taking it easy this week while I recover from the pneumonia that I came down with. In the evenings I finished off the two mini RC tracked vehicles I had been working on. The basis of both are simple kits which I then modified and added RC receivers and motor controllers to. While I am a grown adult I must admit they are fun to play with. The first is a basic platform RC tracked vehicle which I attached a Lego sheet to. Little did I know that this would be so popular with my son. He has been building towers and all types of structures on top of it.

Why drive your car to a car park when the car park can come to you. No joke that’s what my son said.

Mobile tire store

Bulldozer and sweeper

At the same time I also built a kit that has a shovel that moves on the front. Again I modified it to be radio controlled, including the shovel. This vehicle is a HUGE hit with my son and he has been busy building towers, knocking them down, then tidying them up with the shovel.

There are a couple of video’s of these little things in action on my You Tube page: https://www.youtube.com/user/MrMickPosner (and a video of my chicken food winch system)

Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, Man Hours Savings, Mick's Projects, Milestones, Project management, System Validation, Technical | Comments Off

Ice Cream with Raspberry Pi for Remote System Connectivity

Posted by Michael Posner on 15th February 2014

Engineering departments can no longer afford the luxury of all team members being located in the same office. The term global localization is used to describe how a team is split up over multiple geographies but must function as one unified entity. This is not only true for the personnel but also for the tools they use including FPGA-based prototyping hardware. While every software engineering in the world wishes for a high performance prototype directly on their desk typically logistically and financially this is not possible. FPGA-based prototyping systems must support this capability to ensure they can be accessed from anywhere around the world.

The HAPS series of FPGA-based prototyping systems support remote access via the HAPS Universal Multi-Resource Bus, or HAPS UMRBus for short.

The HAPS UMRBus enables the users to remotely access the HAPS system, configure it, monitor it and basically love it from a distance. The HAPS UMRBus enables much more than just remote access! The HAPS UMRBus enables data streaming to and from the system for test case stimuli or debug, advance use modes such as Hybrid Prototyping and transaction based validation and provides a generic API for user capability extensions. The HAPS UMRBus is able to deliver these additional capabilities because it’s a very high bandwidth, low latency connection from a host machine to the HAPS system.

The HAPS-70 series offers this high performance HAPS UMRBus and an integrated HAPS UMRBus over a lower performance USB 2.0 standard interface. The recommendation is that if you only needed remote connectivity for configuration and monitoring then use the HAPS UMRBus over USB 2.0 interface. If you needed high performance and low latency for Hybrid Prototyping and the other advanced capabilities then utilize the high performance HAPS UMRBus. Great right………………… Enter global localization…..

Our customers love that HAPS systems can be remotely accesses as it enables them to utilize the systems 24/7, 365 days a year (HAPS don’t even get Christmas off). However they like to lock them up along with their server hardware or in a data center. Some customers have dedicated hosts serving the HAPS which enables them to utilize the high performance, low latency HAP UMRBus and all the advanced capabilities. However, others just want to utilize the remote access via the HAPS UMRBus over USB 2.0 and while they have thousands upon thousands of Ethernet drops available they rarely have a host which they can plug the USB 2.0 cable into. So what are these users to do?

Enter the Raspberry Pi (see the blog title was not a typo but I bet the engineers already knew that)

To enable our customers to plug the HAPS system directly into an Ethernet hub one of our engineers came up with the great idea to utilize the off-the-shelf Raspberry Pi.

How it works: You buy a Raspberry Pi, USB cable, power supply and SD card, this is going to set you back around $50 (yep, not a typo, $50 and that’s usually a top of the range one). You then contact Synopsys HAPS support and we will provide you with a boot image to load on the SD card. The boot image is a standard Raspberry Pi OS with the HAPS remote access utilities, called HAPS Confpro, pre-installed. Next connect the USB cable between the Raspberry Pi and the HAPS-70 (or HAPS-DX) system. Finally connect the Raspberry Pi’s Ethernet connection into the Ethernet hub/switch and power it up. We recommend assigning a defined IP address to the Raspberry Pi so the HAPS system it’s connected to can be easily recognized. That’s it, you are ready to access the HAPS system remotely. I personally love this solution as it not only solves the problem but also lends itself for further capability expansion in the future. More on the expansion capabilities in a future blog….

What do you use the Raspberry Pi for?

Posted in Admin and General, Debug, Project management | Comments Off

Call to Action: Wiki FPGA-Based Prototyping Page Needs Content!

Posted by Michael Posner on 11th July 2013

While surfing the web I ran across the Wikipedia pages on FPGA-Based Prototyping, which they call FPGA Prototypes. http://en.wikipedia.org/wiki/FPGA_prototype Unbiased content is much needed for this page. Synopsys recently made a couple of updates implementing some quick fixes but what it really needs is some real users to update the article.

I know there are many FPGA-Based Prototyping experts out there, put this talent to even more use and update the Wiki page. If you comment below and let me know you have updated the page I’ll be happy to send you one of my Subaru piston paper weights that for some strange reason no one has claimed yet.

Off subject (as usual) it’s been surprisingly warm here in Oregon. With the nice weather I moved the two bouldering walls that I built to the outer part of my patio. The kids love to climb around on them and having them next to the big planter boxes that I built make for additional climbing challenges.

Posted in Admin and General, FPGA-Based Prototyping, Getting Started | Comments Off

Jim Hogan falls prey to HAPS cloak of invisibility

Posted by Michael Posner on 29th April 2013

I used to own a Ford F350 truck and it was huge with the long wheel base, full bed, extended crew cab measuring a length of about 25 feet (8 meters). The problem was that it came installed with a cloak of invisibility. I didn’t know it had a cloak of invisibility when I purchased but soon after while driving it down the freeway (motorway) a small car merged into the side of me. Unsurprisingly I won that battle and when I asked the other driver how it happened they responded “I didn’t see you”. Wait a second my truck is 25 feet long and that day I was towing a 25 feet long fully enclosed car hauler meaning I was over 50 feet long. How do you not see that…….. That’s when I realized that this truck came with the unadvertised cloak of invisibility option.

So what has this got to do with Jim Hogan you all ask….. well read on and find out.

The cloak of invisibility must be an undocumented feature of the HAPS product line as Jim Hogan wrote a complete article on emulation with mention of prototyping and managed not to mention HAPS once (well ok, once but that was in a table and that was the only mention). I should state that I do not know Jim personally and hold nothing against him. Jim’s article was pretty good but I am afraid I have to personally doubt the credibility of the data when the highest quality and most well-known FPGA-Based Prototyping product, HAPS, didn’t get a proper mention. Jim what were you thinking!!!!  Jim’s article focused on emulation but draws reference to FPGA-Based prototyping a number of times which is why I think HAPS should have been included in the article.

I have to believe that this omission was due to the undocumented HAPS cloak of invisibility. Jim; contact me and let’s solve this mystery.

What also got me all riled up was the following;

  • All FPGA-based solutions are “Emulators”

Not so! Jim included FPGA-based prototypes in the discussion – referring to them as “low-capacity emulators” (and never mentioned HAPS). Emulators focus on Verification providing a high level of automation and debug.  FPGA-based prototypes focus on Validation providing the high performance needed for software development and system validation with real world IO. I’ve blogged about the differences in the past (here).  Below is a recap of that incredible blog with simple graphics

I love the above analogy. You own both but depending on the task at hand you pick the right tool for the job.

The following simplifies the difference between Verification and Validation. While they both start with the letter V the goals are very difference which is why both emulation and prototyping play an important part of an SoC’s development.

Oh, I should also apologize for being tardy on my blog post this time around. I’ve been traveling a lot and when weighing up either writing a blog or sleeping, sleep always won.

Posted in Admin and General, ASIC Verification, FPGA-Based Prototyping, Humor | Comments Off

Don’t Forget SNUG SJC !!!!

Posted by Michael Posner on 22nd March 2013

Don’t forget SNUG SJC

http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

Mingle with over 2500 over engineers just like you (But of course you are the best)

Posted in Admin and General, FPGA-Based Prototyping | Comments Off

SNUG and FPGA Debug

Posted by Michael Posner on 8th March 2013

This week, I have mostly been eating sushi.

Did you notice my blog title rhymed, SNUG and FPGA Debug, I thought that was pretty catchy.

 Alert, SNUG Silicon Valley is approaching fast, March 25th – 27th. http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx I’m personally not going to be able to make it down this year so I need you, my readers, to attend and then tell me all about it. There is a dedicated FPGA-based prototyping track and an FPGA implementation track.

 FPGA-Based Prototyping Track Highlights

  • FPGA-Based Prototyping: My BFF FPGA-Based Prototyping Solution: Better, Faster, and Flexible
  • Bring-up and Debug of FPGA-based prototypes: Pest Control, Hunt Down Bugs Like the Experts
  • Hybrid Prototyping 101

 FPGA Track Highlights

  • Designing with Xilinx 7 Series FPGAs: The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs
  • Maximizing Productivity on Large FPGA Designs: Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs
  • Synthesis Methods for FPGA-Based Prototyping

While I’m unable to go to the SNUG Silicon Valley event I’m planning on making a special appearance at SNUG UK.

On another note, did you miss the recent live web seminar on “10 ways to debug your FPGA design”? Well if you did don’t worry, the recorded version is available here: https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=579541&sessionid=1&key=1319D5CFF949C3FDAA3F860D951BE1F1&cmp=WEBR-fpga100204-HPW I highly recommend it and it’s presented by Angela Sutton who is an expert in the field.

Yummy sushi picture just for fun.

I’m working on a deep technical blog posting for next week. Well when I say working on I really mean I’ve got an idea for one I just need to formulate my thoughts. Lets see if I can wrangle them by next week.

Posted in Admin and General, FPGA-Based Prototyping, FPMM Methods, Getting Started, Humor, Tips and Traps | Comments Off