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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Speeding Prototype to Host Connectivity

Posted by Michael Posner on August 14th, 2014

A Chain picture which I thought would represent the link from host to HAPS.

A while back I talked about the various prototype to host connectivity modes facilitating IP and SoC validation including Hybrid Prototyping. The use of the Synopsys Universal Multi-Resource Bus, UMRBus for short, is key to deploying these use modes. Synopsys introduced the UMRBus along with the HAPS-60 systems and it’s popularity has grown ever since. The UMRBus provides an easy to use infrastructure for any user of the HAPS systems to configure, monitor and expend the capabilities of the HAPS system.

The UMRBus technical architecture. One side you have the hardware client application interface module, CAPIM for short. The otherside you have the generic UMRBus API which is the software layer which you program against

Synopsys provides the high level UMRBus API and the hardware interface modules along with the HAPS systems. These are the same building blocks that the Hybrid transactors are built on top of and which are delivered as part of ProtoCompiler. Multiple UMRBus connection modes are supported depending on the goal of the usage such as simple remote access and configuration to full blown high performance data streaming and Hybrid Prototyping. The follow is a list of the various connectivity modes and the expected performance. You can use these to pick the best connectivity solution to match your prototyping needs.

UMRBus over USB. The easiest connection mode as you just plug a USB cable from the host into the HAPS System either HAPS-70 or HAPS-DX

Typically the USB connection mode is used when all you want to do is remotely configure and debug the prototype.

UMRBus pod connecton. This provides the most flexibility in connectivity with UMRBus access to any and every FPGA in the system.

The UMRBus pod enables a seamless interface into the HAPS system with direct visibility into any FPGA in the HAPS chain.

This is UMRBus over a PCIe Paddle board. Basically the UMRBus is a layer on top of PCIe delivering the UMRBus capabilities over a very high performance link

This is a very high performance UMRBus mode for the HAPS-DX making it perfect for IP validation where lots of data need to be streamed on and off of the prototype. Using this mode over 400 MB/s streaming data bandwidth can be achieved

Same high performance as UMRBus over the paddle board, over 400MB/s with the added flexibility of a cable based connection

The UMRBus over PCIe MGB connection is similar to the PCIe paddle board version for the HAPS-DX and works for the HAPS-70 via a flexible cable setup. This connection method can also be used on the HAPS-DX and delivers similar performance of over 400MB/s.

We provide example designs showing how each of the UMRBus connection modes can be used as well as integration with the prototyping software tools including the new ProtoCompiler and ProtoCompiler DX. This makes any of the modes super quick to deploy.

So as you can see, lots of options to connect HAPS to a Host for advanced prototyping.

(I’m off on vacation for two weeks, so sorry, I doubt that I’ll blog during that time.)

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One Response to “Speeding Prototype to Host Connectivity”

  1. Mick Posner says:

    As a side note, we also provide example designs which enable a native PCIe end point to be integrated quickly into the HAPS prototype. The advantage of native PCIe is that the DUT can be transparently memory mapped across the PCIe bus onto the host. This mode is typically used for IP validation and early software development before the rest of the system RTL is available. The disadvantage is that this solution requires the user to modify the hardware interface to the PCIe block themselves to match the DUT requirements. The user also needs to create the C API themselves as it also needs to be tailored to the application.

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