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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

HOW TO: Achieve Fastest Time to Operational Prototype and Highest Performance

Posted by Michael Posner on July 24th, 2014

Road runner the bird, not the cartoon

If you didn’t know the above picture is of the greater roadrunner (Geococcyx californianus). Trust me I didn’t just make up the Latin name. The Latin name means “Californian earth-cuckoo”. This blog is about how to achieve the fastest time to operational prototype, accelerating ASIC and SoC verification, speeding validation and the road runner was first image that popped into my mind when I wanted to articulate fast. There has been a lot of talk about Time To First Prototype, TTFP, recently so I thought I would blog a how to on achieving accelerated TTFP. I thought I’d raise the bar and deliver a how to on both achieving this AND get the highest operational performance out of the FPGA-based prototype.

If you have found yourself reading this blog you are looking for the magic solution but I am afraid I have to burst your bubble, there is no black magic solving this problem.

Home made no back magic logo

It’s better, all you need is a fully integrated FPGA-based prototyping solution. Yep, that simple, blog done, thank you :) (What? You want to know why an integrated solution solves all your problems!) To answer this we need to quickly review the challenges to FPGA-based prototyping. The below picture describes the challenges to prototyping, based on a recent survey that Synopsys ran. It also includes on the left the solutions to these individual challenges.

Click on the images to view the whole picture. I made them large so they were easy to read.

Survey results defining the challenges of FPGA-based Prototyping and the combined HW/SW capabilities needed to solve them

Do you spot the common theme? The challenges cannot be solved with hardware or software alone, it’s the combination that solves the problem. An example is performance, I’ve blogged about this is the past that it’s the combination of hardware interconnect flexibility and the ability to deploy a high speed time domain, differential signaling, solution that is the key to achieving the highest performance. In this case the software has to have intimate knowledge of the hardware, it’s electrical and SI characteristics to be able to correctly implement the high speed time domain IP in the multi-FPGA prototype design. At the same time ALL hardware must meet a minimum level of performance across all interconnections to ensure that when the prototype design image is deployed across many systems it always runs reliably.

Summary examples of what integrated capabilities are of the Synopsys solution

Debug is another good example. To deliver the highest debug visibility you need both a software flow that enables instrumentation of the RTL, graphical display AND hardware capabilities to store the physical data. The result of integration reduces your need for expertise as the solution has the expertise. Same for partitioning across multiple FPGA’s, as the software is hardware aware and the hardware can be tailored to the software recommended best interconnect topology the result is optimal.

Lucky for you, Synopsys delivers a fully integrated solution of ProtoCompiler plus HAPS so you don’t have to wait. And… if you call now, not in 5 minutes but now, I’ll personally visit your site to say hello.

Synopsys' integrated FPGA-based prototyping solution including ProtoCompiler software, HAPS FPGA-based hardware, debug, DesignWare IP, Support, HAPS Connect Program

While ProtoCompiler was only recently launched its delivering some fantastic customer results, see below, accelerating time to first prototype and delivering the highest performance. This was a customer design, 48 Million ASIC gates, four Xilinx Virtex-7 FPGAs. ProtoCompiler is fully integrated with HAPS leveraging its strengths. HAPS interconnect can be tailored based on the ProtoCompiler recommendations and ProtoCompiler understands the HAPS architecture and resources such as clocks and resets. ProtoCompiler is built around a stable code base of Synopsys’ mature and unique compilation and synthesis engines delivering the highest QoR for out-of-the-box results.

Synopsys achieves fastest time to prototype and highest performance operation with ProtoCompiler plus HAPS

A fully integrated solution delivers not only accelerated time to first prototype and highest performance but also reduces your effort as it’s doing the hard work for you. Just don’t tell your boss otherwise he will give you more work.

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2 Responses to “HOW TO: Achieve Fastest Time to Operational Prototype and Highest Performance”

  1. Mick Posner says:

    Readers: Let me know if you like the large format images that you have to click on OR if you prefer smaller?

  2. Input from readers was 50/50 in respect to large format pictures vs. smaller ones. Some like the large format as it made them easier to read on mobile devices. Others said that they liked the smaller ones as you don’t need to click on the picture to see the whole image. Apparently you can even set it up (with more effort) that you have a smaller picture embedded and the click will bring up the bigger version. I’ll work out how to do this in a future blog. Thanks for the input