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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Top Secret IP Accelerated Testing

Posted by Michael Posner on June 6th, 2014

IP-Accelerated

Synopsys’ big press this week from DAC was the announcement of the IP Accelerated initiative. As this initiative combines Synopsys’ leading interface IP, DesignWare, HAPS FPGA-Based Prototyping systems and Virtual Development Kits as you might guess I have been very involved in this evolutionary development. I executed my own personal top secret testing of the deliverables, more on that later in this blog. I’m so happy that we have finally made this initiative public as I have really wanted to talk about it.

Highlights from the press along with my personal comments on each of the bullets

  • The IP Accelerated initiative augments Synopsys’ leading IP portfolio with new IP prototyping kits, software development kits and customized IP subsystems

Synopsys has taken an evolutionary step and will be delivering packaged subsystems for DesignWare IP with HAPS FPGA-based systems for immediate prototyping productivity, virtual development kits enabling pre-RTL early software development. These DesignWare IP reference subsystems also enabling rapid customization for application specific needs. Customers demand high quality IP where the digital RTL controller has been validated against the mixed signal PHY and Synopsys has always delivered this value. The IP Accelerated initiative delivers the DesignWare IP packed up in a reference subsystem. The subsystem enables Linux to be booted immediately, no effort from the user, and includes the DesignWare IP software drivers. These subsystem references enable the IP users to be immediately productive with either early software development for the select IP. For the hardware or prototyping engineers these subsystems deliver a fully operational prototyping reference which can be used to explore the IP capabilities and accelerate the bring-up of an SoC level prototype.

  • The DesignWare IP Prototyping Kits include a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers

Wow, it’s like the Synopsys R&D engineers have been reading my blog and have implemented a hugely scalable IP prototyping subsystem enabling immediate productivity and a flow for streamlining IP to SoC prototype bring up.  I urge you to watch the videos, especially the demo as it’s amazing to see Linux boot so fast and see the IP operating under a real OS.

  • The DesignWare IP Virtual Development Kits are SDKs that include a processor subsystem reference design, a configurable model of the DesignWare IP as well as a Linux software stack and reference drivers

These deliverables are targeted at the software engineers who want to start there customization of the DesignWare IP drivers targeting their specific application. The advantage of the SDK is that they do not require RTL, they are highly portable and very fast. The advantage of the hardware based DesignWare IP prototyping kits is that they include the prototyping model of the DesignWare IP RTL so cycle accurate and physical real world IO enabling compliance and interoperability testing. Software drivers developed on the SDK can be executed on the real hardware to validate their operation in real world scenarios.

  • For hardware engineers, the IP Prototyping Kits provide a validated IP configuration that can be easily modified to explore design tradeoffs for the target application
  • For software developers, both the IP Virtual Development Kits and IP Prototyping Kits can be used as proven targets for early software development, bring-up, debug and test

These are self-explanatory, basically you are productive immediately. Even an engineer with no previous IP, FPGA-based or virtual prototyping experience can use them.

  • To reduce risk and accelerate time to market, Synopsys experts can assist designers in creating and customizing IP subsystems for their specific application requirements as well as integrating the subsystems into their SoC

The deliverables are packaged as a reference but as the IP is highly configurable enabling it to be tailored to application specific needs it’s expected that the deliverables will be modified for specific project usage. Some of this customization is enabled directly in the kits and the Synopsys experts are there to help with this task.

As mentioned above, I have been personally involved and took on a top secret project as a test pilot. You can see the summary of the top secret testing here: https://www.youtube.com/watch?v=WN-ZsLK_IZw

IP_Accelerated_Initiative_test_pilot

Do you have a question on the IP Accelerated Initiative? If yes, post me a comment and I promise to respond.

I was at DAC this week, I’ll write up that fun next week

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2 Responses to “Top Secret IP Accelerated Testing”

  1. Dee Mehta says:

    Very interesting and well written article. I was not able to view the video and not sure what happened. Thank you
    Best regards,
    Dee Mehta