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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Superior debug visualization and efficiency

Posted by Michael Posner on October 26th, 2013

I noticed that Synopsys launched the new Verdi3 which provides the capability to debug both the hardware RTL code and the Software C code. Here is a video demo of the new capabilities: http://www.synopsys.com/Tools/Verification/debug/Pages/verdi-hw-sw-debug-video.aspx

Verdi3 addresses the need for a simultaneous view of both hardware and software languages enabling designers to efficiently and effectively advance their debug productivity. So call me a geek but I think this is way cool. I think it’s so cool as I see this as a key new technology which will really benefit designers doing FPGA-based prototyping. The reason I say this is that FPGA-based prototyping is when you are executing key software modules against the hardware aiding in hardware validation and hardware/software integration. Having combined hardware and software debug visibility is going to help you track down the source of the bug much faster.

This is one of the key challenges engineers talk to me about. FPGA-based prototyping gives you the ability to run software against the hardware but when you do run into an issue it can sometimes take a long time working out if the issue is a result of hardware or the software. I’ve seen this at interoperability plug fests where we have the DesignWare IP running on HAPS enabling the IP to be put through the full interoperability testing. Many of the DesignWare IP’s are a combination of the hardware RTL and a software driver. When we run into an issue we have to quickly work out if the error source is our RTL, our software or the component that we are testing interoperability against. Historically we have used a mix of FPGA-base prototyping hardware debug tools such as Synopsys’ Identify and off-the-shelf software debuggers. I am sure we will be looking at utilizing the new Verdi3 in the future.

While we are talking about Synopsys’ Identify did you know that it includes an interface for Verdi? Well it does, extending the great Identify at-speed FPGA-based debug capabilities to Verdi (and visa-versa)

From Verdi you can write out a list of points that you want to add debug visibility and Identify uses this to instrument the RTL. Verdi can be used to automatically create a list of “essential signals” for a block or module. This list of essential signals is the minimum set that Verdi needs to provide 100% debug visibility to the module. Verdi does not require you to log all points as it can re-build the logic state of the others as long as it has the details of the essential signals. This is an amazing feature when added to the FPGA-based prototype. Logging just the essential signals minimizes the FPGA logic utilized for instrumentation while at the same time providing 100% visibility for debug.

The FPGA-based prototype runs at hardware speeds and Identify captures the signal trace data. Once you are finished you then simply export the Verdi FSDB for post processing.

The integration between Verdi and Identify is just one of the many debug capabilities that the engineers have at their fingertips. When using HAPS as the hardware platform you can combine the use of the HAPS Deep Trace Debug with the Verdi support providing the capability to store a huge amount of signal trace data.

Wow, how did this happen, this blog got huge (its Saturday morning) Do you do FPGA-based prototyping? (yes because you read my blog) Do you have access to Verdi? If the answer is yes I would like to hear about your experience in combining the two enabling superior debug visualization and efficiency.

Only lame spam this week. Well all spam is lame but this week was really lame.

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