Posted by Michael Posner on October 11th, 2013
This week I was asked to compare the Synopsys HAPS systems to FPGA vendor evaluation boards. I only have good things to say about the FPGA vendor evaluation boards but when comparing these evaluation boards to HAPS for serious FPGA-Based Prototyping I just said, “That’s like using a hammer to put in a screw”. A hammer is a great tool but it’s not the right tool for the job. Evaluation boards are not designed with FPGA-Based prototyping in mind, they are designed to enable evaluation of the individual FPGA devices capabilities. “Evaluation” board, not FPGA-based prototyping system. HAPS is architected with the FPGA-based prototyping in mind and provides the capabilities to increase the customer’s productivity. Our goal is to improve the customer’s efficiency by providing out-of-the-box capabilities which the customers can deploy immediately. To meet the demands of FPGA-based prototyping the customer would need to hand craft such capabilities for an evaluation board and then internally support it’s usage which detracts the customer from the important tasks such as early software development, hw/sw integration and creating product differentiation.
<- DON’T USE THIS WITH THESE ->
Then of course I was asked to explain and provide a couple of examples of what FPGA-Based Prototyping capabilities are. Below are just a couple of the examples:
The evaluation board has no reuse when going from standalone IP to SoC level prototype. Pin-outs change, constraints change resulting in duplicated effort between IP and SoC teams. With HAPS this flow is streamlined as each system is designed with expansion in mind.
The evaluation board has no built in debug capabilities, HAPS offers deep trace debug with support for Synopsys’ Verdi/Siloti for deep and wide visibility. Speeding up the debug process will make the teams more productive. HAPS also includes support for Real Time Debug providing automated setup of a logic analyzer which is used to capture almost infinite debug data. Improved debug efficiency for the customer’s teams increasing productivity.
The evaluation board is typically delivered with a version of the vendors synthesis tool which has no dedicated prototyping capabilities. The HAPS prototyping software tools deliver prototyping capabilities such as gated clock conversion, clock optimization, fast synthesis and prototyping diagnostic compiler. These capabilities will ease the flow from RTL to operational prototype making the customers more productive.
The evaluation board offers no hardware flexibility (similar point to the one above for IP to SoC). The evaluation boards only offers a rigid hardware architecture forcing the DUT to have to be force fit to it. HAPS provides a flexible hardware architecture with FPGA-based prototyping capabilities and reuse across multiple projects. As an example, if an interface is used on the evaluation board that’s great but if it’s not used then it’s a wasted resource tying up IO’s. HAPS enables higher return on investment for the customers ensuring the hardware can be utilized across multiple groups and projects.
The evaluation board has no built in Hybrid prototyping support. HAPS offers a complete solution for Hybrid connectivity including native Universal Multi-Resource Bus, UMRBus connectivity and supporting API. The UMRBus also streamlines the creation of custom application widgets for tasks such as pre-loading memories, initializing registers and debug and protocol monitors. The UMRBus includes complete host software application programming interface and hardware interface modules for rapid deployment of the UMRBus capabilities.
HAPS delivers an on-board supervisor enabling remote access and HAPS-Aware query and system check capabilities. These capabilities ease the use of HAPS and provide a mechanism to check the system setup before deployment ensuring immediate productivity.
Like I said, evaluation boards play an important role enabling you to evaluate an FPGA devices functionality. However an FPGA-based prototyping system such as HAPS offers tailored capabilities which are required to successfully prototype an SoC.
No fun spam this week