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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Hitting Your Milestones

Posted by Michael Posner on August 21st, 2013

This week I had to explain why FPGA-based prototyping is used. (I had to remind myself that not everyone lives and breathes FPGA-based prototyping day in day out like I do) The explanation was for an exec so I had to ensure the explanation was clean and sharp. I simply said “FPGA-based prototyping helps you meet your milestones, both for hardware development and the software development”. This caught their attention so I expanded the answer with

FPGA-based prototyping enables:-

  • Early software development. Parallel development. Don’t wait for silicon to come back, start software development against an accurate and high speed model of your SoC. (Hit your software milestones)
  • Hardware/Software integration. This is going to flush out both HW and SW bugs which could have resulted in a product limitation or worse a silicon re-spin. (Hit your integration milestones)
  • System Validation. Validate that the whole product meets the users needed. Test interfaces for compliance and interoperability with off-the-shelf hardware, demonstrate the design to your customers early. (Hit your system product milestones)

Great they said, we will take 1000…….. The value of FPGA-based prototyping is clear and it’s why over 70% of SoCs are prototyped.

Even with all this prototyping going on the #1 reason for re-spins is still hardware functional issues based on SNUG survey data. This says to me that not all of the design is being prototyped and bugs are going undetected. This has been the case as until recently FPGA capacity limited how much could be modeled. With products like the HAPS-70 supporting 144 Million ASIC gates finally you can model more of the SoC including multi-cores and big blocks such as GPUs. Model more of the SoC means you can validate more of the capabilities, more HW/SW coverage and lower risk.

To date customers have deployed over 350 HAPS-70 units, that’s many happy customers who we are helping to meet their milestones.

How has FPGA-based prototyping helped you?

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