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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Understanding IP and IP to SoC Prototyping

Posted by Michael Posner on July 18th, 2013

I’m presenting at the quarterly GSA Intellectual Property (IP) Working Group Meeting this morning and while reviewing my slides I thought I would blog on a couple of aspects of IP (RTL blocks) and IP to SoC Prototyping. I’ve blogged on this topic before but it was ages ago and even I’ve forgotten what I spoke about.

The first is what I like to call the other three laws (not to be confused with the FPMM three laws, who can remember what they are?)

  • IP and SoC level prototypes require different capacity solutions
  • IP and SoC level prototypes require similar capabilities
  • IP prototypes need to be rapidly integrated into SoC level prototypes

 Simply put, RTL IP blocks maybe a small fraction of the whole SoC but when you FPGA-based prototype them the only requirement that changes is the capacity (ASIC Gates) of the solution you use.

Thinking about everything I want to write about I think this is going to turn into a blog series as it’s too much for one blog. Yay, that makes the next couple of weeks easy for me.

As mentioned, regardless of the size of the block being prototyped you still need high performance operation, you still need a flexible solution which can be tailored to your designs needs, you still need debug capabilities and an easy to use implemtation tool flow. You can of course get away with less but that just makes your validation and software development task harder and we all have it tough enough already so we strive for an easy life.

Lets start off with looking at the RTL Block/IP prototyping use modes. As usual FPGA-based prototyping of RTL blocks is not done the same way every time but I have been able to create three groupings to help explain how these blocks are typically handled. The three buckets are:- Standalone, PCIe connected and Hybrid.

What I am calling standalone is by far the most popular and easiest use mode to understand. The PCIe connected prototype is the second most popular use mode with the Hybrid prototype being the newest and emerging use mode.

Based on these buckets which use mode do you use for your RTL block/IP prototyping?

In the coming weeks I will explain each use mode in detail and provide tips on structuring the smaller prototyping design so that it can be easily integrated into the larger SoC level prototype.

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