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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Standalone Validation & the Wow Factor of Turbo Antilag

Posted by Michael Posner on July 24th, 2013

Continuing on my theme of RTL Block/IP validation I wanted to discuss the most popular and typically the most well understood usage mode, Standalone.

The characteristics of a setup with define usage as standalone is well….. it’s standalone…… In a typical standalone setup the DUT is being stimulated by real world input and it’s generating some type of real world output. A good example of a standalone prototyping setup is the DesignWare MIPI demo of CSI/DSI. (Video: http://www.synopsys.com/dw/ipdir.php?ds=mipi_csi2 ) The real world input is a MIP camera and the real world output is a MIPI compliant display. The design under test in this case is both the DesignWare CSI and DSI digital controllers implemented on the HAPS FPGA. The DesignWare DPHY is being validated as part of this setup as well as they are utilized to facilitate the physical electrical interface with the test chips mounted on HAPS daughter boards.

Within the standalone setup a processor may or may not be used depending on the DUT. In many cases a processor is implemented as part of the prototype that controls the configuration of the DUT. In the case of the above example I remember that a processor is used which executes a light software layer enabling software control of the IP’s dynamic configurations. The code is controlled and debugged via a simple JTAG connection.

The DUT is being immersed in real world stimuli identical to how it would be when utilized in a full SoC design. This is why it’s validation! you confirm that the DUT does what it’s supposed to do and that it meets user requirements. In the case of our example video in and video out, you see the results.

A requirement of a standalone prototype platform like this is that it has to be high performance to support the real world interfaces which typically have minimum clock frequencies.

The standalone setup can be used for HW validation in addition to HW/SW integration and or course as a platform for continued SW development. These usage modes make the standalone prototype highly useful across hardware, software and system design teams. This is why the standalone use mode is by far the most popular and well understood usage mode.

Next week I’ll discuss the PCIe connected modes and introduce the “Loop Concept” exciting right!

And for those of you who only read my blog for the “non” FPGA stuff here is a link to a video of me having a little fun at The Ridge Motorsports Park in my 450 WHP Subaru: http://www.youtube.com/watch?v=1Cn79GSTfXc (This was why last weeks blog update was on Thursday, I was doing this on the Friday) You will have to take my word on it that in fact it’s more fun to do than watch on video. Here is another video from a while back of me tuning what is known as the “Turbo Anti-lag” system on my Subaru: http://www.youtube.com/watch?v=Ppv3EMGlITY  

I don’t use the antilag system very much as it’s pretty hard on the engine components but when I do it certainly brings a smile to my face and shock and awe to onlookers. Fast n Furious yo….

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