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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Prototyping the Ubiquitous or should we say infamous USB 3.0

Posted by Michael Posner on May 13th, 2013

Follow up from last week’s blog…… http://blogs.synopsys.com/breakingthethreelaws/2013/05/high-speed-io-and-the-cloak-of-invisibility-strikes-again/

Kirk Saban of Xilinx answered my question of why the line rate of the -2 2000T silicon is 10.3125. Kirk states:

10.3125 Gb/s is the line rate required to support 10 Gb Ethernet which requires 64b/66b encoding. (10Gb x 66)/64 = 10.3125 Gb

I would have been surprised if Kirk got this wrong as he is the Product Manager for the V7 FPGA’s. Kirk then goes on to challenge us with a follow question:

I will follow up my answer with an additional question… what speed grade of 7V2000T is required to support 12.5 Gbps!?

You would have thought the answer is the “-3 part” but you would be wrong as there isn’t a -3 part. The correct answer is the -2G part. I found the following text in one of the Xilinx datasheets which confirms the -2G part

Thanks to Kirk for answer the question and enlightening us on the -2G part. For this honor Kirk gets to buy me dinner and drinks the next time I’m in CA.

USB is everywhere; even my fridge has a USB port. Last week I asked a non-tech-savvy person if they knew what USB actually stood for. They didn’t know, they just knew that it’s everywhere and mostly works out of the box. (Universal Serial Bus for the non-tech-savvy readers). While USB is everywhere it still presents a challenge to FPGA-based prototypers as the various interfaces have minimum frequency requirements and timing constraints between RTL controller and mixed signal PHY. I ran across a great write up by John Kuhns, Design Consultant, Synopsys Professional Services, in this month’s DesignWare Technical Bulletin, http://www.synopsys.com/Company/Publications/DWTB/Pages/default.aspx

Here is a link directly to the article: http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-usb-prototyping-2013Q2.aspx

John provides insight on how to get your HAPS-based prototype up and running in a short period of time by taking advantage of solutions such as a implementing a simple USB device driver written in C and a WINUSB-based host driver to facilitate testing. Nice work John!

Coincidently Synopsys just launched the USB University, http://www.synopsys.com/IP/Pages/usb-university.aspx If you are new to designing with USB, or looking for tips on implementing USB 3.0 IP, Synopsys’ USB 3.0 University has a session for you. From a basic USB overview, to implementing USB on FPGAs, to top-level synthesis, you’ll find the information you need in this instructional video series.

Off subject does anyone know which year Pacman the video game was launched?

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