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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

High Speed IO and the cloak of invisibility strikes again :(

Posted by Michael Posner on May 7th, 2013

Last week I discussed the occurrences of the cloak of invisibility in respect to my black truck and trailer as well as HAPS. Well fate was unhappy with me exposing the truth about the existence of the cloak of invisibility and sent me a message

Yes, last week someone drove into my car hauling fully enclosed trailer. Ouch. No one was injured but I was spooked by what the other drive said when I asked what happened, their response

I didn’t see you

Come on now, it’s a 25 foot long fully enclosed trailer that blocks out the sun. Maybe that’s the issue, maybe it’s really a black hole in disguise and the other driver was sucked into it !!!!

Last week I was asked if the Xilinx transceivers, the high speed serdes capable pins, were available on the HAPS-70. The answer is yes, we make 16 lanes of the transceivers available per FPGA across two multi-gigabit (MGB) connectors. The MGB is a generic connector meaning that the user of the HAPS system can either use an off-the-shelf MGB daughter board from Synopsys or build a custom MGB style daughter board to access the transceivers. Synopsys provides off-the-shelf MGB daughter boards for PCI E, SATA and Ethernet. The transceivers support a wide range of different protocols.

Here is an example of the Synopsys PCI MGB daughter board

Here is an example of the MGB access riser. A user would build a MGB daughter board to either plug into this of bypass it and go straight into the MGB connector itself.

Different from the previous “T” Xilinx FPGA variants the Virtex-7 2000T’s speed grade changes the max speed of the transceivers. The -1 part supports up to 6.6 Gb/s while the -2 part supports up to 10.3125 Gb/s. Does anyone know why it’s 10.3125 Gb/s? I do but if you know the answer make a comment below and I’ll ensure you are written up as a star in my next blog.

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One Response to “High Speed IO and the cloak of invisibility strikes again :(”

  1. Kirk Saban says:

    10.3125 Gb/s is the line rate required to support 10 Gb Ethernet which requires 64b/66b encoding. (10Gb x 66)/64 = 10.3125 Gb

    I will follow up my answer with an additional question… what speed grade of 7V2000T is required to support 12.5 Gbps!?

    Kirk