Posted by Michael Posner on April 5th, 2013
Over coffee this morning I found myself thinking about virtual prototyping. Blasphemy you say, Mick is hard core FPGA-based prototyping and he would fight till the death and his cold lifeless body was rotting on the battlefield. (Yes, this blog is 18+ Rated today). The reality is that virtual prototypes, such as Virtualizer, are complementary to FPGA-Based prototyping.
Virtual prototypes are not reliant on the availability of RTL so can be used far, far, far earlier in the design cycle. Much software is independent of physical implementation so you get a huge advantage from developing a virtual prototype enabling software development to start early. Because you model the system at a higher level of abstraction you get high performance as well.
On the flip side, virtual prototypes don’t use the physical RTL so it’s only a close representation of the target system, not the system itself. This is the value of FPGA-based prototypes, such as HAPS, they utilize as much of the actual RTL as humanly possible. The FPGA-based prototype is as close as you can get to the real system. Some say (incorrectly) that partitioning and pin multiplexing adds a level of complexity and error. The fact is with new automated techniques offered by tools like Synopsys’ Certify the partitioning and insertion of pin multiplexing logic is transparent to the user and error free.
Then sitting in the middle is Hybrid Prototyping, merging the best attributes of both technologies.
Both technologies play a critical part of the design cycle.