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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

FPMM Downloads surpass 3500 copies, do you have a copy?

Posted by Michael Posner on March 29th, 2013

Wow, the free ebook download of the FPGA-based Prototyping Methodology Manual has surpassed 3500 downloads. The PDF version has been downloaded over 2800 times in addition to the Epub and Kindle version at over 500 times each.

We have collected over 2800 surveys from the users who requested the download. As expected the #1 downloader of the FPMM is hardware engineers. These engineers are living and breathing FPGA-based prototyping so get immediate value from the FPMM’s guidance.

Based on this survey data the top challenges these engineers face still fall into the categories of ease of use, debug and performance. In the below data you can see mapping the ASIC into FPGA and clocking issues as the #1 and #2 challenges. Both of these are in the category of ease of use challenges and these barriers need to be crossed before you can get an operational FPGA-based prototype and become productive. This is where the Synopsys Certify multi-FPGA prototyping environment helps. Certify automates many of the steps needed to condition ASIC RTL ready for the FPGA-Based Prototype. For rapid bring up, Certify is configured to provide fast turn-around enabling multiple iterations per day as you experiment with implementations.

It’s logical that once you have an operational prototype that the key need becomes debug visibility. The engineers need to debug the initial bring-up of the prototype and function. The Synopsys Identify tool helps here by providing various debug capabilities for system validation and fast turn-around with deep trace storage debug visibility.

Once you have a good stable FPGA-based prototype it’s time for deployment for System Validation and software development. This is why the focus then changes to performance. You know that your software team won’t tolerate waiting around 5 seconds for an OS to boot. Now is the time to configure Certify for full optimization and squeeze the most out of both the FPGA technology and the FPGA-Based Prototype.

Do you agree with these challenges or do you face others? Post a comment and let me know. Oh and sorry for the delay in blogging, I’ve been traveling the world again.

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