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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

How IO Interconnect Flexibility and Signal Mux Ratios Affect System Performance

Posted by Michael Posner on February 15th, 2013

One of the “Breaking The Three Laws” is that your SoC partitioned blocks typically have more signals than physical IO’s on the FPGA. Technically this is not one of the three laws but it should have been and as I own this blog I can make one more up. Welcome to the Breaking The Four Laws blog. During a recent engagement for the HAPS-70 the user wanted Synopsys to create a demonstration proving the HAPS High Speed Time Domain Multiplexing, HSTDM and Certify tool automation capabilities. The challenge; Create a design which passed 1800 signals between four FPGA’s using less than 200 physical IO’s.

As you can see from the block diagram above the 1800 signals would be passed between FPGA’s and compared at each point proving that the transmission and receive of data was valid. This was an easy design to replicate for Synopsys as we create similar designs to qualify the HSTDM operation. Based on the users constrains we were able to achieve the following results

  • System: HAPS-70 S48 (-1 speed grade)
  • #Signals multiplexed per set: 1824
  • HT3 connectors used for signal set: 4 (200 IO’s, 96 differential pairs)
  • HSTDM Ratio: 24
  • HSTDM Frequency: 1.1 Gb/s
  • Resulting System Frequency: 17 MHz

We successfully implemented four fully independent HSTDM channels between four FPGAs, Multiplexing 1824 design signals across four HapsTrak 3 connectors. The user required the use of only four HT3 connectors this results in 96 differential pairs available for HSTDM. Based on the requirement of transferring 1800+ signals this results in a required HSDTM ratio of 1824/96 = 19. HSTDM supports multiples of 8 so a ratio of 24 was used. As stated, using a HSTDM factor of 24, we achieved a design system clock frequency of 17MHz.  HSTDM transfer clock rate is 1.1 Gb/Sec and this is fully operational on the -1 speed grade HAPS-70 S48 system. Due to the use of the HSTDM ratio of 24 we have un-used HSTDM channels in the current implementation which could be used for other purposes if needed.

But wait !!!!!        The HAPS-70 systems has far more available IO and the rule of thumb is the lower the mux ratio the higher the overall system performance. Each HAPS-70 FPGA-module has 23-user HapsTrak3 connector available, if we were to increase the number of connectors and cables used by 1, so a total of 5 HT3 connectors for this (1800-IOs) data exchange, we still have 18 more connectors available.

Our recommendation was that by simply increasing the number of HT3 connectors used per link will result in far higher system frequency. By using one more HT3 connector, so a total of 5 per link, the HSTDM ratio will be reduced to 16. So we implemented it and below are the results

You can also see that we also proved that by using more HT3 links that the mux ratio could be reduced even more, down to 8 resulting in a system frequency of over 24 MHz.

This example shows the advantage of the flexible interconnect of the HAPS-70 systems combined with the HAPS HSTDM technology with the result being one very happy user. For those of you doing FPGA-Based prototyping, are you able to get similar results?

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