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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Globally located R&D enablement, SRAM Daughter Boards & High Speed IO

Posted by Michael Posner on February 5th, 2013

This week I’m visiting one of our R&D teams based in Erfurt Germany. I took the opportunity to take some photos of the HAPS-70 development systems along with a number of the off-the-shelf daughter boards which are available from Synopsys as part of the solution.

First let me introduce Andreas Jahn, R&D Manager pictured above with the HAPS-70 S48 (far left), HAPS-70 S24 (right bottom) and the HAPS-70 S12 (right top).Note that the HAPS-70 S12 is connected to the Universal Multi-Resource Bus, UMRBus, by the blue Control and Data Exchange cable. The UMRBus enables the system to be access remotely. This is a key capability enabling global accessibility which is important to Synopsys as we have both local teams and remote teams working with the development systems. Just like Synopsys, many customers have globally located teams handling all sorts of tasks such as hardware validation and software development. The UMRBus enables the HAPS systems to be globally accessed meaning that locally based hardware is not required.

Below is a picture of one of the HAPS-70 S48 systems in use for SRAM daughter board testing. The SRAM daughter boards are located on the left side of the system, multiple are installed and a number are stacked up on top of each other.

Tests were being executed against these SRAM boards, again, all controlled via the UMRBus. The Identify team were using these SRAM daughter boards to continue development of the HAPS Deep Trace Debug, HDTD, capability.  HDTD provides off chip storage for debug sample data meaning that you are not reliant on FPGA devices on-chip memory. HDTD enables a large window, 100x or more when compared to on-chip memory, of debug data to be stored. On the same system you can see that many links have been configure with the high performance coax cables. This system was setup to mimic a customer design and their expected interconnect between the FPGA’s. This was setup to prove that many thousands of signals could be passed across a very low number of physical interconnect IO’s utilizing the HAPS High Speed Time Domain Multiplexing, HSTDM. As HSTDM is automated as part of Certify it was easy to setup a design and validate the HSTDM operation for this specific example.

Finally above is a zoomed in picture of the Multi-Gigabit, MGB, riser and adapters for both PCI Express and SATA. The HAPS-70 enables direct access to the Xilinx devices native transceivers. As part of the solution Synopsys offers a set off-the-shelf MGB daughter boards which link the transceivers to a standard connector. Nice view of the user panel which houses the SD Card which is used for standalone boot configuration. This mode is liked by the software developers as they can quickly load the new build images from their hardware team. Just load the SD card and plug it into the system.

If you spot anything else in the pictures that you want to know about ask the question via the comments

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