HOME    COMMUNITY    BLOGS & FORUMS    Breaking The Three Laws
Breaking The Three Laws
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Everyone loves cool hardware, especially me….

Posted by Michael Posner on February 28th, 2013

Over the last couple of weeks I’ve been chatting about the various capabilities of the HAPS-70 solution and how it directly improves the FPGA-based prototyping experience. Now have a look at the system hardware and software in this short video introduction to the HAPS-70.


I’ve also blogged a lot about the HAPS-70 S48, our 48 million ASIC gate solution but not much on our smaller S12 and S24, 12 million and 24 million ASIC gate solutions. The S12 and S24 utilize the same modular and flexible architecture, UMRBus capabilities, supervisor software and software tool flow chain.

If we look at the S24, above, I’ll remind you that there are no embedded traces between the FPGA’s. This is a huge advantage for the S24 as the typical use case for such a system is a processor subsystem in one FPGA and the DUT subsystem in the other FPGA. With such a setup many signals need to be past between the FPGAs and this is of course where the flexible interconnect architectures strength is. An example of this is say we have a setup that requires ~300 IOs for daughter boards, which is six HT3 connectors, the remaining 17 are free to use for inter-FPGA connections, that’s 816 (17 * 48) raw IO’s. On its own that’s a tonne (I’m working in metric today) of signals. Now factor in the use of HSTDM at say a ratio of 8 and you can support 6528 ( 816 * mux ratio of 8 ) signals between FPGA’s. That’s HUGE.

In other cases the prototyping design is external IO intensive but the actual DUT is pretty small compared to a complete SoC project, enter the HAPS-70 S12. The S12 includes 23 HT3 connectors providing the maximum IO available for daughter boards, external IO and connectivity to other systems. Picture a small subsystem being modeled, the S12’s IO can support the use of multiple daughter boards such as SRAM, DDR3, Flash, UART, custom application specific daughter boards, DesignWare PHY test chip boards and more. All these plus a connection to Ethernet, SATA or PCI Express via the available MGB connector accessing the on-FPGA transceivers.  Oh and lets not forget that you can still utilize the UMRBus connection with it’s zero pin overhead to monitor and interact with the prototype.

The S12 is also a key building block for the “cloud” systems. Buzz word alert !!! The HAPS-70 systems can be chained to create higher capacity systems. The chaining is done utilizing a simple supplied cable we call the CDE, Command and Data Exchange cable. This chains configuration and synchronizes clocks so that while physically you are linking multiple systems the cloud of systems acts and is seen as one unified prototyping project. Partition the design across the multiple FPGA’s just like they were all in one unit. Below are the form factor cheat sheets describing the base systems as well as the cloud systems. I should note that the S144, 144 million ASIC gate system is missing just because I could not fit it all nicely into one page.

Funny, I had originally thought I was only going to blog the HAPS-70 introduction video… wow I got wordy this morning…. Oh, ate chicken salad at the Hilton Garden hotel in Mountain View CA, very nice J

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn