HOME    COMMUNITY    BLOGS & FORUMS    Breaking The Three Laws
Breaking The Three Laws
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Direct Route or Take the Bus?

Posted by Michael Posner on February 22nd, 2013

Last week’s blog was on direct interconnect density and the effect it has on pin mux ratios. The example focused on using HSTDM but one of the readers correctly pointed out that interconnect density effects any pin muxing scheme, not only HSTDM. The rule of thumb is the greater the density of interconnect routes the lower the possible mux ratio can be. This is a HAPS-70 hardware strength as the interconnect can be tailored to create greater route density just where you need it.

So that’s direct interconnect routes but what about busses? Take a typical SoC as below

The SoC infrastructure defines a logical partition which could be mirrored on the FPGA-based prototype. In its simplest form you would assign each block to an FPGA and mirror the interconnect. The HAPS-70 flexible interconnect architecture again enables you to tailor the system to match the SoC specific interconnect. Of course in reality you would combine multiple blocks into each FPGA. Regardless there are occasions where busses (sometimes known as multi-drop connections) are required.

When first looking at the HAPS-70 the conclusion could be drawn that all connections are point to point and that busses are not supported……… Well of course that conclusion would be wrong. Enter the breakout board !

The breakout board plugs into the HAPS-70 system HT3 connector and connects that single HT3  to two HT3 sockets. Basically it creates a “Y” connection. This simple concept enables a bus to be routed around as many FPGA’s as you like. The example below shows how you create a bus of 48 IOs across four FPGA’s. (Bought to you via my amazing whiteboard skills)

It’s easy to see that with the use of a third breakout board and high performance coax cable that the bus could be extended to five FPGA’s and so on for more. Creation of a wider bus just requires the use of more breakout boards and cables. The bussed connections have matching timing characteristics due to the fact that the HT3 connectors are 1-1 bank matched with both the Xilinx IO bank and the SLR region of the 2000T device. Uniform timing as you are not crossing banks or SLR’s.

On a random topic I used to eat chicken wings everywhere I travelled to. Over the course of 18 years of business travel I ate spicy wings at almost every dinner. I wish I had written a book about it. Not a boring book rating how good the wings were (or bad) but about the quest itself. I would have called it “Wings around the world” catchy title right! I had a lot of fun on the drives, walks, trains and busses while on the quest for the wing. Well that era is now over, for some strange reason I gained 30 Lbs over the last years. Maybe, just maybe, the wings had something to do with this. Anyway it’s lean chicken and salad from now on. Can anyone make up a catchy title for the book that I won’t write on my new quest for the salad?

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn