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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Improving Ease of Use for FPGA-Based Prototyping

Posted by Michael Posner on December 14th, 2012

Traditionally ease of use for FPGA-based prototyping was all about how long it took to go through FPGA synthesis and FPGA place and route. Easy was defined as faster through the flow. With advances in Synopsys’ Certify and Synplify tools adding incremental compilation methods, multi-processing & fast synthesis specifically for FPGA-based prototyping the impact of “bit” file turn-around has been dramatically reduced. With that part of the problem solved the term “ease of use” is now used to represent more than just the implementation tool flow. The ease of use phrase has been extended to include the complete usage flow from first bring up to deployment for HW/SW Integration, System Validation and SW Development.

With the introduction of the HAPS-70 systems Synopsys now offers a new System Query and System Check capability which improve the ease of use of the solution.

The HAPS System Query jump starts the creation of a prototyping project based on a specific physical configuration of the HAPS system. The example being you already sort of know how many systems will be used together, how many and what types of daughter boards are needed and the sort of interconnect topology that is best suited for your design. With the new HAPS Query you can “build” the physical system placing the daughter boards and cables on the system and then via the UMRBus have the HAPS tools build you the prototyping project template based on the physical implementation. This template is then used as part of the Certify multi-FPGA prototyping flow to jump start the activity. Super easy right.

The HAPS System Check is targeted at the deployment stage. I’ve heard so many horror stories of remote teams taking weeks to become productive as they had been debugging a problem which was caused by an incorrectly configured system or incorrectly placed daughter board. No joke, I was told that one team took almost two weeks to bring up a system as no one noticed that a daughter board had been placed on the wrong set of connectors. The engineer was looking at the picture of the system basically upside down.

 The HAPS-70 systems include a System Check capability. The use mode of this capability is to validate the physical connectivity and performance of the system interconnect BEFORE you load your user design. In essence system check is a set of debug capabilities targeted at ensuring the system has been setup according to your project and that everything is operating correctly. If the system passes these checks then you can be assured that you are debugging your design and not the FPGA-based prototype itself. System check will identify where daughter boards are located and check that the voltages have been applied correctly. System check can validate the cable interconnect topology and run a performance check to ensure that all connections are electrically good and meet the requirements defined in the users project. These system check capabilities can be interactively run via a GUI or scripted.

 IMO this makes the systems not only easier to use but assures stability which is essential in a production project environment.

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