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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Konnichiwa from ET/EDS Fair

Posted by Michael Posner on November 19th, 2012

Last week I attended the Embedded Technology and Electronic Design Solutions Fair in Yokohama Japan. We showcased the newly launched HAPS-70 FPGA-based prototyping systems. It was a great show, really busy.

Below you can see the HAPS-70 on display with a sample of the high performance coax cables that are used to create the design specific interconnect between FPGA’s.

The advantage of the cable based interconnect is the user can create higher density connectivity (example below) where their design needs it the most. The granularity of the HAPS-70 interconnect also means less I/O waste unlike what is typical with a fixed PCB trace based interconnect. The coax cables are spec’ed to very high performance and combined with the Synopsys High Speed Time-Domain Multiplexing, HSTDM, capability they deliver the highest system performance. This higher density flexibility matching the designs requirements means that multiplexing ratios are typically minimized, again providing a system performance boost.

In addition to the HAPS-70 display we also had live demonstrations of HAPS capabilities for high performance HD imaging, Hybrid Prototyping and connections to Synopsys’ Processor designer.

Image processing in real time is a requirement for FPGA-based prototyping at many Japanese customers. The HAPS-64 demo used at the ET/EDS fair implements a HDMI video processing block which processes live streaming HDMI 1080p data. The HAPS UMRBus is used to dynamically change the processing blocks configuration resulting in real time manipulation of the video stream. This highlights not only the high performance characteristics of the HAPS systems but the advanced connection capabilities of the UMRBus with HAPS.

Who’s that good looking chap taking the picture?

The Hybrid Prototyping demonstration showcased an ARM-based SoC subsystem modeled in Virtualizer connected to the DesignWare USB 3.0 IP core executing in HAPS. The whole system models a mobile device with USB 3.0 storage. The Hybrid prototype boots Linux and executes the standard USB 3.0 drivers controlling the DesignWare USB 3.0 core. The demo streams a video off the Hybrid storage device and ran continuously looping the video for the full three days of the event. Hybrid Prototyping utilizes transactors for AMBA to create the connection between the Virtualizer Virtual prototype and the HAPS hardware. Hybrid prototyping is very interesting to the Japanese customers as it enables software development for IP blocks to start before the full SoC RTL is available. Being able to test the software against the real world IO early in the design cycle is very valuable.

The connection between Synopsys’ Processor Designer and HAPS demonstrated the debug capabilities that are enabled when the two are used together. A custom PD designed processor is implemented in HAPS and the UMRBus is used to directly connect the PD debugger to the system. The software code running on the custom processor can then be debugged while the system is running at very high performance.

I actually think ET/EDS Fair was bigger than DAC. Are you going to DAC this year?

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