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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Is your FPGA-Based Prototype fast enough for PCI Express Gen 3? HAPS is!

Posted by Michael Posner on November 5th, 2012

I love it when I see real world uses of FPGA-Based Prototyping. The picture below was snapped during the PCI Sig show in July 2012. The demonstration shows Synopsys’ solution for PCI Express Gen 3 all running on the HAPS systems which is actually hidden behind some of the other hardware, just take my word for it.

This is one of the forgotten strengths of FPGA-based prototyping system, the fact that they act as a great demonstration platform. What better way to show a potential customer your product months before silicon is available than a full functional demonstration. This same platform could then be used by said customer to start early software development.

At this point I have to poke a little fun at the PCI Sig. What in the world were they thinking when they decided to use Giga Transfers per second, GT/s !! As I am not familiar with PCI Express I had to research what GT stood for. Why in the world did they not just say 8 Gb/s? Maybe there is a specific reason for it but I cannot work out what it would be. I think I’m going to ask my friend Scott Knowlton, the owner of the “Express Yourself” Blog (A blog all about PCI Express) and see if he knows the background of it. Post me a comment if you know why it’s GT/s and not Gb/s….

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