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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Is it a bird, a plane, No! it’s the HAPS-70

Posted by Michael Posner on November 12th, 2012

Today (November 12th 2012) Synopsys announced the availability of Synopsys’ HAPS®-70 Series FPGA-based prototyping system solutions extending the successful HAPS product line to address the increasing size and complexity of system-on-chip (SoC) designs. The HAPS-70 systems deliver the most comprehensive solution in the industry that combines physical hardware with fully integrated prototyping software.

Read the full press release which includes an introduction video.

Highlights (With Mick’s mini explanations)

  • Up to 3x improvement in system prototype performance enabled through enhanced HapsTrak® 3  I/O connector technology and high-speed time-domain multiplexing

System performance needed for effective HW/SW validation is key to successful FPGA-based prototyping. The new HapsTrak 3 IO connector technology combined with Synopsys’ High Speed Time Domain Multiplexing (HSTDM) provides  3x or more improvement in system performance. 

  • Modular system architecture scales from 12 to 144 Million ASIC gates to accommodate a range of design sizes from individual IP blocks to processor subsystems to complete SoCs

The new HAPS systems are modular and scalable, just like the previous generations of HAPS systems. The product brochure has a nice chart at the end of it highlighting the different options.

  • New capability in Synopsys’ Certify® software, in combination with the HAPS’ flexible interconnect architecture, accelerates multi-FPGA partitioning productivity by up to 10x

This new capability not only reduces the time from ASIC RTL to FPGA ready design files but the new “patent pending” algorithms have also proven to automatically find an optimum partition to achieve lower multiplex rations meaning potentially higher system performance.

  • Enhanced Universal Multi-Resource Bus host connectivity of up to 400 MB/s facilitates debug and increases hybrid prototyping performance with Synopsys’ Virtualizer™

The UMRBus just got faster. You can do a lot across the UMRBus, remote access, configure and load the systems, data streaming from a host, co-simulation in addition to enabling Hybrid Prototyping. You can load four Xilinx Virtex-7 FPGA’s in about 20 seconds across the UMRBus, that’s magnitude faster than a traditional JTAG cable.

  • Pre-validated Synopsys DesignWare® IP with HAPS systems enables efficient integration of IP blocks and earlier software development

Leverage the work Synopsys has already done validating the DesignWare IP on HAPS. Not only does it mean that your risk is lowered as you know the DesignWare IP has been hardware tested but your effort to integrate the IP into a HAPS prototyping system is reduced.

Over the next couple of weeks I’m going to blog in detail about the new system capabilities. Have you been waiting for the HAPS-70 systems? Let me know your thoughts on the capabilities.

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