Posted by Michael Posner on August 23rd, 2012
Did you know that the team responsible for Synopsys’ FPGA-based prototyping products has been innovating for over 10 years?
It all started in 2000 with what we like to call the Pre-HAPS platform
As you can see this was designed as a plug in card and included on-board SDRAM. This was one of the first commercially available systems and extended FPGA-based prototyping capabilities to the masses. Feedback from customers was that the systems needed more external access enabling real world I/O connections. The other feedback was that “if” the SDRAM was used great, but if it was not then it reduced the number of I/O’s available to the end user.
Innovation lead to the first HAPS system, the HAPS-10, this was based on the Xilinx Virtex-II FPGA devices
The HAPS-10 system introduced the new familiar Hapstrak connector and flexible I/O based architecture. Haptrak provided a set of six connectors around each FPGA providing the end user with an abundance of I/O for daughter board connection for real world I/O. In addition, connector boards could be used to increase the number of I/O’s between FPGA’s ensuring ample signaling for partitioned designs. Note that the system also included a flash card for configuration of the FPGA’s.
The HAPS-10 was quickly followed by the HAPS-20 keeping pace with the latest available FPGA’s which in this case were the Xilinx Virtex-II Pro P100 devices.
The HAPS-20 systems extended the FPGA’s new higher performance capabilities to the FPGA-based prototypers. The systems maintained the Hapstrak connector ensuring previously designed daughter boards were reusable across the new generation of systems.
Next to come was the HAPS-30 systems. These improved on clocking capabilities and when used with the Synopsys Certify tool greatly eased prototyping and helped the user get the systems up and running as quickly as possible.
The HAPS-30 systems utilized the Xilinx Virtex-4 LX200 devices which again increased total capacity and performance of the system. The HAPS-30 systems offered significant value over a board that could have been built by a standard engineer such as immediate availability, high quality, high performance. At this point over 5 years of experience and innovation had been built in. As mentioned the systems were easier to use, clocking was simplified and power regions were controlled via on-system dip switches. A testament to high quality of these systems is that we still have customers using them today, 7 years in service!!!!
The HAPS-50 systems in 2007 took another leap forward with higher performance, greater capacity, 8 million ASIC gates per system and enhanced clocking enabling multiple systems to be easily chained for expansion.
The HAPS-50 systems utilizing the Xilinx Virtex-5 FPGA’s are still available to purchase from Synopsys. While the FPGA technology is a couple of years old the capabilities that the HAPS-50 systems extend for HW/SW integration, validation and software development is still sufficient for many SoC designs.
The latest generation of the HAPS series is the HAPS-60
The HAPS-60 again innovated and enhanced the use of the on system supervisor from simple setup and configuration to enabling advanced capabilities such as the Universal Multi-Resource Bus now used for Hybrid Prototyping and data streaming. Note that the HAPS-60 includes no dip switches, all configuration was now automated by the supervisor software. HAPS-60 also introduced the new Hapstrak II connector which provided greater signal integrity which was needed to support higher speed interfaces such as DDR3-800.
HAPS-60 is fully integrated with Certify and combined supports High Speed Time Division Multiplexing, HSTDM, the ability to automatically package individual signals together, send them across a high speed link between FPGA’s and un-package them within the same clock period. HSTDM not only improves the performance of a system that requires pin multiplexing but is also the enabler for some designs to be partitioned for FPGA-based prototyping. Without HSTDM a design which required thousands of signals to be passed between FPGA’s would have been impossible to partition with high speed results.
So who would like to guess what Synopsys has in store for FPGA-based prototypers in the future?
(Oh, I’m out for a couple of weeks, look out for some guest bloggers)