HOME    COMMUNITY    BLOGS & FORUMS    Breaking The Three Laws
Breaking The Three Laws
 
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Would you like 2X Performance AND Reduced Tool Runtime (Turn-around-Time)?

Posted by Michael Posner on August 29th, 2015

HAPS HSTDM Testing between HAPS-70 and HAPS-80

Above is a picture of HAPS High Speed Time Domain Multiplexing (HAPS HSTSM) being tested across the current HAPS-70 and the new HAPS J systems based on Xilinx UltraScale FPGA devices.

This week I’ve been busy presenting our next generation HAPS Solution, based on Xilinx UltraScale VU440 FPGA’s, to a number of key customers. First of all they love it, the benefit of the co-designed solution combining HAPS and ProtoCompiler are easily recognized. I’m personally confident that the new generation solution will be the most successful HAPS product to date. Each generation of HAPS has been more successful, dollar wise and sales unit volume wise, than the generation before it. The customers I’ve been presenting to are all existing HAPS-70 users so one of the focus points was to ensure they understood that the HAPS-80 and this new generation project are interoperable with each other. Not only does the hardware seamlessly chain, one cable between systems is all that is needed for the system to look like a single setup, but the design tool of choice, ProtoCompiler, supports mixing both Xilinx Virtex-7 and Xilinx UltraScale systems in one project. Of course when you mix systems don’t expect the older system to support the new capabilities. In a mixed setup the feature set supported between the two is dictated by the older generation.

Customers who have adopted HAPS-70 with ProtoCompiler are realizing some quite amazing results. As part of my presentations this week I’ve been sharing some customer experiences of HAPS-70 and ProtoCompiler usage. Below are a summary of some of those successes.

Great results with ProtoCompiler and HAPS, case1

The interesting part of this success is that ProtoCompiler was able to automatically find a better partition solution that not only increased performance, 4X, but also reduced the number of FPGA’s. The reduced test execution time was what most impressed this customer. While the above example only represents a short test, the almost 3X reduction in test run time will help the customer run their full suite of regressions in far less time, well almost 3X less time.

Great results with HAPS-70 and ProtoCompiler, case2

The key part of this success is that the customer was able to get their HAPS-70, 72 Million ASIC gate (six-FPGA) prototype up and running in less than two weeks. As part of that two weeks the customer optimized for performance achieving 10 MHz and incorporated the HAPS Deep Trace Debug capability delivering enhanced visibility. ProtoCompiler’s co-designed automated capabilities and scripted flow ensures predicable, high performance and reliable results every time.

Great results with HAPS-70 and ProtoCompiler, case3

The final customer experience also resulted in a higher performance prototype from ProtoCompiler finding a better partition solution. In this case though ProtoCompiler was given the freedom to target an existing 3-FPGA design to 4-FPGA’s. The resulting prototype was not only 2X higher performance but also reduced the RTL to bit file turn-around time by over half.

The HAPS & ProtoCompiler Co-Designed Advantage

I’ve seen many users get caught when they develop their own capabilities on one of their in-house developed FPGA boards. They tune the capability to the piece of hardware they are running only to find out that it does not run on any of the other FPGA boards they have. This is not an issue with HAPS and ProtoCompiler as they are co-designed and co-tested.

Co-design is the term we use for the parallel development of capabilities which require both hardware and tool support. The HAPS High Speed Time-Domain multiplexing and HAPS Deep Trace Debug are great examples of co-designed capabilities. The hardware has to be designed to support the capability and the ProtoCompiler tool has to include the feature to insert and deploy it. The advantage of co-designed capabilities is that the HAPS hardware characterization data is built into the ProtoCompiler tool ensuring that the feature is correct constrained. A version of this constrained feature is then used as part of the production test for the HAPS hardware ensuring that when the capability is used it always runs in a reliable and highest performance fashion. We continuously test the production implementation against the production HAPS systems ensuring backward compatibility in addition to reliable operation you can trust. If your prototype is acting funny you can be assured that it’s a legitimate issue in YOUR RTL or YOUR software and not an artifact of the HAPS capabilities.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

I’m presenting at SNUG Taiwan in a couple of weeks. If you happen to be around the SNUG location, drop in and say hello to me. I’ll be presenting the new HAPS systems and will have a live demo running on the new Xilinx UltraScale based system as well.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Bug Hunting, Man Hours Savings, Performance Optimization, Project management, UltraScale | No Comments »

Double performance with SLR to IO Bank to Connector 1 to 1 mapping for Xilinx UltraScale VU440

Posted by Michael Posner on August 24th, 2015

A long time ago in a blog since forgotten I talked about the importance of 1:1 mapping between the Xilinx FPGA Super Logic Region, SLR, to IO Bank to Connector. The result of which can be as much as 2X system performance thanks to efficient mapping of the design to the FPGA.

To recap, the Xilinx Virtex-7 2000T FPGA was made up of four(4) SLR’s and included fifty(50) IO’s per bank. The new Xilinx UltraScale VU440 is made up of three(3) SLR’s and include fifty two(52) IO’s per bank. It’s still a multi-SLR device so it’s key to design hardware in the right way to support this architecture.

Prototype design considerations for VU440 Xilinx UltraScale devices

It’s very important for the SLR to IO Bank to Connector mapping to be 1:1 matched. The new HAPS system has again been designed to minimize the detrimental effect of SLR crossing. Signals that cross SLR’s is fine, it’s when the signal makes multiple SLR crossings that you start to notice their effect. The new HAPS system, just like the HAPS-70, has been designed with 1:1 mapping of SLR to IO bank to connector including support for the fifty two(52) IO’s vs. the previous fifty(50) without the need for new accessories. The Hapstrak 3 spec included reserved pins which now support the extra IO.

If your FPGA hardware has connectors that pull in IO across multiple SLR’s you have a very high chance of forcing multi-SLR crossings resulting in much reduced performance.

Mismatched SLR to IO Bank to Connector results in reduced performance

If you select the HAPS-70 or new generation of HAPS utilizing the Xilinx UltraScale VU440 parts then you can expect higher performance operation as this SLR crossing effect is minimized or non-existent.

1:1 mapping of the HAPS-80. SLR to IO Bank to Connector 1:1

You can’t “fix” this in software, this is a hardware artifact which needs to be designed in from the ground up as it has been for the multiple HAPS generations

This is especially important for IP’s. As the SLR’s are so huge in the VU440 it’s possible to fit a whole IP into a single SLR with the IP’s interface going directly to the connector IO’s. *IF* the IP’s interface signals are forced to cross an SLR boundary just to get to connector IO the performance of the IP’s interface is going to be much reduced. IP’s such as USB 3.1, PCIe Gen3 and Gen4 all require interface timing closure above 156 MHz which means they cannot tolerate any SLR crossings for the interface signals to reach the IO.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in IP Validation, UltraScale | No Comments »

Performance boost from Xilinx UltraScale based prototypes

Posted by Michael Posner on August 14th, 2015

High Performance Engine in Micks Subaru Wagon Race Car

Everybody wants to know how much faster their FPGA-based prototype will run when they migrate to a Xilinx UltraScale VU440 based setup. This blog sets about trying to answer that very question. Sadly there is not a simple equation that can be applied as final system performance is highly design specific. Increase in performance falls into three or so buckets

  • Potential performance increase from the individual FPGA technology itself
  • Potential performance increase from design consolidation
  • Potential performance increase from prototyping platform specific capabilities

Potential performance increase from the individual FPGA technology itself

This is the potential performance increase you get from the “Raw” Xilinx UltraScale VU440 device performance. So far from Synopsys testing this is expected to be between 10-20% higher than raw Virtex-7 2000T performance. This is preliminary data based on our initial internal experiments from benchmarks across existing prototyped designs. This performance increase is really only applicable to single-FPGA sub-systems and IP prototypes.

Potential performance increase from design consolidation

This is where you take for say a four(4) FPGA design and manage to squeeze it into a two(2) FPGA design thanks to the greater capacity of the VU440. The VU440 is quoted as 2.2X the capacity of the V7-2000T. Synopsys rates the VU440 as 26 Million ASIC Gates. (Read this blog to understand how to calculate ASIC gates equivalency: https://blogs.synopsys.com/breakingthethreelaws/2015/02/how-many-asic-gates-does-it-take-to-fill-an-fpga/ ) Design consolidation like this has the highest probability of the largest performance boosts. Historically customers have seen significant performance improvements going from HAPS-50 (Virtex-5) to HAPS-60 (Virtex-6) to HAPS-70 (Virtex-7) and we expect the same going to the new Synopsys HAPS platform.

A data point to highlight this is from a recent engagement with a Synopsys customer. They had an existing three(3) FPGA design which ProtoCompiler was able to identify a new partition and delivered an auto-partitioned solution across just two(2) FPGAs. With the new partition the CPU performance was increased to 30 MHz which is a 63% improvement in boot test runtime.

On the flip side a second example is where we engaged with another customer who had an existing three(3) FPGA design. This time ProtoCompiler was able to find a new partition solution which targeted four(4) FPGA’s. The result was a 2.7X reduction in flow turn-around time and over a 2X system performance improvement.

The age old quote applies here “Design Specific, Your Results May Vary”

Potential performance increase from prototyping platform specific capabilities

This is the potential performance increase from the physical hardware itself as well as new capabilities. As noted in previous blogs, performance of a multi-FPGA prototyped design is typically dominated by Pin Multiplexing between FPGA’s. HAPS and ProtoCompiler delivers the highest performance solution for these cases, with or without pin multiplexing. With the new generation of HAPS you get even more:

Direct FPGA-FPGA connections: A tiny increase in performance expected

  • Up to 104 MHz vs. 102 MHz on HAPS-70

HAPS/ProtoCompiler delivers High Speed Time-Domain Multiplexing (HSTDM), which is a Differential signal based pin multiplexing scheme:

  • Bitrate increased to: 1300Mbps vs. 1100 Mbps on HAPS-70

The new HAPS/ProtoCompiler solution introduces a new pin multiplexing scheme, Single Ended Time Domain Multiplexing (SETDM):

  • Expected bitrate 1200 Mbps for most connections, this is up to 20% faster than our existing HSTDM
    • While SETDM looks to be higher performance, single ended technologies has a lower drive strength meaning lower SI over long reaches. Don’t worry, ProtoCompiler will be able to automatically identify short vs. long reach connections and automatically select the optimum pin multiplexing scheme to deploy for your specific design needs.

The new HAPS/ProtoCompiler solution introduces a second new pin multiplexing scheme, Multi-Gigabit TDM(MGTDM)

  • Recommended for pin mux ratios of x128 and above
  • Read this blog to understand about the new HAPS capability to off-load signals with more slack enabling more IO to be dedicated for the higher priority high performance signal needs.

The result of the combination of these HAPS/ProtoCompiler capabilities should ensure that under all situations you see a significant performance improvement when you transition to the new solution.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

Did anyone notice that the picture at the top of the page is actually of the engine bay of my Yellow Subaru Wagon race car? Check it out: https://www.youtube.com/watch?v=UYLQXur54zA I just got it running again after a break last year. I’ve been running and coaching using my other track only car, a Mazda Miata. The two cars are a little different, 480 Wheel HP from the Subaru and 80 Wheel HP from the Miata…..

Eye Candy time

Mick's Yellow Subaru Wagon Race Car

Micks Race Car, no I don't have a radio

Micks Race Car. That's a burly cage

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in UltraScale | No Comments »

Prototype ready IP for immediate productivity

Posted by Michael Posner on August 7th, 2015

MIPI CSI DWC IP Prototyping Kit as seen at SNUG Israel. Hi, thats me, Mick

Back in 2011 I had a vision, a vision for how users of both IP and FPGA-Based Prototypes could be more productive. The problems these users faced was not to do with bugs or lack of capabilities in the products but from the fact that the usage crossed between the two products. IP users traditionally are not experienced prototypers and prototypers lacked IP specific knowledge. Of course this was not helped by the fact that the IP did not document it’s prototyping specific needs. For example, the IP is optimized for ASIC deployment and when you prototype it the clocking, reset and rams sometimes need to be modified to fit into a FPGA environment. Another issue is that as it’s ASIC IP not all configurations can be physically supported in FPGA. For example while the IP might support up to 16 IO ports on the prototype you might only be physically implement up to 4.

So back in 2011 I presented this slide as part of a larger proposal. (Don’t worry, it’s not confidential at this point)

DesignWare IP on HAPS for the Win presentation back from 2011

Eventually this proposal turned into part of Synopsys’ IP Accelerated initiative, the DesignWare IP Prototyping kits. Well I like to think that this was the source of inspiration which lead to the DesignWare IP Prototyping kits. Others “claim” the idea and I’m happy for them to have the glory as they put far more effort taking a vision to reality that I did. It’s still a nice feeling to know that I identified the original need.

Fast forward and there are eight IP protocols supported with over seventeen different configuration varieties including Hybrid IP Prototyping Kit versions.

While at SNUG in Israel recently, the technical marketing manager and I met in front of the MIPI CSI DesignWare IP Prototyping Kit. The picture at the top of the blog is me in front of the demonstration, below is the TMM in front of it.

Hi from the TMM for DesignWare IP Prototyping kits

The funny thing is that this is not really a demo, it’s the actual execution of the DesignWare IP Prototyping kit. This highlights the huge benefit the kits bring to it’s users.

The DesignWare IP Prototyping Kits include the following:

  • Synopsys’ HAPS-DX FPGA-based prototyping system with pre-configured IP and SoC integration logic
  • PHY daughter board
  • Simulation testbench DesignWare ARC-based software development platform running Linux, or PCI Express connection to PC, or Virtualizer Development Kit
  • Reference drivers Application examples

Finally, below is a picture of my favorite coffee mug. Trust me when I say you don’t want to talk to be before I reach the bottom of the mug. I like to say never talk to Mick B.C, Before Coffee. Others within Synopsys have worked out that this is very true but have reduced the quote to “Never talk to Mick”………………. You folks are soooooo funny……

How fast do you run your prototypes? Make a comment and let me know.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

I love coffee

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in DWC IP Prototyping Kits, Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | No Comments »

How To Run Your Multi-FPGA Prototype at Ludicrous Speed

Posted by Michael Posner on August 2nd, 2015

Ludicrous Speed

In this blog I’m going to explain how you can run a multi-FPGA HAPS prototype at up to 100 MHz !!!!!

I’ve blogged a couple of times now on how the HAPS flexible interconnect routing architecture combined with HAPS High Speed Time Domain Multiplexing (pin multiplexing) increases the performance of a multi-FPGA HAPS prototype.

This week I was asked how fast can you run a multi-FPGA HAPS system when NO pin multiplexing is needed. Interesting, I sometimes forget that there are designs which do not exceed the number of physical IO pin’s on the HAPS systems. So let’s assume you have a design which can be partitioned without the need for pin-multiplexing. This means that the number of signals between FPGA’s does not exceed ~1100 (per FPGA) in the case of the HAPS system. Did you know that Synopsys ProtoCompilers goal is to find an automated partition with a goal of no pin multiplexing. Yep, ProtoCompiler will try to find a partition which does not require any pin multiplexing. If ProtoCompiler cannot find a solution it deploys HAPS High Speed Pin Multiplexing with a goal of the lowest pin-mux ratio to deliver the highest performance. Many designs require multi-thousands of signals between FPGA’s so ProtoCompiler has to automatically deploy one of the available multiplexing schemes.

I was asked if the intelligent interconnect affects performance, as in are PCB traces faster? The answer is in the space of prototyping the effect is negligible. I blogged on this case with the technical data as to why here https://blogs.synopsys.com/breakingthethreelaws/2013/03/ufc-cables-vs-pcb-traces/

HT3 interconnect routes raw performance

The HT3 interconnect is capable of operating far faster than you can run the prototype.

Combine this with the fact that you can tailor the HAPS flexible interconnect to match the requirements of the SoC (DUT) the result is an optimized configuration.

HAPS Flexible interconnect routing architecture

Ok, so you are getting bored by this point so I’ll finish with the data which is needed to calculate the performance of the HAPS prototype when no pin multiplexing is implemented. The equation is (Total FPGA delay + Inter-FPGA delay) = System path delay (The link from one pin on an FPGA to another pin on a second FPGA)

The inter-FPGA delay for the HAPS-70 and the new generation of Xilinx UltraScale VU440 based systems is actually very close, ~6 ns for both.  The difference will come in the FPGA fabric:  Virtex 7 2000T(logic delay + IO) vs. UltraScale(user logic delay + IO).  For best case logic delay, we can assume clk-to-Q + LVCMOS_18 IO delay.

For UltraScale VU440 (very preliminary because Xilinx datasheets are not complete, so I extracted what I could):

•             LVCMOS_18 output delay for -1 parts:  1.19 ns

•             LVCMOS_18 input delay for -1 parts:  0.54 ns

•             Global clock input with MMCM to clock output:  1.79 ns

•             Total FPGA delay = 3.52 ns

•             System path = 3.52 ns + 6 ns = 9.52 ns

Result 104 MHz

For V7 2000T:

•             (2.36 ns + 0.9 ns + 0.49 ns) + 6 ns = 9.75 ns (Result 102 MHz)

Ergo, performance with no pin multiplexing of up to 102/103 MHz on HAPS systems. No real difference between the two platforms as the architectures are the same and the FPGA’s performance improvement is insignificant so has minimal effect.

The funny thing is I have never come across a customer running a multi-FPGA prototype at this performance even when they are not using any pin multiplexing. The reason is the USER LOGIC Delay. Above we assume best case, clk to Q, but in reality users designs end up adding ~15ns user logic delay. So now rather than a delay of ~10ns you have a total path delay of ~25ns or 40 MHz. This is a more realistic performance number to expect from a multi-FPGA prototype when no pin multiplexing is used. If ProtoCompiler is able to find the perfect clk-to-Q partition point on all signals that have to cross FPGA’s then yes, the resulting HAPS prototype is capable of running at up to 100 MHz. Even if ProtoCompiler is forced to deploy HAPS High Speed Pin Multiplexing, HSTDM, at the lowest ratio you can get up to 30 MHz, again the biggest performance limiter is user logic delay, not the technology itself.

I took a day off this week so I could go to the track. I volunteer and coach race car driving with a side benefit of getting a lot of time on the track myself either in a coaches only session or out with the students doing lead/follow. I got in over 200 miles this weekend at the Ridge MotorSports Park, great fun. I also enjoyed making use of the tent on top of my truck so I didn’t have to get a motel room. The moon was amazing on Friday night.

I’m not sure if you can see my tent in this picture :)

Tent on top of Toyota FJ truck with Race Car Trailer behind it

How fast do you run your prototypes? Make a comment and let me know.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Performance Optimization, UltraScale | No Comments »

Prototyping a PowerVR Series6XT GPU using an optimized flow from Synopsys

Posted by Michael Posner on July 24th, 2015

Block diagram on Imagination PowerVR Series6XT GPU

I ran across this blog on Imaginations website which covers details on prototyping the PowerVR Series6XT on HAPS: http://blog.imgtec.com/powervr/prototyping-a-powervr-series6xt-gpu-using-an-optimized-flow-from-synopsys

I highly recommend reviewing the material as it provides insight into not only how to prototype large GPU’s but also how to quickly scale multi-FPGA prototypes.

Short blog this week as I’m off to do a little camping and when I camp I like to camp in style.

Tepui tent installed on top of my Toyota truck

I love my little retro-style teardrop camper and my tent on top of my truck. Enjoy.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Early Software Development, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | No Comments »

Xilinx UltraScale VU440 based HAPS Solution Shipping (HAPS/ProtoCompiler)

Posted by Michael Posner on July 17th, 2015

HAPS PMM Polishes HAPS Xilinx UltraScale VU440 based system during photo shoot

That’s right, Synopsys’ new FPGA-based prototyping solution of HAPS hardware with integrated ProtoCompiler software is shipping…………… to the lucky early adopters.

This week I popped into one of the Synopsys conference rooms and snapped off a couple of mobile phone pictures during the professional photo shoot of the next generation of HAPS systems utilizing the Xilinx UltraScale VU440 FPGA devices. The systems are fully operational, powered by the built-in HAPS supervisor firmware and fully integrated ProtoCompiler software. Before the systems ship off to early adopter customers we wanted to snap off a couple of pictures for our official launch materials. Above, the HAPS product marketing manager polishes one of the new systems to remove R&D finger prints. (Note the ESD protection before doing this!)

Below, a view of the 4-FPGA and 1-FPGA version, I didn’t like the way the 2-FPGA picture turned out but we offer that form factor as well.

Mick snaps of a mobile phone picture of the new 4-FPGA HAPS Xilinx UltraScale VU440 based systems

Extreme close up of HAPS 1-FPGA Xilinx UltraScale VU440 based system

We also populated a set of 19” server rack frames with systems to capture the look and feel of the HAPS hardware in a server farm remotely managed scenario. We support in excess of 1.5 Billion ASIC gates which is sixty four (64) FPGA’s operating within a system synchronous chain with automated ProtoCompiler design flow. Sadly my mobile phone picture did not look great, really fuzzy, but I’ll see if I can get another picture to post at a later date.

It should be noted that these HAPS system are classed as Pre-Production, Synopsys production candidate hardware with Xilinx Engineering Sample FPGA’s as that is all that is available in respect to the FPGA devices at this time. Full Production systems (Hardware & ProtoCompiler software) will be officially available timed with the production availability of FPGA devices from Xilinx. As you can see through, if you want early access, Synopsys can service your need now with these pre-production systems and early access to the ProtoCompiler software.

As a refresher, the key benefits of the new fully integrated solution include but is not limited to:

  • The fastest time to operational prototype, on average 2 weeks from initial RTL, and the fastest RTL-to-Bit file flow for rapid incremental turn-around
  • Highest performance with an end-to-end timing-driven multi-FPGA flow & new high-speed TDM-based pin-multiplexing schemes
  • Global synchronous (no pin multiplexing) operation of up to 100 MHz
  • Always available, built-in debug delivers superior debug visualization over thousands of RTL-level signals
  • Global accessibility, regression farm support and multi-design capabilities
  • Modular & scalable to over 1.5B ASIC gates – 1 to 64 Xilinx UltraScale VU440 devices.
  • Preserves existing HAPS investment, interoperable with HAPS-70, mix and match design flow and hardware, same form factor, I/O voltages, HT3 connectors, daughter boards, cables

As a 2nd refresher, (or the first time for those who missed them) here is a list of my blogs around the next generation Xilinx UltraScale-Based HAPS solution, hardware and ProtoCompiler SW.

Xilinx UltraScale solution focused.

In between these blogs you will find a stack of other posts great information (if I do say so myself)

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in UltraScale | 2 Comments »

Welcome new HAPS Connect Partners, Sunstone Circuits, Screaming Circuits and Radix Co., Ltd

Posted by Michael Posner on July 13th, 2015

HAPS Connect Partner Services for HAPS systems

I’m back from vacation (which was great, thanks for asking) and happy to announce three new HAPS Connect partners, Sunstone Circuits, Screaming Circuits and Radix Co., Ltd. A list of all the HAPS Connect partners can be found following this link.

Sunstone Circuits is the established leader in providing innovative and reliable printed circuit board (PCB) solutions for the electronic design industry. With over 40 years of experience in delivering high quality, on-time PCB prototypes, Sunstone Circuits is committed to delivering production-grade small-quantity PCB manufacturing, from layout to fabrication, from board test to assembly (in partnership with Screaming Circuits), Sunstone Circuits can help you build out your HAPS system quickly and effectively. http://www.sunstone.com

Screaming Circuits assembles prototype and small volume production PC boards. We’ll build as few as one board for a quick-turn prototype, and up to thousands for low-volume production. We’ll build from your kit, or, with our long-time PC board fab partner, Sunstone Circuits, and parts suppliers, such as Digi-key, Arrow, and others, we’ll handle the whole procurement and build process for you. We’ve built boards that have gone up into space, down into the ocean, and everywhere in between. ITAR and IPC Class III are available. http://www.screamingcircuits.com

Radrix Co., Ltd. is a university venture company based in Japan. Radrix provides various engineering solutions, including system design and development for the signal processing and wireless communication field. Radrix has developed chipsets, ASIC and FPGA level design and system simulators for next-generation wireless LAN 802.11n/ac and other next-generation digital communication systems. http://www.radrix.com/?lang=en

Please join me in welcoming these three new HAPS Connect Partners. The HAPS Connect Program expands the choice of HapsTrak and Multi-Gigabit board and service offerings available for HAPS systems. The HAPS Connect Program helps customers to: Develop HAPS prototypes faster by leveraging compatible daughter boards from leading industry hardware vendors; Reduce project risk by taking advantage of hardware and services from vendors with HAPS system expertise; Save on prototype development costs and resources by using products and services tailored for HAPS systems. Interested in being a Synopsys HAPS Connect Partner? Contact us for more information on how to join the HAPS Connect Program, hapsconnect@synopsys.com

I love nature and Hawaii has a lot of it, check out this huge snail found in Maui

Check out the size of this snail... and this was one of the small ones

These guys turned their backs to me, apparently they don’t like the Posner paparazzi.

These little animals didn't like their picture being taken

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in HAPS Connect Program | Comments Off

Exploratory Place and Route improves timing by up to 10%

Posted by Michael Posner on July 1st, 2015

Example of a routing hot spot in FPGA

This week I am going to discuss a new and unique capability in the Synopsys FPGA/FPGA-based prototyping tools that get you the double whammy, helps solve FPGA routing congestion and improves FPGA performance. The new capability is called Exploratory place and route (PAR). Oh, before I forget I’m off on vacation for a week so no blog next week. I know this is going to break my posting flow and even though FPGA-based prototyping is always on my mind even when I’m hiking or snorkeling or kayak surfing or just sitting on the beach relaxing, I’m going to resist the urge to post by not traveling with my laptop.

While the new FPGA devices have more routing, designs sometimes run into congestion, especially ASIC designs being prototyped as they are not specifically designed for FPGA resources. Mitigating routing congestion is a difficult task and runtime scales with design sizes and complexity. One size does not fit all, as in there is not a single silver bullet option to solving routing congestion as there are many causes for it. In prototyping one way to reduce congestion is to simply partition across more FPGA’s. In ProtoCompiler it’s easy to do this but of course this is at the cost of additional hardware. Another means for tackling the problem is parallelization of the place and route task driving the tools with different seeds. The Synopsys Exploratory Place & Route feature exploits parallelism along with design characterization to make ‘smart’ choices for P&R configurations

ProtoCompiler’s Exploratory Place and Route feature first scans the design and generates a signature based on the architecture. ProtoCompiler then invokes parallel Vivado P&R jobs, and learns from each results so as to determine the optimum P&R settings to meet timing and route the design.

Flow for the new Synopsys exploratory place and route capability

During synthesis, the Synopsys mapper generates design characteristic and design statistics information. These characteristics are used to select Vivado Place & Route configurations and launches parallel P&R jobs. These jobs are monitored and subsequent jobs are launched, provided the Worst Negative Slack (WNS) for each individual job is < 0. Once a P&R job has WNS > 0, the monitor terminates all remaining jobs. Hey presto, rapidly find the best P&R settings based on your design. No longer do you have to rely on guess work or default to what worked well in the past as that strategy might not be suitable for the new design.

Synopsys Exploratory PAR results, up to 10% improvement in timing

Total number of possible jobs will be run until the best result (based worst negative slack of the design) is achieved. The best results are written to the Place & Route directory (including .dcp files, log files etc.) along with a par_explorer.log which contains a description of each place and route job run. Synopsys’ Exploratory Place & Route parallelizes the problem across multiple cores or multiple machines. When a satisfactory result is achieved, all remaining jobs are terminated, and the successful run is saved. We have seen up to 10% timing improvement from utilizing this new capability (not represented in the pic above)

Super cool, basically takes the guess work out of configuring the place and route. This capability is an integral part of the complete timing driven flow delivered in ProtoCompiler and which I discussed in an earlier blog. In summary to achieve the highest possible prototype performance you need a complete RTL to Bit file, end to end flow. ProtoCompiler is the only tool in the market able to offer this.

HAPS ProtoCompiler end-to-end timing driven flow for highest performance operation

Average results at each stage of HAPS ProtoCompilers timing driven flow optimizations

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in Performance Optimization, Use Modes | Comments Off

Intel’s FPGA-Based Prototyping presentations from SNUG Israel

Posted by Michael Posner on June 27th, 2015

Recently at  SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology guide so I highly recommend you review the material.

http://www.synopsys.com/community/snug/pages/proceedingLp.aspx?loc=Israel&locy=2015

Intel presentation from SNUG Israel on FPGA-based Prototyping of SoC's

The second paper titles  “Large Scale IP Prototyping” is a great example of multi-FPGA designs using Synopsys’ HAPS/ProtoCompiler solution and specifically the HAPS High Speed Time Domain Multiplexing to pass ~25K signals between FPGA’s. The material presents Intel’s usage and results and again I recommend downloading and reviewing the material.

http://www.synopsys.com/community/snug/pages/proceedingLp.aspx?loc=Israel&locy=2015

Intel presentation on Large IP Prototyping using HAPS and ProtoCompiler

Oh, you need to have a Synopsys SolvNet ID to download….. Oh#2, I just noticed the proceedings are not posted yet. I am reliably informed that they will be posted shortly.

Many of you know that I travel internationally on business on a regular basis and have asked how I cope with the constant time changes. I employ two simply methods to manage jet lag, #1 No alcohol while traveling at all. This helps when you are only getting 3-5 hours of sleep and #2 Coffee

Best jet lag #2 Coffeeeeee

Luckily while in the UK they serve up vats/buckets of coffee that require two handles to hold the weight. This is a six shot “eye opener”

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Another option to subscribe is as follows:

• Go into Outlook

• Right click on “RSS Feeds”

• Click on “Add a new RSS Feed”

• Paste in the following “http://feeds.feedburner.com/synopsysoc/breaking”

• Click on “Accept” or “Yes” or whatever the dialogue box says.

  • Print
  • Digg
  • StumbleUpon
  • del.icio.us
  • Facebook
  • Twitter
  • Google Bookmarks
  • LinkedIn

Posted in ASIC Verification, Debug, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Milestones, Performance Optimization, Project management, System Validation, Technical, Tips and Traps, Use Modes | Comments Off