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Breaking The Three Laws
  • About

    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Read Issue #1 Prototyping Newsletter: Reduce Risk and Speed Time-to-Market with End-to-End Prototyping

Posted by Michael Posner on May 20th, 2016

Prototyping-news-letter

We have just published the first issue of our new prototyping newsletter. This quarterly newsletter provides you with the latest information on end-to-end prototyping, including in-depth technical articles, white papers, videos, webinars, product announcements and more.  As the industry’s number one provider of architecture design, virtual and physical prototyping solutions, Synopsys is committed to providing you with the resources you need to accelerate software development and system validation.

Subscribe to the Prototyping Newsletter and get it delivered directly to your email

Featured Articles (not all articles listed, just a couple, click image above to go to full newsletter)
Faster Prototyping with HAPS
Learn how the HAPS integrated prototyping solution enables use case specific debug capabilities.
How Prototyping Increases Interoperability Success
Learn how a prototyping platform can make the difference in high-pressure situations like interoperability events.
Practical Power Management
Learn how to establish a power management strategy that meets your design goals.
White Papers
Scaling Automated Software Testing with Virtualizer Development Kits
Learn how simulation-based Virtualizer Development Kits (VDKs) enable software to be tested in a system context much earlier, bridging the gap with unit and integration testing.
End-to-End Prototyping to the Rescue
This white paper reviews how companies have been adapting their processes to provide more functionality through software through the increased adoption of prototyping methods.
On-Demand Webinars
Better Testing Through Automation and Continuous Integration with Virtualizer Development Kits
How Flexible Debug Can Speed Physical Prototyping Bring-Up and Software Development
Videos
EE Journal Chalk Talk: The Market Shift to Integrated Physical Prototyping
Industry Articles
Electronic Design: Q&A: Using FPGA Prototypes for Software Development
News
Synopsys Platform Architect MCO Delivers Industry’s First Power-Aware Architecture Analysis Tool Supporting IEEE 1801-2015 UPF 3.0
Synopsys and ARM Expand Collaboration to Accelerate Software Development for ARM-Based Designs
Publications
Best Software Faster! Best Practices in Virtual Prototyping
FPGA-Based Prototyping Methodology Manual: Best Practices in Design-for-Prototyping

Happy with the blog, click the subscribe link on the left and follow the instructions

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Posted in Prototyping newsletter | No Comments »

Which is your favorite FPGA-based prototyping setup?

Posted by Michael Posner on May 13th, 2016

Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards,

eetimes-image

I would actually argue that only the #1 listed solution, HAPS with HAPS ProtoCompiler is a comprehensive FPGA-based prototyping solution. The others all serve a purpose but typically have no specific features facilitating FPGA-based prototyping.

HAPS with HAPS ProtoCompiler you get the following which specifically addresses the challenges of FPGA-based prototyping

  • Reduces time to high-performance prototype to <2 weeks
  • Built-in debug captures >1000 RTL signals per FPGA at speed
  • Delivers up to 100 MHz system performance
  • Scalable, modular, large capacity – up to 1.6B ASIC
  • Fast and incremental tool flow

What is your favorite FPGA-based prototyping setup? Post a comment below.

To SUBSCRIBE use the Subscribe link in the left hand navigation bar.

Oh, and to motivate you to post comments, I’ll select one person randomly to receive a HAPS with HAPS ProtoCompiler tote

Here you can see me modeling it

HAPS-n-Mick-Tote

And a detailed picture. Great right. Can’t you just picture your shopping and groceries packed into this :) You will be the talk of the town

HAPS-Tote

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Posted in Admin and General, HAPS-80, Support, UltraScale | Comments Off

Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

Posted by Michael Posner on April 29th, 2016

I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)

The new release includes capabilities which reduce the time to first prototype even more than we do today, greater design visibility with new and automated debug features, automated performance boosting methods and many more like support for UPF 2.1 as blogged about a while back.

The two capabilities which caught my eye were the new HAPS Global State Visibility and the performance improving HAPS Timing Aware System Route.

HAPS Global State Visibibility

HAPS Global State Visibility, HAPS GSV, delivers a method to capture all register values in a non-intrusive fashion, meaning no instrumentation needed. This is an on-demand design visibility capability which is incredibly valuable to help debug issues immediately. Even better, you are not debugging complex FPGA specific register names, the HAPS ProtoCompiler flow maps the data back into the original RTL golden source namespace. So cool.

HAPS Timing Aware System Route

One of the other capabilities which impressed me (well done R&D), is the enhanced HAPS timing aware system route. The HAPS system route phase automatically selects the optimal multiplexing (HSTDM) ratios based on the over design and specific path’s slack. In most cases this new level of automation is delivering ~10% increase in the HAPS prototypes performance.

Look out for a new blog starting soon: https://blogs.synopsys.com/hittingthemark/

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Posted in ASIC Verification, Bug Hunting, Debug, FPGA-Based Prototyping, HAPS-70, HAPS-80, Man Hours Savings, Performance Optimization, Real Time Prototyping, Tips and Traps, UltraScale | Comments Off

Verifying Power Management Modes, both Software and Hardware

Posted by Michael Posner on April 14th, 2016

Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!”

Raspberry PI image

BTW: This blog was inspired by a true story of a challenge that Achim Nohl, Technical Marketing Manager for HAPS Physical Prototyping recently experienced: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=51543

Power management is an increasingly complex function provided by hardware and controlled by a large extent by software. The software is orchestrating the power-up and power-down sequence of the SoC’s subsystems and peripherals in various scenarios such as cold boot, warm boot, resume, hibernate etc. These scenarios involve multiple software layers such as firmware, boot loader, operations system and user space software. The interaction between those layers, which often reside in different privilege modes (aka exception levels), is complex and prone to errors due to the variety of scenarios, conditions and distributed ownership of the software modules in different teams and 3rd party or open source.

Testing this software power management prior to silicon is a huge concern but, the same concern is with the hardware designers as it’s the software that controls most of the hardware operation. The complexity of software power management is mirrored in the hardware through complex clock-/power-management units, a growing number of power domains and the required logic for retention and isolation functions. While the power-off sequence in software is a coarse grain level for the power domains, the power gating (PG) sequence in hardware is a complex fine grain control of isolation, retention, voltage and clocking. Before a power domain can be powered off after shutting down the clock, the outputs need to be isolated to prevent floating signals to propagate to neutral power domains. Certain flops may need to keep their state during power gating using retention cells after isolation has happened. Only then, the voltage VDD can be safely removed, keeping the lower retention voltage VSS, which levels have been programmed via software using a PMIC (Power Management IC). A lot can go wrong here and a flaw may just be exposed under very specific conditions during field operation. That is why we are seeing so many answers like this in user forums. “It Works!! Disabling the power management of my Wifi chipset solved my instability problem”. Whoops, a bug got through somewhere, could be software, could be hardware but we don’t know for sure. What we do know is that the bug only showed itself when power management is active.

In order to address the important and urgent need to verify and validate hardware and software power management functions prior to silicon designers have turned to physical prototyping. The power management software can be executed against the power management hardware before you commit to silicon. Of course you can only do this if your physical prototyping solution supports modeling of the power management hardware. The HAPS physical prototyping solution enables support for those power management use-cases. Compared to traditional FPGA synthesis targeting FPGA as the final product, HAPS ProtoCompiler is able to understand the hardware power intent from UPF (Universal Power Format) specification and translate this into the required logic for prototyping power management. UPF is the IEEE standard for describing the power supplies, power states, retention etc. and separated from the RTL description of the design.

Low power intent view in ASIC

Typically, this is not something you are concerned as an FPGA implementer and that is why synthesis tools for FPGA implementation do not support it and provide power management solutions very different than the ones for ASIC implementation. Since HAPS ProtoCompiler has a different objective, which is the validation of ASIC hardware and software under real world conditions, UPF is an integral part of the HAPS prototyping flow. For this purpose HAPS ProtoCompiler goes beyond translating UPF into a neltlist for the FPGA and enables new techniques which allow more and targeted testing of power management functions. Fro example the flow enables the isolation and retention logic to be prototyped, in addition, dedicated capabilities enable corruption of sequential elements when the power domain is shut off to better reflect what the final SoC would experience. This way, HAPS ProtoCompiler increases the test coverage for the crucial isolation and retention logic.

Low power modes modeled through ProtoCompiler for HAPS

Not testing power management software and hardware is risky as it leaves a gap in the pre-silicon validation. HAPS with HAPS ProtoCompiler enables power management capabilities to be verified based on a standard UPF flow.

Look out for a new blog starting soon: https://blogs.synopsys.com/hittingthemark/ This blog will discuss both Virtual and FPGA-based Prototyping

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HW/SW Integration, Man Hours Savings, System Validation, UltraScale, UPF, Use Modes | Comments Off

ESD Precautions Essential for prototype handling

Posted by Michael Posner on April 8th, 2016

Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape.

First read my recent blog on the subject: Preventing Electrostatic discharge

Second, watch the Synopsys video on specific handling instructions of the HAPS system

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Finally, build your own Van de Graaff generator: https://youtu.be/-WradvSywWM

Mick's Home Built Van de Graaff Generator Micks-VDG-2 Micks-VDG-3

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Posted in Admin and General, HAPS-80, UltraScale | Comments Off

Prototyping enables worlds first PCIe Gen4 (16 Gb/s) demonstration

Posted by Michael Posner on April 1st, 2016

While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:

DesignWare PCIe Gen4 (16Gb/s) demo on HAPS-DX

This is the demo setup for the DesignWare IP for PCIe Gen4 which is the latest and fast 16 Gb/s PCIe transfer solution. (Sorry for the low quality mobile phone pic). This is the platform which we have been using around the world to demonstrate our hardware validated PCIe Gen4 solution.

At the top of the pic is the ARC platform which is used to execute software to manage the DesignWare PCIe controller core which is modeled in the HAPS-DX system in the center of the pic. The large daughter board at the bottom houses the testchip of the mixed signal PHY. It connects to a simple PCIe backplane which is the card right at the bottom under the PHY daughter board, almost out of sight. The backplane connects up to an almost identical setup on the backside. One side is the root complex, other is the device, both using DesignWare IP as at this time their is practically no PCIe Gen4 hosts on the market.

This reminded me of a key value of FPGA-based prototyping…. EARLY…. This HAPS-based prototyping setup enables validation of hardware and software for a cutting edge protocol. Below you can see a video of the DesignWare PCIe Gen4 setup in action

Can’t embed the video so please click this: https://www.youtube.com/watch?v=P2G2nGqgf2E

You can also find out more about the DesignWare PCIe Gen4 solution on the Express yourself blog, https://blogs.synopsys.com/expressyourself/2015/11/13/the-worlds-second-pcie-gen4-system-arm-beats-intel/ and here: https://blogs.synopsys.com/expressyourself/2016/03/04/the-long-lost-video-the-worlds-2nd-pcie-gen4-system/ and Synopsys webpages here.

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Posted in DWC IP Prototyping Kits, In-System Software Validation, IP Validation, Man Hours Savings, Real Time Prototyping | Comments Off

It’s not too late to attend SNUG Silicon valley

Posted by Michael Posner on March 28th, 2016

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

Prototyping topics:

  • Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System
  • FPGA Debug: Improving Debug Turnaround Time in High Speed Designs
  • Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution
  • Adapt, Port, and Integrate Quickly – Prototyping the Right Way
  • Address TTM by Prototyping and Validating SoC Design Using HAPS-70 System
  • Reduce Overall TAT and Increase System Performance of Prototype Using ProtoCompiler

Many of these are user presentations so not to be missed.

More details here: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/Documents/snug-sv-2016-schedule3.pdf

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Another option to subscribe is as follows:

• Go into Outlook

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• Click on “Add a new RSS Feed”

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• Click on “Accept” or “Yes” or whatever the dialogue box says

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, DWC IP Prototyping Kits, Early Software Development, FPGA-Based Prototyping, FPMM Methods, Getting Started, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, Support, System Validation, Technical, Tips and Traps, UltraScale, Use Modes | 1 Comment »

What’s in it for me? The market shift to integrated Physical Prototyping

Posted by Michael Posner on March 11th, 2016

What's in it for me

FPGA-based physical prototyping is the go-to standard for high-performance, high-productivity verification, debug, and software development on many electronic systems today. But, it is becoming increasingly difficult to put together an ad-hoc prototype mixing pieces from various vendors with home-grown components. With the complexity of today’s systems, an integrated prototyping system can bring significant advantages.

Learn about these advantages (the answer to the question “what’s in it for me”) in this Electronic Engineering Journal chalk talk http://www.eejournal.com/index.php?cID=35861 hosted by Amelia Dalton.

EE Journal

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Over the last weekend I coached teens how to handle unpredictable and potentially dangerous driving situations. You can find a short story on the Tire Rack Street Survival School here: http://www.kgw.com/news/local/street-survival-school-helps-teens-become-better-drivers/70835667 At the end of the clip you will see a silver car pass behind the person being interviewed, that was one of my students and I’m in the passenger seat.

The primary emphasis of the Tire Rack Street Survival is a “hands-on” driving experience in real-world situations! We use your own car to teach you about its handling limits and how you can control them. The students will become more observant of the traffic situation they find themselves in. They will learn to look far enough ahead to anticipate unwise actions of other drivers. As the students master the application of physics to drive their cars, they will make fewer unwise driving actions themselves. They will understand why they should always wear their own seatbelts, and why they should insist that their passengers wear seatbelts, too.

I enjoy volunteering for this school as I hope that the skills the teens learn could help save their lives in the future. It’s about more than driving – it’s about LIVING!

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Real Time Prototyping, System Validation, UltraScale, Use Modes | Comments Off

Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Posted by Michael Posner on March 4th, 2016

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

A recent web seminar presented the various debug scenarios and maps which debug capabilities to use for the particular scenario.

HAPS Debug Visibility Web Seminar

https://webinar.techonline.com/1674?keycode=CAA1BC&cmp=WEBR-fpgabp100503-HPW

I highly recommend you take the time and watch the seminar as it covers not only the traditional physical prototype debug capability but also introduces the new capabilities such as HAPS Deep Trace Debug, the ability to capture huge amounts of debug data as well as HAPS Global State Visibility. Global State Visibility has always been seen as the Holy Grail of FPGA-based prototyping, the ability to trace the state of all design registers, dynamically, without the need to pre-define of instrument.

HAPS & ProtoCompiler Debug Visibility Solutions

The web seminar also includes a mention of utilizing the other capabilities such as HAPS Real Time Debug enabling a debug connection to a Logic Analyzer and cross triggering to aid in HW/SW debug.

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Do you think that the wireless megatrend, data transfer and charging will replace wired USB? Read this: https://blogs.synopsys.com/tousbornottousb/2016/02/26/will-wireless-data-charging-replace-usb/ and post your views.

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, System Validation, UltraScale | 2 Comments »

Q&A Using FPGA Prototypes for Software Development & More

Posted by Michael Posner on February 26th, 2016

Great article by Tom De Schutter on using Physical Prototyping for software development. The article goes into other use cases and explores the age old make vs. buy decision making process.

http://electronicdesign.com/fpgas/qa-using-fpga-prototypes-software-development

Click here for the full article

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Posted in ASIC Verification, Bug Hunting, Debug, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, IP Validation, Man Hours Savings, Performance Optimization, Project management, Real Time Prototyping, System Validation, Use Modes | Comments Off