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Breaking The Three Laws
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    Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
  • About the Author

    Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. Previously, he has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.

Why Do You Prototype? If You Don’t Know I Can Tell You

Posted by Michael Posner on January 30th, 2015

I was forwarded this user quote and I thought I would share as it was so heartwarming for me

The design came up on HAPS in less than two weeks and we found a rather serious bug early in testing.  This is the bug that would have cost the company dearly if it wasn’t found until later in the development cycle.

It’s short and sweet and communicates the HUGE value that FPGA-Based Prototyping delivers.  This note reminded me that a while back I did an internal analysis of the value of HAPS FPGA-based prototyping in respect to the various use modes. The use modes I examined was Functional Verification, HW/SW Integration, Firmware Development, System Validation and Software Development. First I created a baseline score for HAPS in respect to various user requirements. This list stays consistent across all use modes.

  • Early Availability
  • Initial Design Setup
  • Iteration Turnaround Time
  • Execution Speed
  • Capacity
  • Deployment (Ease of/Cost of)
  • Accuracy
  • HW Debug Visibility
  • SW Debug Visibility
  • IO

How the scoring works, 1 = Sub-Optimal, 10 = Excels. To score I created a set of definitions per requirement and using real data which compared the results to other technologies thus to objectively score. The scores are mapped into a radar chart. Here is the scoring baseline for HAPS. I should point out that its subjective but I tried to be as data driven as possible. If anything I might have been a little harsh on HAPS to be fair.

HAPS Value, baseline scoring in respect to capability strengths

At the same time and using the same list of requirements I scored the NEEDS of the use mode. For example the user needs for software development are pictured here. Note the dotted line.

Baseline requirements mapped into radar chart in respect to the needs of software development

The baseline needs were mapped for each of the desired use mode. Then it’s a simple case of overlaying the results of the baseline value score of HAPS against the use mode. It’s a multiplication of the value times the need. This way it clearly shows where there is synergy of a need and as strength.

Starting with Functional Verification

HAPS Values Mapped to the Functional Verification Use mode

Remember the dotted line represents the user needs within the use mode of functional verification and the solid line represents the relative strengths of HAPS. Within a radar chart it’s easy to see the matching requirements and HAPS strengths. It’s clear to see that while HAPS does bring value to functional verification it’s definitely not the best technology for the use case. Hey, we all knew this already. A simulator such as VCS or emulator such as ZeBu is a far better choice for functional verification as they deliver on the key needs of the use case such as early availability, debug visibility, capacity etc. But I also know that HAPS is used in this use mode as the performance enables a huge amount of tests to be run in a short amount of time flushing out those hard to find RTL bugs.

Now lets review the HW/SW Integration use mode

HAPS Values mapped into the HW/SW use mode

Immediately it’s clear that the value of HAPS FPGA-based prototyping is far better matched to the requirements for HW/SW Integration. HW/SW Integration is typically the point at which FPGA-based prototyping is deployed in development. As more and more RTL blocks are coming together and the volume of software has become significant then the additional performance that HAPS FPGA-based prototyping delivers is needed to execute in a reasonable timeframe.

Now onto Firmware Development

HAPS Values mapped against the needs for firmware development

FPGA-based prototyping enables the use of real physical interfaces using the real interface blocks such as DesignWare IP. This means that the hardware aware firmware development is a key use case for HAPS FPGA-Based prototyping and this is represented in how well the values match the use case needs. The real physical IO, actual RTL blocks combined with the high performance operation make HAPS FPGA-based prototypes one of the best firmware development platforms next to the real silicon. Actually I would be bold enough to say better than the real silicon as once you have silicon its too late to fix RTL bugs!

System Validation

HAPS Values mapped against the needs of system validation use mode

For the same reasons as firmware development it’s clear to see that HAPS FPGA-Based prototyping is the best technology to address the needs of System Validation use mode. In System validation you will be running lots of software against the hardware, doing interoperability and compliance testing against real hardware. No other technology enables you to do this, PRE-SILICON

Finally the software development use mode

HAPS Values mapped against the needs of software development

This is the traditional and most well know use mode for FPGA-based prototyping. Again the HAPS values map very well against the needs and requirements of Software Development. Really the only area in question is capacity. I thought it would be interesting to add the benefits of Hybrid Prototyping into the scoring for this particular use model.

HAPS Hybrid Prototyping mapped against the needs of Software development

Hybrid Prototyping, the combination of HAPS FPGA-based and Virtualizer Virtual Prototyping makes for a powerful platform for software development. Hybrid Prototyping combines the accuracy, performance and real world IO of HAPS with the capacity and differentiated debug capabilities of Virtualizer. I can tell you that a number of customers have adopted Hybrid Prototyping to improve their early software development activities. A number of these have been able to accelerate their software development and validation to a point where the software run on the real silicon on day one! Hey bonus, the green radar chart line looks like a fish, do you see it?

Anyway, there you go, the value of HAPS across multiple use modes. Is this consistent with your scoring of FPGA-based prototyping in respect to your project usage?

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Posted in ASIC Verification, FPGA-Based Prototyping, HW/SW Integration, Hybrid Prototyping, In-System Software Validation, IP Validation, Milestones, Project management, Real Time Prototyping, System Validation, Use Modes | No Comments »

Scared of Multi-FPGA Prototyping, Don’t Be !!!

Posted by Michael Posner on January 25th, 2015

Random image of someone looking scared

Last week I spent a week in Japan visiting users to discuss their FPGA-based prototyping challenges and explain how Synopsys can help. My overall take-away of the visits was that many companies want to expand their current single FPGA-based prototyping to multi-FPGA but fear the challenges associated with this. The summary of what I explained was pretty simple but to the point. #1 Having a defined methodology, flow and tool set is key. #2 Yes Multi-FPGA is more complex but it’s not as steep of a learning curve as you may think. And that’s it…..

#1 Having a defined methodology, flow and tool set is key

In respect to methodology you of course can refer to the FPGA-based Prototyping Methodology Manual, FPMM. (English and Japanese versions, 英語版と日本語版) I used Google translate so I hope I didn’t just offend the whole of Japan. Read the FPMM and you will become an expert prototyper but we all know that in this age of technology a summary is always nice. This is why I blogged about 3 Phase Approach to Successful Prototyping a while back. Yes, this is the blog with the upside down pyramid which at the time I thought was a great way to show the progression down through a funnel. The three phases are “Make Design FPGA Ready”, this is all about making the ASIC RTL FPGA friendly. “Bring Up Functional Prototype”, this is where you want to get onto the hardware as quickly as possible so you can functionally validate the design. Finally “Optimize Prototyping Performance”, pretty self-explanatory really.

Synopsys' definition of the three phases of FPGA-based prototyping. Follow this methodogy for success

Along with a defined methodology you need to utilize a tool flow which is designed for prototyping. I was amazed in Japan that many companies still tried to use the FPGA vendor tools for prototyping. I have nothing against FPGA vendor tools, they are great for their job which is FPGA synthesis. When I asked about the challenges these customer faced it was the same story I have heard before, ASIC clock conversion, gated clocks, memories and for the few that did multi-FPGA the key challenge was clock/reset synchronization and pin multiplexing. If you want to go fast on the freeway you don’t buy a bicycle you buy a car, it’s the same with prototyping. If you want to prototype buy a tool set which is designed for the purpose. I blogged about ASIC Gated clock conversion a while back, Unlocking the Secrets of ASIC Clock Conversion, which is just one example of a tool set designed for prototyping. Search my blog and you will find a stack more examples of what is possible by the tools these days. You need a tool set which is more than just a FPGA synthesis tool, you need a tool set that understands your challenges and can help with automation and dedicated capabilities.

#2 Yes Multi-FPGA is more complex but it’s not as steep of a learning curve as you may think.

If you have never prototyped before I’m not going to tell you to start doing multi-FPGA prototyping straight away, too many variables to take on at once. Start small, create a single FPGA-based prototype of a subsystem of your design. Don’t fall into the trap of thinking you can get away with using the FPGA vendor tools (see above) use a dedicated FPGA-based prototyping tool. This is exactly why we provide ProtoCompiler DX as part of the HAPS-DX system. ProtoCompiler DX is everything you need to implement the prototype and more as it includes high visibility debug capabilities. Once you have a prototype up and running on a single FPGA, then it’s time to expand, but don’t bite off more than you can chew, again start small. My suggestion is that you do not add anything new to the design you already have operational. Simply select a block or two from the existing design and move them into a 2nd FPGA. Using your multi-FPGA prototype tool, such as ProtoCompiler, get familiar with partitioning and pin multiplex IP insertion. Get familiar with customizing the hardware to match the needs of your design. Abstract Partition Flow Advantage, this is an important step to ensure that you create the highest performance multi-FPGA prototype. Once you have the same design up and running on two FPGA’s and a design flow and expertise in place you are ready for greater things. Go off and be successful in multi-FPGA prototyping.

The weather was pretty nice in Japan, here is the view from the hotel I was staying at:

View from my hotel room

We had lots of nice meals out, can you guess what was served at this restaurant?

I wonder what you serve here?

We did a day trip to Shin-Osaka via the bullet train, Shinkansen, what a mean looking train

Bullet Train, the Shinkansen, pretty mean looking

Nice view of Mount Fuji on the way up

Mount Fuji as seen from train from Tokyo to Shin-Osaka

While the Japanese can build a train that goes 200 MPH they have the same problem as the rest of the world, horrible coffee. Luckily when we arrived the local team treated me to vending machine coffee

Yum, vending machine coffee...

Of course many may question my judgment for even trying train coffee and vending machine coffee. You have to remember I was jet lagged and this was better than no coffee….. but only marginally.

I met the star of the film, Big Hero6, Bay Max, well at least his inflatable body double

Mick meets Bay Max, the star of the film Big Hero6

The funny thing is that Bay Max the real character is also inflatable so what this really a body double or his clone?

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps, Use Modes | No Comments »

Coming To A Lab Soon: Xilinx VU440 FPGA Devices

Posted by Michael Posner on January 16th, 2015

Xilinx Summary of the new UltraScale VU440 FPGA device capabilities for prototypers

In late 2013 I blogged about the newly announced Xilinx UltraScale devices, the VU440 specifically that will be the largest FPGA device on the market: http://blogs.synopsys.com/breakingthethreelaws/2013/12/xilinx-fpga%E2%80%99s-for-fpga-based-prototyping/

Well this week Xilinx officially announced that they have shipped the first samples of the VU440 devices: http://press.xilinx.com/2015-01-15-Xilinx-Delivers-the-Industrys-First-4M-Logic-Cell-Device-Offering-50M-Equivalent-ASIC-Gates-and-4X-More-Capacity-than-Competitive-Alternatives

Snippet from Xilinx Press release on the VU440 device and the fact that Synopsys received the first device samples

And check out who received the first of these samples…………………………… ok, you don’t need to read it, Synopsys did…….. We have optimized every generation of our HAPS prototyping systems for the highest system performance, greatest capacity while adding significant capabilities on top delivering prototyping specific features. We all know the FPGA device is a required component within the FPGA-based prototyping hardware but it’s not what defines or makes the solution useful. Anyone can slap an FPGA on a board but this does not help a prototyper as the device alone does not deliver the capabilities they require. Prototypers rely on a solution which includes a software implementation tool flow, integration between hardware and software accelerating time to operation, built in capabilities such as high speed pin multiplexing and high visibility debug to ease bug hunting while being modular and scalable. (side note: Synopsys offers exactly this…. just in case you didn’t know)

I recommend you also check out the VU440 demo video. It stars my friend Kirk from Xilinx who introduces the new device and the demo running ten ARM Cortex-A9 CPU’s, pretty impressive. http://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html#uniquePlayer1

Over the coming weeks I’m going to focus my blogs on the capabilities that the new Xilinx UltraScale devices deliver and the impact they have to prototypers. As noted above, an FPGA alone does not deliver FPGA-based prototyping so I will discuss how the device capabilities are expected to be integrated and leveraged delivering a solution.

Oh, and just because Synopsys has received Xilinx sample devices don’t expect a new HAPS next week. Delivering a solution requires hardware development, software development and a huge amount of validation. But I’m confident that when you are ready to adopt, Synopsys will be ready to deliver…..

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Posted in Admin and General, ASIC Verification, Bug Hunting, Debug, Early Software Development, FPGA-Based Prototyping, HW/SW Integration, In-System Software Validation, Man Hours Savings, Milestones, Technical, Tips and Traps | No Comments »

Prototyping at the Consumer Electronics Show, CES

Posted by Michael Posner on January 10th, 2015

Let me be the last to wish you “Happy New Year” and all that….

Of course it was the Consumer Electronics Show, CES recently and no good blogger would let this opportunity pass without writing something about it. Regardless of this I’m still going to write something. (If you got that joke comment below)

Hot at CES was self-drive cars with Advanced Driver Assistance Systems (ADAS), Sling TV, SuperHD TV’s, robots and of course wearables and the Internet of Things, IoT, because everyone wants a cooker with built in internet browser (well I do but as I already have a full PC in the kitchen for streaming TV and web browsing I will hold off on buying a cooker with similar capabilities)

It was nice to see that a number of projects that I know have been prototyped were being debuted at CES. It’s very fulfilling seeing a product go from idea to reality. While the big buzz was around everything you could see it’s the things you could not see which I want to discuss this week. These little electronic gadgets power the world of self-drive cars, wearables and IoT…. Yes I’m talking about sensors!!!!!

Wearables powered by sensors

ADAS Sensors

Lets face it, the sensors themselves don’t make the product but without them the device would not be able to operate so they really are the little product hero’s. Managing and data acquisition from these sensors can be a complex project in itself which is why Synopsys made it easier with the DesignWare Sensor and Control Subsystem.

DesignWare Sensor and Control Subsystem

This nifty subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more power efficient processing of the sensor data. The DesignWare Sensor and Control IP Subsystem provides designers with a complete, pre-verified solution that optimizes sensor fusion and actuator/motor control functions increasingly prevalent in automotive, mobile, industrial and IoT markets.

If you look at the block diagram above you can see that the interface to these sensors is usually pretty simple, UART, DAC/ADC, SPI, I2C and basic GPIO with the most complex interface being AMBA APB. I worked with a user recently who wanted to incorporate sensor information directly into their FPGA-based Prototype. The solution we came up with was to utilize off-the-shelf Peripheral Module interface, PMOD, boards. PMOD is a standard defined by Digilent Inc : http://en.wikipedia.org/wiki/Pmod_Interface

PMOD sensor example

Diligent have a wide range of these little modules: http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 covering various applications.

Note that the PMOD’s are typically a standard 6-Pin interface with 4 signals, one ground and one power pin so very low pin count. The user connected these to the new HAPS GPIO board, pictured below, in order to interface the modules into their custom design modeled within HAPS.

HAPS GPIO board, easy way to connect switches, LED's, sensors and much, much more into your HAPS modeled design

Note that the HAPS GPIO board is a vertical mounted board so just like the PMOD’s themselves do not take up much physical real estate.

HAPS GPIO board mounted

We ended up making full use of the HAPS GPIO board with multiple PMODs connected, interface to the ARM debugger, LED’s to signal various operational states and push switches to simulate user input. The GPIO board is very versatile with 3 standard 3.3V HAPS 10-pin GPIO headers, (Compatible with HAPS BIO1), 2 high-speed VCCO level GPIO headers (Red), 20-pin ARM JTAG header, Micro-USB for UART, MMCX clock connectors, 5V TTL header for serial LCD display, Level shifted header for I2C and SPI, 6 buttons and 4 LEDs on mini-daughter board which is connected to 3.3V HAPS 10-pin GPIO header when needed.

Unfortunately I was sick during the break so I didn’t get to as many of my little projects as I would have liked. I did however manage to complete one of them that I had been excited about for a while now. I made myself a portable gaming station complete with 412 games from the 1980-1990 era.

Mick Built Toys: Video Gaming Center. Waste away years of your life on mindless games

The whole setup packs away in a study roller case (which I got used which is why it’s so beat up). Open it up and pull the control station to the top of the box, plug it in and you are off. Favorite games like Pacman, Space Invaders, 1945, Donkey Kong and many, many more. I can now waste away many hours into the wee night playing mindless video games.

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Posted in Daughter Boards, DWC IP Prototyping Kits, FPGA-Based Prototyping, Getting Started, Humor, Mick's Projects | No Comments »

How Proven Solutions Reduce Risk

Posted by Michael Posner on December 19th, 2014

How Proven Solutions Reduce Risk

A couple of weeks back Synopsys announced that we had shipped, to date, over 5000 HAPS systems across more than 400 customers

Synopsys Ships Over 5,000 HAPS Prototyping Systems for Software Development, HW/SW Integration and System Validation

HAPS FPGA-based Prototyping Systems Help More Than 400 Companies Accelerate Time to First Prototype and Avoid Costly Device Re-Spins

This week a prospective user asked me why they should care how many systems Synopsys had shipped. It’s very simple I said, it reduces your risk. Now why this reduces risk takes a little longer to explain as there are many aspects of risk.

A proven track record,  such as the one Synopsys has with HAPS, is very important to risk reduction. When you buy a product from a company that has delivered multiple generations of a product as well as shipping in volume you know that the products are field proven. This means that your project is less likely to run into surprise issues reducing your projects risk. Risk reduction like this is always hard to measure but cannot be ignored.

A track record like this also means that the company is invested heavily in the success and support of the product. Synopsys has over 240 engineers involved with the FPGA-based prototyping products meaning that you can be assured of timely updates, great support and new generations of products right when you need them.

HAPS Units Shipped

I recommend you all check out the latest Synopsys Insight publication. There is a great article titled “Prototyping Imagination’s PowerVR Series6XT Dual-Cluster 64-Core GPU” which documents prototyping the Imagination GPU using ProtoCompiler and HAPS.

Synopsys Insight Article. Imagination PowerVR 6XT on HAPS using ProtoCompiler

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Merry Christmas and a Happy New Year !!!!!!!!!!!!!!!!!!!!!

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Unlocking the Secrets of ASIC Clock Conversion

Posted by Michael Posner on December 13th, 2014

open-safe

Warning: Technical Content!

I read an online article this week which flagged an issue with FPGA-based prototyping, clock conversion. Clock conversion is one of the most important aspects to successful prototyping and this week’s blog is dedicated to sharing information enabling you to be successful. Specifically I will cover automated Gated Clock Conversion, GCC, as the user realizes the highest benefits. With automated gated clock conversion you don’t need to maintain a separate RTL code branch for prototyping, you use the golden RTL source. Clock conversion done right ensures the prototype runs at the highest performance functionally equivalent to the source. If you look at the data from the Channel Media survey that Synopsys had conducted you see that for large FPGA-based prototyping, clock conversion is a major challenge.

Clock Conversion, the #1 challenge facing prototypers who do larger than 10M ASIC gate prototyping

Hold on, I forgot to cover why clock conversion is needed for FPGA-based prototyping. It’s one of the three laws, ASIC are not the same as FPGA’s, specifically in this case FPGA’s do not have the same clock resources like ASIC’s do. ASIC designs often use clock gating to reduce dynamic power and have complex clock logic to generate numerous internal clocks. In the ASIC flow, users do Clock Tree Synthesis to balance all the clock paths between the sources and destinations and avoid clock skews between them. The problem is the number of ASIC clocks in the design typically exceed the number of global clock lines available in the FPGAs. There are a limited number of dedicated global clock lines in FPGA devices and Global clock lines cannot accommodate clock generating and gating logic. Thus GCC is needed to convert these ASIC clock structures to FPGA comparable structures. You could do this manually but that’s time consuming and error prone.

One of the three laws of FPGA-based prototyping, ASIC clocks exceed the number of FPGA clocks

In Emulation oversampling type techniques are used to solve this problem, this is where all clocks are resolved to one synchronous clock source and all clocks are driven from derivatives of this clock. The benefit of this technique is that the conversion is fast and practically any type of clock tree structure can be handled. The main two disadvantages are #1 you tank performance as the system frequency is dictated by the slowest clock. #2 the design loses some fidelity as all clocks are synchronous to each other which may not reflect the true asynchronous clock behavior hiding issues in clock domain crossing circuits. Techniques similar to this such as the HAPS Clock Optimization in ProtoCompiler (I think I’ll blog about HAPS Clock Optimization in the future but for today I’ll focus on Gated Clock Conversion) which map clocks to HAPS hardware resources, are getting popular in FPGA-based prototyping as they can help reduce the time to first prototype enabling a prototype to be handed off to the software teams quickly. It will not have the high performance expected by the software engineers but it’s available quickly, handles almost any ASIC clock structures and this gives the prototype engineers a little breathing space to complete the high performance version.

Oversampling, the typical method used by emulation to handle clocks

Gated Clock Conversion, GCC, converts ASIC clock structures to FPGA friendly structures mapped to FPGA clock resources. GCC also needs to handle timing violations due to clock skew created because of clock gating logic. These violations are introduced on paths where the source and destination flops are driven by different clocks. Data from the source may reach the destination quicker/later than the clock resulting in hold/setup time violations in many paths. GCC has to ensure that there is no clock skew between two synchronous clock domains. The GCC capabilities of ProtoCompiler directly addresses both these conversion challenges in a fully automated fashion. ProtoCompiler maps to FPGA resources and moves the generated clock and gated clock logic from the clock pin of the sequential elements to the enable pins. This includes supporting implementation of these structures across block boundaries and across multiple FPGAs as part of partitioning.

Hold time violation example

Tool support of automated gated clock conversion is not a milestone it’s a journey as ASIC coding styles are continually evolving and the tools need to keep pace. ProtoCompiler has an extensive portfolio of supported structures including, but not limited to, Generated Clock, Gated Clock, Integrated Clock Gating Cells, Complex Sequential Cells, Instantiated Cells, Mixed Async Controls, Data Latches and MUX / XOR structures. With the correct clock constraints ProtoCompiler should automatically identify these gated clock structures and convert them to FPGA friendly structures. Below is an example of generated clock identification and the result of the automatic conversion.

Generated clock conversion example showing the result after ProtoCompiler automated conversion

In summary clock conversion is essential to successful prototyping. The ProtoCompiler Clock Conversion capabilities moves the generated clock and gated clock logic from the clock pin of the sequential elements to the enable pins, allowing sequential elements to be tied directly to the source clock, removing skew issues and reducing the number of clock sources in the design making it FPGA-based prototype friendly. Automated Gated Clock Conversion is just one of the many capabilities that ProtoCompiler delivers and is essential for prototypers.

Summary list of ProtoCompiler capabilites and benefits

Don’t forget that the FPGA-based Prototyping Methodology Manual, FPMM, has a section to help understand clock conversion and other ASIC design structure handling. Last week I had the pleasure to hang out with Rene Richter, one of the authors of the FPMM. Rene signed a book copy for me, this copy could be yours if you comment and answer the following question

How many HAPS systems has Synopsys shipped and to how many customers?

A signed copy of the FPMM

Answer the question by comment and if you get the answer right I will contact you to get your shipping addresss.

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Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Technical, Tips and Traps | 2 Comments »

Recap of what you missed, impactful blogs from the last 3 months

Posted by Michael Posner on December 5th, 2014

WOW

During a customer meeting last week I found myself explaining many different topic’s all of which I have blogged about over the last couple of months. I suddenly realized that while I blog every week that many of you might not get time to read them every week and miss important information. Below is a list of what I think are the impactful blogs from the last couple of months, just in case you missed them.

The Top 3 Myths of Prototyping – BUSTED. This was a particularly popular blog as it highlights the state of FPGA-based prototyping addressing capacity, time to first prototype operation and debug.

http://blogs.synopsys.com/breakingthethreelaws/2014/09/top-3-myths-of-fpga-based-prototyping-busted/

Solving the ASIC Prototype Partition Problem. Discusses a Synopsys whitepaper on partitioning of an SoC/ASIC to FPGA-based prototype using ProtoCompiler. ProtoCompiler generates a partition solution in minutes, (under 10 minutes in most cases).

http://blogs.synopsys.com/breakingthethreelaws/2014/08/solving-the-asic-prototype-partition-problem/

Abstract Partition Flow Advantage. Sort of goes hand in hand with the solving partition problems blog. This blog focuses on how to use an abstract partition flow to create the highest performance and optimal hardware interconnect and software partition for a given SoC/ASIC.

http://blogs.synopsys.com/breakingthethreelaws/2014/10/abstract-partition-flow-advantage

The Secret Ninja-Fu for Higher Performance Prototype Operation. It’s no secret how to achieve the highest performance prototype, you need an integrated solution and the ability to tailor the hardware inter-FPGA interconnect to the needs of the SoC/ASIC being modeled. Dedicated “fixed” traces just don’t cut it, they restrict the platforms flexibility and introduce interconnect bottlenecks.

http://blogs.synopsys.com/breakingthethreelaws/2014/04/the-secret-ninja-fu-for-higher-performance-prototype-operation/

3 Phase Approach to Successful Prototyping. Pretty much the bible of successful prototyping. Follow these three commandments will lead to successful prototyping.

http://blogs.synopsys.com/breakingthethreelaws/2014/10/3-phase-approach-to-successful-prototyping/

Going vertical for all the right reasons. Blog on developing and the advantages of vertical daughter boards. One of our customers read this post and then went on to develop a stack of custom vertical daughter boards for their specific needs. I’m happy that my blog helped this customer to be successful.

http://blogs.synopsys.com/breakingthethreelaws/2014/07/going-vertical-for-all-the-right-reasons/

Anyway, this should be enough to keep you busy for a week.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, IP Validation, Man Hours Savings, Use Modes | 1 Comment »

Mick’s Projects Update

Posted by Michael Posner on December 1st, 2014

The blog is about work in progress or completed

With it being USA Thanksgiving last week you would think I would have relaxed but I must say I’ve been very busy finishing off a couple of projects. So this week’s blog is on these my latest projects.

Firstly I put the finishing touches on the Sauna which was a birthday gift for my wife. It’s a kit from Finlandia which comes with almost everything you need, you just need to build it, roof it, tile the floor, install electric, you know, one of these “two weekend” projects

Outside view of our Finlandia Sauna

I had never done a shingle roof before but I must admit I really like the look. Actually the whole sauna looks and smells (cedar) nice.

The inside of our Finlandia Sauna kit

The inside is nice as well and the 8KW heater warms the sauna up in about 15 minutes even from freezing. It’s been great and the whole family is enjoying sauna time.

Next I completed the conveyor belt toy that I was building. It goes up and down with the use of a linear actuator and the conveyor moves objects like Lego’s from one end and drops them off at the others. In the pictures you can see it transporting from the toy box to the toy truck.  

Mick built conveyor belt toy. Belt runs, conveyor goes uo and down

Notice that I put a Lego plate on it so my son could build his own Lego structure on top of it.

Next project as a big one, a water feature for the local school. The school has an outside nature garden area and they wanted a water feature which the kids could play in, build dams and do all the fun things kids do with water. Well below is a picture of what I came up with.

The water feature I built for the local school

It uses a bilge pump to recirculate water from a tank. The surface is large pebbles and some odd rock columns I found at the local rock shop. It’s 12v battery powered that is recharged with a solar panel. It’s built with materials that can withstand the elements but the school thinks it looks so nice they are going to try and find somewhere to store it in the winter. It’s heavy with all the river rock but at least it has wheels to move it around.

Finally while with the in-laws over the thanksgiving weekend I thought I would play with my father-in-laws wood working lathe. I had bought him some wood blocks for Christmas and given them to him early…. I thought I would use one myself. Here is the result.

Mick Built Bowl, not bad for first time wood working lathe use

Not bad for a first time using a wood working lathe. The wood is Orange wood and it’s color matches it name

Opps, forgot one small project, I modified a box kit toy, the OWI-536 robot, to be wirelessly remote controlled. I don’t have a picture of that but I do have a short video: https://www.youtube.com/watch?v=bTg1RtThVj8 If you are wondering why it’s got a huge battery zip tied to the top stop and ponder this, I had all the parts for the modification laying around the garage.

Did you do any projects over the last couple of weeks? If yes send me a comment and tell me about them.

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Posted in Mick's Projects | Comments Off

Instant Productivity with IP Prototyping Kits

Posted by Michael Posner on November 21st, 2014

List of new DesignWare IP Prototyping kits, USB 3.0, UFS, PCIe and more....

This week Synopsys announced that we have expanded the IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols 

  • IP Prototyping Kits enable designers to accelerate prototyping, software development and integration of IP into SoCs
  • Supported protocols include USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0 and JEDEC UFS 

What are IP Prototyping Kits?

IP Prototyping Kits center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic (clock, reset, power management, and test logic) for a specific IP protocol. With these kits, designers can be instantly productive—integrate the IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware.

The kits include:

  • Synopsys’ HAPS-DX FPGA-based prototyping system with pre-configured IP and SoC integration logic
  • PHY daughter board
  • Simulation testbench
  • DesignWare ARC-based software development platform running Linux or Host PC Connection
  • Reference drivers
  • Application examples

Why is this important?

  • With the increase in SoC hardware and software complexity, companies need more from their IP providers to help meet their time-to-market schedules.
  • Delivering IP blocks alone is no longer adequate to address growing SoC design and integration challenges.
  • Synopsys goes beyond the traditional IP supplier paradigm, redefining what is expected from IP providers to help customers achieve successful IP integration with less effort, lower risk, and faster time-to-market.

When are the kits available?

  • IP Prototyping Kits for all listed protocols are available now.

Additional information

I’m personally very proud of the DesignWare IP Prototyping kits as I feel I helped drive the initial concept. Back in 2010 we had identified the need and in 2011 I presented the slide below at an offsite strategy meeting.

DesignWare IP on HAPS initial concept

The actual DesignWare IP Prototyping kits deliver this and far more and I have to give credit to the product managers who really drove this from concept to product as they did all the heavy lifting. I still like to think that I was there at the beginning.

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FPMM Book Achieves Major Milestone, More than 8000 Copies Distributed

Posted by Michael Posner on November 14th, 2014

FPMM Book Cover. FPMM is the holy grail of FPGA-based prototyping unlocking the secrets to successful prototyping

Recently Synopsys promoted that “Synopsys Virtual Prototyping Book Achieves Milestone of More Than 3000 Copies in Distribution to Over 1000 Companies” – http://news.synopsys.com/2014-11-05-Synopsys-Virtual-Prototyping-Book-Achieves-Milestone-of-More-Than-3000-Copies-in-Distribution-to-Over-1000-Companies Virtual Prototyping continues to gain momentum including Hybrid Prototyping, which combines Virtual Prototyping with FPGA-based prototyping. The VP book statistics prompted me to have a look at the FPGA-based Prototyping Methodology Manual, FPMM statistics.

To date there have been over 6000 FPMM downloads across 2800 different companies and over 2500 free books handed out. WOW. I expect a bit of overlap between the two but still that’s got to be over 8000 copies distributed. I’m happy that the FPMM has been able to help so many engineers around the world.

Looking at the challenges facing these prototypers, below image, you can see that conversion of ASIC to FPGA is still rated as #1.

Challenges identified by prototypers who downloaded the FPMM. These challenges are solved by integration of HW and SW prototyping tools such as the Synopsys HAPS and ProtoCompiler products

Actually the #2 challenge, clocking issues, really falls into the this same category. As previously blogged, these challenges are not solved with just software or just hardware changes, they are solved by integration. When the software has built in understanding of the hardware and when the hardware can be customized to the needs of the SoC many of the challenges disintegrate.

A great example of the value of integration is the DesignWare IP Prototyping Kits which are part of the Synopsys IP Accelerated Initiative. DesignWare IP prototyping kits deliver a comprehensive IP subsystem which enables immediate productivity for both Hardware and Software engineers. Individually IP & FPGA-based prototyping deliver value but when combined the value is increased. It’s like the 1+1 = 3.

Talking of IP, DesignWare USB 3.1 IP is now available. http://www.synopsys.com/Company/PressRoom/Pages/usb-3-1-news-release.aspx . I have been talking about USB 3.1 for a while now and blogged about it here. You can also find a video of the DesignWare IP for USB 3.1 running on the HAPS-70 systems here https://www.youtube.com/watch?v=isQ7cvuyoTw

Enjoy

Do you have a topic you would like me to blog about? If so, drop me a comment and I’ll pop it in the queue.

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, IP Validation, Technical, Tips and Traps | 1 Comment »