So… In our previous blog, we promised you an interview with one of our speakers at DesignCon AMS tutorial (that’s if you manage to read my blog until the end ).  Well here we go !

DesignCon AMS tutorial emphasizes on S-parameter modeling and simulation for Signal Integrity Analysis. As a chairman for this track, I contacted three senior SI engineers in this domain:Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys.

In this interview, Brad Brim shares his insights about his incoming experience as a speaker for this event and his experience using HSPICE.

Brad Brim has over 20 years experience in electronic design automation. His responsibilities with Sigrity include market and product management for electrical model extraction and system-level simulation across chip, package and board domains. His present areas of focus are signal integrity and power integrity for high-speed designs. His background includes roles in development, applications and marketing for both components and systems from high-speed digital to RF/microwave/antenna.

Q: could you please describe your job responsibilities? What kind of circuits did you simulate using HSPICE and which specific simulator capabilities did you focus on?

My role at Sigrity is “marketing”, but please don’t hold that against me   This includes the familiar responsibilities of product definition and promotion but also includes being a technical expert for internal and external consulting.  The products for which I am directly responsible are in the area of “extraction” and “analysis” for signal integrity (SI) and power integrity (PI) across the physical domains of chip, package and board.  My background includes many years of EM and circuit simulation algorithm development and applications of such to a large breadth of high-frequency and high-speed designs.  My experiences and current responsibilities span design simulation for components, circuits and complete systems.

I apply a number of simulation tools in my daily efforts, including Sigrity extraction tools and Synopsys HSPICE.  The majority of Sigrity tool users are also HSPICE users and the synergies between the two toolsets are of primary importance to our tool users.  Whether S-parameter models extracted by PowerSI, RLGC and IBIS package models from XtractIM or power-aware IBIS 5.0 buffer models converted from transistor netlists by T2B; nearly all model extractions by the tools for which I am responsible are eventually applied in HSPICE. Users of Sigrity tools are typically concerned with whole-board/package designs and combining chip/package/board models for characterization of entire systems. Even our block-level system analysis environment SystemSI applies HSPICE as a circuit simulation engine for characterization of serial channels and parallel buses. We provide technical support on a daily basis to our customers who are applying S-parameters directly in HSPICE, or indirectly applying such through HSPICE-specific macromodels. We have, as have our tool users, noticed a marked improvement in recent releases of HSPICE for efficiency and robustness in dealing with frequency domain model data. This has enabled our tool users to address not just wider parallel bus designs but to also include greater electrical resolution (more nodes) of the power delivery network (PDN) in their system simulations. This is especially important for power-dominated applications such as simultaneous switching output (SSO), where detail of the PDN must be included for proper system-level characterization. Even for characterization of high-speed serial channels the ability to handle high-pin-count S-parameter models enables consideration of PDN effects and their influence on jitter.

Q: Can you tell us more about the section of the tutorial you are covering? What can attendees gain from your presentation ?

My portion of the tutorial is to review the basics of S-parameters. All of what I will address can be found in the literature or college texts. However, there are a number of subtle details we all seem to forget all too-often. These details are often the assumptions upon which further analysis of circuits and systems are based, and as we all know, false assumptions lead to questionable analysis results. For example, it is critically important to recall that S-parameters are a “differential” measurement; a two-terminal concept, just like voltage. You know the difference of voltage between the two terminals, but not the absolute (i.e. global ground referenced) voltage at either of the two terminals. Many EDA tool users, and even some EDA analysis tools, tend to forget this concept and therefore improperly apply S-parameter models. This often results in questioning of the S-parameter models rather than the manner in which they were applied. My goal is to convey an intuitive understanding of these concepts in hopes the attendees will learn how to more effectively and correctly apply S-parameter models for their circuit and system level simulations.

Q: What is your overall impression on using HSPICE for Signal Integrity? What are the key capabilities and where do you think SYNOPSYS should focus on moving forward?

I observe HSPICE to be one the most widely applied EDA tool by Signal Integrity engineers worldwide. A number of other schematic capture environments, layout based SI-only simulations and assorted time-/frequency-domain circuit simulators are commonly applied for boards and packages. But even as a stand-alone circuit simulation engine HSPICE may be the most widely applied tool for SI applications. This is because pre-layout netlist based investigations are supported well with excellent circuit simulation algorithms, transistor-level circuit convergence is good and libraries are available for many of the devices and circuits applied by SI engineers. Then, for verification of system-level behavior HSPICE is again applied to assemble component, circuit and whole-board/package and even chip models to simulation of complete systems. HSPICE has addressed a number of detailed challenges to support this verification flow. One example is direct application of Sigrity’s broadband network parameter (BNP) file format for S-parameter data. This provides HSPICE with the ability to read very compact sized data files while retaining access to full spectral content of the underlying data; simultaneously boosting accuracy and increasing accuracy.

You have certainly received feedback from may HSPICE users for where they wish enhancements. There’s always what I call “great taste, less filling”, which is larger/faster simulations that consume less memory to complete. One area of concern I hear repeatedly from SI engineers, especially those who apply transistor-level buffer models is “convergence”. You’ve made good progress in recent releases with application of frequency-domain data and I assume this effort will continue. In addition HSPICE now supports power-aware IBIS 5.0 buffer models. This is a necessary step to enable full-bus design of memory interfaces and their seemingly now-required SSO analysis with PDN effects. CPU core speeds are not increasing as rapidly as in years past so parallelization or distributed computing may be an avenue to increase both speed and capacity. This can require a lot more work than one may first expect, since basic algorithms and sequential process assumptions applied throughout many years of code development must be reexamined.

Q- What do you foresee for Signal Integrity in the next five years?

I foresee SI/PI engineers addressing larger portions of the system and doing so with more electrical resolution. Switching speeds will continue to increase, driving bandwidths even higher for SI/PI engineers to consider. Wider memory buses will be characterized in-full and the interaction between unique buses will be desired in simulations. The interaction amongst many high-speed serial channels will be required. In a sense, high speed serial and parallel bus design concepts may become more similar than they are today. I foresee a further blending of SI and PI issues and the engineering responsibility for such. It is quickly becoming a requirement to include PDN effects, even for high-speed serial channel design. These practices imply circuit simulations of increasingly larger size and complexity. A larger number of CPU cores will be available for engineering desktop compute environments and EDA tool users will expect full utilization of their compute hardware. Distributed computing environments are becoming more popular in larger corporations and this trend is likely to continue. However, I suspect design data security issues may mitigate short term adoption of cloud computing for EDA applications. All of this implies there are bright employment opportunities for many more SI/PI engineers. Further, both Synopsys and Sigrity have a lot on our plates to address these future needs.

As a chair(wo)man for the AMS track at DesignCon, I wanted to talk about a special event we are offering at DesignCon. We specifically created this year a tutorial to emphasize on S-parameter modeling and simulation for Signal Integrity Analysis and we contacted three senior SI engineers in this domain: Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys.

A few key takeaways:

- Understanding S-parameter definition and implicit assumptions

- How to effectively and properly applying S-parameters for chip-centric and system-level simulation

- Understanding potential problems with measurement and simulation data

- Judging the quality of S-parameter and channels

- Troubleshooting and solving S-parameter issues in time domain simulations

- Learning strategies for conversion in transient simulators

- Constructing and applying stressed eye in a pre-hardware context; Relating simulated eye parameters to targeted BER

The tutorial can be accessed at:

http://schedule.designcon.com/

(You will need to select Analog and Mixed signal verification track and half day tutorial).

If you have any questions regarding this tutorial, feel free to contact me anytime. As usual, your feedback is more than welcome !

Next, I will post an interview I conducted with Brad Brim, one of our speakers. We talked about the tutorial content as well as his experience using successfully HSPICE  for Signal Integrity. See you at our next post ! A bientot !

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up
your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

We are pretty excited about this new integration and held a webinar on the topic this week. If you missed, don’t worry, it is archived on our website and you can watch it here.

Fred

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

Rather than trying to completely automate away the layout phase (as some have tried) we chose a different path. In analog designs the layout designer must have complete manual control of the layout so how do you automate that?

We chose a new path
 we decided not to enforce our automation on designers but rather give them a toolbox of powerful new features that simplify their jobs and help get it done quicker. This is the first in a series of blog entries that will feature some of the ideas our team came up with after talking to many, many layout engineers.

Today’s topic is zooming and it’s evil twin counting grids. Layout designers often spend a great deal of time zooming into a region to start a wire, then zooming out to route it followed by a zoom back in to finish aligning the end of the wire. That’s a lot of clicks and often the designer has to go back across the wire counting grids and moving segments to make sure that he hasn’t violated the rules.

What if you could wire at high-altitude and eliminate the zooms? What if you could click near a terminal or a gate and have the new wire adopt the width, snapped to and pre-aligned with the terminal and just start wiring immediately?

We call it “SmartConnect” and it does just that. Another cool feature is SmartConnect’s “Alignment Markers” that make it obvious when you are aligned with the left, center or middle of another object.

Sounds simple but these features enable very rapid wiring without forcing the layout engineer to accept somebody else’s idea of what makes a good layout.

‘Til next time, keep wiring away and stay tuned. We’ve got a lot more stuff in the pipe for our next release that I think you will really like


Fred

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

One of the Custom Designer developers  said, “That capability looks a lot like this new feature that will be released in the up coming version of Custom Designer.” We all got VERY excited when he then demonstrated the beta version of this new feature to the assembled group. It was really cool and very useful. We then asked for a minor extension of the feature and he had that up and running in a trial tcl script within the hour. Sweet. We can hardly wait for the next release.

Later that night at dinner, one of the corporate apps engineers came up to me and said, “You don’t remember do you? I visited you 7 months ago with a list of planned features for CD and you looked it over and said –  “these are all OK but what would be really nice is if you could…” and then you described this new feature. We thought it was a great idea and put it at the top of the list.” I then told him that it was no wonder I had liked the new feature so much but I also told him I was terribly disappointed. When he asked why I was upset I said “Well if I had remembered I had suggested it I could have said ‘7 months – what took you so long!’”.

So when you see the next version of Custom Designer, there is at least one really cool feature that will blow you away (I haven’t seen the other cool one yet – just heard about it). You will know which feature it is because it is so useful. You will also know how we feel to work with an analog design tool that is growing and improving DAILY with developers who listen to us – how sweet it is!

Bob Lefferts

Hi Everybody!

First my apologies for our silence over the past couple of weeks. We’ve had our head down in preparation for and the delivery of the 47th Design Automation Conference in Anaheim last week (47? Really?)

Synopsys had an outstanding DAC this year and had many announcements to go with it. In addition to our main booth, we showed Custom Designer, HSPICE and CustomSim at a number of different venues throughout the show and that kept us, ah, rather busy.

Our demo suites were jammed and we hosted numerous customers, editors, analysts, breakfasts, lunches and dinners and the transcripts of many of those will be available soon. Stay tuned.

The show is over and now that we can breath, we’ll get back on track with some new posts about some great new technology we have coming up.

Fred

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast
 One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency
) can be set independently from the y-axis (be it voltage, current
) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end




; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat 
 ***
   *** loading waveform file t1.dat    
 ***
   *** loading waveform file t2.dat    
 ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list



Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

Happily, improvements in processor technology have provided new machines with multiple processing cores on the same chip. Although HSPICE has had the ability to use these cores for several years now that hasn’t stopped us from making improvements in our multi-core processing capabilities.

Synopsys recently released a new capability in HSPICE that improves the scalability of simulations on machines with four or more cores. This new high-performance multi-processing capability is seeing great scalability on multiple core machines:

These are average speedups on top of the over 5x speed improvements on single-core HSPICE that our team has already achieved over the past few years. Many of our simulation tests on four cores are reaching even higher performance while maintaining the golden accuracy you demand from HSPICE.

I’d like to go into more detail about how this great new technology works but given that it is patent-pending, I will save that discussion for another blog entry.

Kishore

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

We pondered how we could do this work within the tight time schedule allotted by the customer. They needed a working design in three months and we didn’t have time to start from scratch.

Enter Custom Designer. In use by hundreds of our Solutions Group analog IP designers, its open framework, features, powerful scripting capabilities and overall flexibility were to be the key to resolving this problem.

For those of you who missed my SNUG presentation, we’ve written it up and posted it on the Synopsys website:

Reverse Process Migration from 65nm to 130nm in Under Three Months

Enjoy,

Bob