Archive for the 'Signal Integrity' Category

Happy Friday,

“Chose promise, chose due” – In other words, I owed you a full report on our S-parameters tutorial

As mentioned in one of my previous posts, we received a lot of interest for the AMS tutorial we created for DesignCon 2012. We managed to hold 120 persons in average for three hours talking about S-parameter modeling for SI without even locking doors . Our three Speakers (Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys) explored this topic from an intermediate to a more advanced level. Because each speaker is an expert in a different area, we were able to cover this topic from different angles and with a lot of depth. In this interview, Amir, Brad and Donald talk about their presentations and share their overall impressions (I have also listed each presentation below). We will further explore and refine this topic at next year tutorial so you’d better be there  !

Q>  I will be including each of your presentations at the end of this post. Would each of you give a few lines summary of your presentation?

Brad Brim

[Brad]  My presentation can be described as: An introduction to S-parameters with a focus on issues relevant to designers of chips/packages/boards and systems with high-speed signals. A few basic definitions are covered with the major focus being on practical issues SI engineers tend to learn and re-learn all too often.

[Amir] My presentation is titled “SPICE Simulation with Frequency Domain Models” and covers the following topics: What to learn about the channel just by observing its S-parameter and impulse response and group delay;  Correlation/Calibration the models with measurements to increase accuracy; S-parameter data interpolation/extrapolation; What to do about missing DC data, how to “interpolate”, simulate or estimate it; Requirements for transient simulation; passivity, causality; Convolution and maximizing simulator performance; Best practices at getting good S-parameters from EM solvers; Efficient EM solver data formats for SPICE simulation; Handling reference planes for S-parameter Ports; Defining high-speed link simulations in SPICE; Special cases: Power delivery systems and needed modifications to S-parameters; Nonlinear I/O modeling with IBIS and encrypted HSPICE buffers; and Adding DJ and RJ effects with SPICE Thermal noise.

[Donald] My presentation explains how to combine S-Parameters with active models to simulate high-speed serial links and assess performance using eye diagrams.  Now that S-Parameter and AMI models are flowing more freely throughout the industry it has become possible to examine and validate link behavior, pre-hardware.  I offer a full-day Seminar on this topic that shows how to use these techniques to validate a design and its compliance with the major serial standards, even though the standards still have a post-hardware bias.  There’s huge value in figuring out how to do this before you fabricate or assemble anything.

Q> It appears that this topic was really well received among DesignCon community. Which feedback did you receive from the attendees?

Amir Motamedi

[Brad]  I received positive feedback from attendees concerning the breadth of what was covered. Not from a technical or theoretical perspective but from basic concepts to detailed application for high-speed serial link systems. My choice not to focus on regurgitating basic concepts and definitions that may be found elsewhere on the web, in college texts or in commercially available training classes seemed to resonate with attendees; especially the lessons I covered for which I work with EDA tool users on a daily basis to learn and re-learn. Amir’s intuitive description of the relevance of S-parameter behaviors was also noted as a big positive by attendees. They liked the practical knowledge Amir was able to share based on his experience applying S-parameters in his designs. Donald’s presentation addressed a hot topic for DesignCon for the past few years – high speed serial links. Since a large portion of the attendees are focused on board design, his system-centric focus of bits-to-bits serial link communications through each chip/package/board was highly relevant. For all three presentations I received feedback they were received well in the tutorial nature intended; not as too detailed or too factual, but rather fun and informative.

[Donald] One attendee claimed it was the most useful session he attended.  I think the combination of the talks – all the way from matrices to Bit Error Rates – scratched where people itched.

Q> I noticed DesignCon had an increasing content of AMS/RF related papers and subjects. Have you noticed a change in DesignCon traditional venue?

[Brad]  I have observed the number of RF-related topics peak and valley over the years at DesignCon. Each year the TPC (technical program committee) does a good job of maintaining the traditional focus of DesignCon with its paper selections. In fact, notice the title of the RF-centric track is “RF/Microwave Techniques for Signal Integrity”. This is true also for the “Test and Measurement Methodology” track. Other conferences such as IEEE MTT Symposium are intended for more pure RF/microwave topics.  RF/microwave measurement conferences also exist; as I am suspect Analog IC conferences are plentiful. I believe the “mixed-signal” portion of AMS and analog-specific designs required to support high-speed signaling is very relevant to DesignCon attendees. As bandwidths increase for high-speed signals, we can expect to see a continued increase in the analog content present in topics of interest to DesignCon. For example, the coupling of analog to digital signal and power noise seems a relevant topic for DesignCon, though the design of a purely analog circuit not relevant to high speed signaling may not be.

[Donald] Higher frequencies have forced SI Engineers to increasingly borrow from RF tools and techniques.  In addition, the abundance of silicon gates has pushed things we used to solve on the PCB inside silicon causing convergence of SI, AMS, and DSP design techniques.  So yes, things are changing – they always do.

Q> which subjects would you add for our next year tutorial? Are there emerging trends/hot topics we should cover?

Donald Telian

[Brad]  We should ask ourselves what questions we ask ourselves or what questions our colleagues and customers ask us repeatedly. As authors or “faculty” as DesignCon called us this year, we sometimes forget the presentation is for the benefit of the attendee (not to hear ourselves talk). This is especially true for a tutorial forum. Even if we personally believe the issue to be trivial or covered well in other readily available media we should consider the frequency with which the issue comes up as an indicator of need for further discussion. A tutorial forum is ideal for this type of discussion, since the authors are likely accustomed to addressing the topic daily and have the skill and readily available materials to share with DesignCon attendees.
I was surprised at the high percentage of package and board designers who attended this AMS-sponsored tutorial. Seems the topic was not as well understood even by these attendees, as I had suspected it would be unfamiliar for AMS IC-centric designers.

[Donald] Emerging equalization techniques and associated IC/PCB design capabilities are the next big thing that will push interfaces faster than 10 Gbps into the mainstream.  Engineers are calling for Tutorials that help them bring these things together at the system level.

**********************

Brad’s slides:

BradBrim_TutorialSlides_final

Amir’s slides:

Amir_slides

Donald’s slides:

Donald_tutorial

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week…Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Happy Thursday !

I would like to inform you of our Synopsys HSPICE Special Interest Group event. In addition to having a culinary experience and meeting great people , you will be able to network with peers and hear what industry leaders have to say about using HSPICE in some of today’s most challenging designs. The 2012 event is being held on January 31 at the Marriott Hotel in Santa Clara and will focus on Signal and Power Integrity.

The event format is the following:
DATE:    January 31, 2012
TIME:    6:00 p.m.- 8:30 p.m.
LOCATION:        Santa Clara Marriott Hotel
2700 Mission College Blvd.
Santa Clara, CA 95054
map & info.

HSPICE SIG EVENT AGENDA
6:00 – 7:00 p.m.                Registration and Cocktail Hour
7:15 – 8:15 p.m.                Dinner and Technical Presentations:
Altera: “28nm MOSFET Aging Modeling and Simulation Using HSPICE MOSRA”
Cavium: “HSPICE Signal Integrity Portfolio for High-Speed SERDES Channel Design”
Micron:”Simulating IBIS 5.0 Power-aware Models using HSPICE”
8:15 – 8:30 p.m.                Q&A and Prize Draw

This event is a great opportunity for users to exchange challenges, solutions and best practices as well as to network with peers.
If you are interested, I have included our registration page below:

http://app.connect.synopsys.com/e/es.aspx?s=700&e=29779&elq=2e0672756e024505b1dfd4f2122c3374

I will post next an interview I conducted with Amir Motamedi, one of our speakers for last year event, where he shares his insights about  HSPICE SIG event and Signal Integrity.

Hope to see you there !

So… In our previous blog, we promised you an interview with one of our speakers at DesignCon AMS tutorial (that’s if you manage to read my blog until the end ).  Well here we go !

DesignCon AMS tutorial emphasizes on S-parameter modeling and simulation for Signal Integrity Analysis. As a chairman for this track, I contacted three senior SI engineers in this domain:Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys.

In this interview, Brad Brim shares his insights about his incoming experience as a speaker for this event and his experience using HSPICE.

Brad Brim has over 20 years experience in electronic design automation. His responsibilities with Sigrity include market and product management for electrical model extraction and system-level simulation across chip, package and board domains. His present areas of focus are signal integrity and power integrity for high-speed designs. His background includes roles in development, applications and marketing for both components and systems from high-speed digital to RF/microwave/antenna.

Q: could you please describe your job responsibilities? What kind of circuits did you simulate using HSPICE and which specific simulator capabilities did you focus on?

My role at Sigrity is “marketing”, but please don’t hold that against me   This includes the familiar responsibilities of product definition and promotion but also includes being a technical expert for internal and external consulting.  The products for which I am directly responsible are in the area of “extraction” and “analysis” for signal integrity (SI) and power integrity (PI) across the physical domains of chip, package and board.  My background includes many years of EM and circuit simulation algorithm development and applications of such to a large breadth of high-frequency and high-speed designs.  My experiences and current responsibilities span design simulation for components, circuits and complete systems.

I apply a number of simulation tools in my daily efforts, including Sigrity extraction tools and Synopsys HSPICE.  The majority of Sigrity tool users are also HSPICE users and the synergies between the two toolsets are of primary importance to our tool users.  Whether S-parameter models extracted by PowerSI, RLGC and IBIS package models from XtractIM or power-aware IBIS 5.0 buffer models converted from transistor netlists by T2B; nearly all model extractions by the tools for which I am responsible are eventually applied in HSPICE. Users of Sigrity tools are typically concerned with whole-board/package designs and combining chip/package/board models for characterization of entire systems. Even our block-level system analysis environment SystemSI applies HSPICE as a circuit simulation engine for characterization of serial channels and parallel buses. We provide technical support on a daily basis to our customers who are applying S-parameters directly in HSPICE, or indirectly applying such through HSPICE-specific macromodels. We have, as have our tool users, noticed a marked improvement in recent releases of HSPICE for efficiency and robustness in dealing with frequency domain model data. This has enabled our tool users to address not just wider parallel bus designs but to also include greater electrical resolution (more nodes) of the power delivery network (PDN) in their system simulations. This is especially important for power-dominated applications such as simultaneous switching output (SSO), where detail of the PDN must be included for proper system-level characterization. Even for characterization of high-speed serial channels the ability to handle high-pin-count S-parameter models enables consideration of PDN effects and their influence on jitter.

Q: Can you tell us more about the section of the tutorial you are covering? What can attendees gain from your presentation ?

My portion of the tutorial is to review the basics of S-parameters. All of what I will address can be found in the literature or college texts. However, there are a number of subtle details we all seem to forget all too-often. These details are often the assumptions upon which further analysis of circuits and systems are based, and as we all know, false assumptions lead to questionable analysis results. For example, it is critically important to recall that S-parameters are a “differential” measurement; a two-terminal concept, just like voltage. You know the difference of voltage between the two terminals, but not the absolute (i.e. global ground referenced) voltage at either of the two terminals. Many EDA tool users, and even some EDA analysis tools, tend to forget this concept and therefore improperly apply S-parameter models. This often results in questioning of the S-parameter models rather than the manner in which they were applied. My goal is to convey an intuitive understanding of these concepts in hopes the attendees will learn how to more effectively and correctly apply S-parameter models for their circuit and system level simulations.

Q: What is your overall impression on using HSPICE for Signal Integrity? What are the key capabilities and where do you think SYNOPSYS should focus on moving forward?

I observe HSPICE to be one the most widely applied EDA tool by Signal Integrity engineers worldwide. A number of other schematic capture environments, layout based SI-only simulations and assorted time-/frequency-domain circuit simulators are commonly applied for boards and packages. But even as a stand-alone circuit simulation engine HSPICE may be the most widely applied tool for SI applications. This is because pre-layout netlist based investigations are supported well with excellent circuit simulation algorithms, transistor-level circuit convergence is good and libraries are available for many of the devices and circuits applied by SI engineers. Then, for verification of system-level behavior HSPICE is again applied to assemble component, circuit and whole-board/package and even chip models to simulation of complete systems. HSPICE has addressed a number of detailed challenges to support this verification flow. One example is direct application of Sigrity’s broadband network parameter (BNP) file format for S-parameter data. This provides HSPICE with the ability to read very compact sized data files while retaining access to full spectral content of the underlying data; simultaneously boosting accuracy and increasing accuracy.

You have certainly received feedback from may HSPICE users for where they wish enhancements. There’s always what I call “great taste, less filling”, which is larger/faster simulations that consume less memory to complete. One area of concern I hear repeatedly from SI engineers, especially those who apply transistor-level buffer models is “convergence”. You’ve made good progress in recent releases with application of frequency-domain data and I assume this effort will continue. In addition HSPICE now supports power-aware IBIS 5.0 buffer models. This is a necessary step to enable full-bus design of memory interfaces and their seemingly now-required SSO analysis with PDN effects. CPU core speeds are not increasing as rapidly as in years past so parallelization or distributed computing may be an avenue to increase both speed and capacity. This can require a lot more work than one may first expect, since basic algorithms and sequential process assumptions applied throughout many years of code development must be reexamined.

Q- What do you foresee for Signal Integrity in the next five years?

I foresee SI/PI engineers addressing larger portions of the system and doing so with more electrical resolution. Switching speeds will continue to increase, driving bandwidths even higher for SI/PI engineers to consider. Wider memory buses will be characterized in-full and the interaction between unique buses will be desired in simulations. The interaction amongst many high-speed serial channels will be required. In a sense, high speed serial and parallel bus design concepts may become more similar than they are today. I foresee a further blending of SI and PI issues and the engineering responsibility for such. It is quickly becoming a requirement to include PDN effects, even for high-speed serial channel design. These practices imply circuit simulations of increasingly larger size and complexity. A larger number of CPU cores will be available for engineering desktop compute environments and EDA tool users will expect full utilization of their compute hardware. Distributed computing environments are becoming more popular in larger corporations and this trend is likely to continue. However, I suspect design data security issues may mitigate short term adoption of cloud computing for EDA applications. All of this implies there are bright employment opportunities for many more SI/PI engineers. Further, both Synopsys and Sigrity have a lot on our plates to address these future needs.

As a chair(wo)man for the AMS track at DesignCon, I wanted to talk about a special event we are offering at DesignCon. We specifically created this year a tutorial to emphasize on S-parameter modeling and simulation for Signal Integrity Analysis and we contacted three senior SI engineers in this domain: Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys.

A few key takeaways:

- Understanding S-parameter definition and implicit assumptions

- How to effectively and properly applying S-parameters for chip-centric and system-level simulation

- Understanding potential problems with measurement and simulation data

- Judging the quality of S-parameter and channels

- Troubleshooting and solving S-parameter issues in time domain simulations

- Learning strategies for conversion in transient simulators

- Constructing and applying stressed eye in a pre-hardware context; Relating simulated eye parameters to targeted BER

The tutorial can be accessed at:

http://schedule.designcon.com/

(You will need to select Analog and Mixed signal verification track and half day tutorial).

If you have any questions regarding this tutorial, feel free to contact me anytime. As usual, your feedback is more than welcome !

Next, I will post an interview I conducted with Brad Brim, one of our speakers. We talked about the tutorial content as well as his experience using successfully HSPICE  for Signal Integrity. See you at our next post ! A bientot !

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up…your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!