Archive for the 'Nanometer CMOS' Category

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up
your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

We are pretty excited about this new integration and held a webinar on the topic this week. If you missed, don’t worry, it is archived on our website and you can watch it here.

Fred

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

We pondered how we could do this work within the tight time schedule allotted by the customer. They needed a working design in three months and we didn’t have time to start from scratch.

Enter Custom Designer. In use by hundreds of our Solutions Group analog IP designers, its open framework, features, powerful scripting capabilities and overall flexibility were to be the key to resolving this problem.

For those of you who missed my SNUG presentation, we’ve written it up and posted it on the Synopsys website:

Reverse Process Migration from 65nm to 130nm in Under Three Months

Enjoy,

Bob

Hello, and welcome to our new blog on the state of custom and AMS IC design at Synopsys. We set out some years ago to address the need for alternatives in custom and analog design software, and with the launch of Galaxy Custom Designer in 2008 we are seeing that vision realized.

Synopsys has amassed a powerful presence in the circuit simulation market. Our flagship products, HSPICE and CustomSim, form the backbone of transistor-level design and verification worldwide. Behind these products is a very talented group of individuals who are hard at work on solving some of the thorniest problems facing the EDA market.

Our own digital and analog IP design groups use these products to provide cutting-edge solutions for tough problems. Our proven AIP is used in designs worldwide and before it gets to you, it’s been through the wringer by a set of designers who have no mercy for bad chips.

I’d like to tell you what we have in store for you on this blog.

We have asked two of our most respected thought leaders in their domains to post entries on this blog:
Kishore Singhal: circuit simulation expertise
Bob Lefferts: a user’s perspective designing with Synopsys’ custom design flow
and, of course, I will continue to post my thoughts on custom design and implementation

In the coming weeks, each blogger will post entries on topics in his domains of expertise. You can expect everything from the technical background of the tools, tips and tricks to make you more productive, and ways to extend and integrate your design flows. And every now and then members of our technical teams will also share their experiences with you.

So thanks for reading this reinvigorated Analog Insights blog today. I can guarantee you—there’s a lot more to come!

No… I’m not referring to the infamous Denali Party at DAC. It’s really hard to be hip if you dress like those guys in Disco Inferno. No, if you really want to get HIP at DAC, you need to know about the HSPICE Integrator Program. Clever… eh?

I think we all know that SPICE simulation is the #1 day-to-day workhorse tool for circuit designers. You’ve seen me write about this before (Analog design is NOT black magic… but it is VERY hard, and More “black magic” mumbo jumbo… will it ever end?). Nevertheless, there is still a lot of whining in the press (generally not from analog designers) about how SPICE has been in use for so long… so therefore nothing new has been done in analog EDA. To which I say hogwash!. It may be true that SPICE has been around at least as long as disco, but the difference is that SPICE, and particularly HSPICE has never gone out of style.

There is a lot that’s new with HSPICE and Fast-SPICE, which you can hear about in the Synopsys DAC presentation titled “Advances In Circuit Simulation and Mixed-Signal Verification“.

Here is the description:

Come see the latest improvements in Synopsys’ transistor-level circuit simulation solution. This session will cover updates on the latest 40-nm device models, performance improvement and multi-core in HSPICE, fast and accurate transient simulation and mixed-signal verification in FastSPICE, and the best-in-class mixed-signal waveform analysis and debug capabilities.

Other simulators compare themselves to HSPICE because HSPICE is the incumbent gold standard in the industry. HSPICE has the highest level of silicon correlation in the industry, and recently Synopsys partnered with TSMC to develop the modeling interface technology that will be used for 40nm and beyond. An entire network of companies (or ecosystem in marketing speak) provide value-added solutions that employ HSPICE as the core simulation engine. To better support this HSPICE ecosystem, Synopsys recently created the HSPICE Integrator Program. Twenty-five EDA vendors composed the founding group of companies for HIP.

You can hear more about HIP when you visit DAC in Anaheim. You will see HIP members displaying the “integrated with HSPICE” stamp on their presentations.

With silicon-accuracy being such a critical issue, I would like to highlight two of the HIP members that will be showing solutions for more accurately modeling silicon variability. This goes straight to the issue I have discussed recently about how silly it is to focus on matching one SPICE simulation data point, rather than looking at the true distribution of circuit performance (Simulation accuracy… it’s the silicon, ******!).

Solido Design Automation will be presenting a technical seminar at DAC titled “Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design“. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented. You can find out more about the Solido solution for performing statistical variation analysis by clicking on the link to register for their seminar.

MunEDA will also be presenting their HIP solution at DAC in an “Automatic Flow for Library Cell Optimization with Synopsys HSPICEÂź & MunEDA WiCkeDℱ“. The MunEDA solution enables users to take into account inter- and intra-die variation and the effects on parametric performance such as leakage and timing. As an added incentive there will be a Bavarian Beer event at the MunEDA booth on Wednesday afternoon.

So… it’s too bad there is nothing new going on in analog EDA, huh?

Don’t forget to register for the Synopsys AMS breakfast at the Marriott on Tuesday morning. Our topic is AMS Verification and Moore’s Law
 solutions for 45nm and beyond.

I hope to see you in Anaheim.

-Mike
SPICE HSPICE Fast-SPICE Design Automation Conference Synopsys