Archive for the 'Mixed Signal/Cosimulation' Category

If you need a very thorough refresh and/or advanced class on Analog Mixed Signal simulation, I have some good news for you ! I have been working with a team of experts to create a class on AMS verification for UCSC. I will be teaching this class this summer every Tuesday night from June 19^th to July 27^th, as part of UCSC evening classes offering. So in addition to enjoy my remarkable teaching skills , you will hear the latest on Analog Mixed signal verification, from basic simulation topics (design types, analog and digital solvers, communication interface) to more advanced features (Behavioral modeling, real number modeling, AMS verification flow). We designed this class to present some basic concepts first, and to naturally evolve to more complex elements necessary for today AMS and SOC designs. We will be using Synopsys CustomSim-VCS, Custom Designer and CustomExplorer Ultra tools to showcase Synopsys advanced mixed signal solution. Synopsys CustomSim-VCS mixed signal flow has been used successfully by many large corporations and has been chosen for performance, robustness and ease of use.

You can get more information and register using the link below:

http://course.ucsc-extension.edu/modules/shop/index.html?action=section&OfferingID=5270152&SectionID=5271225

Our development team includes experts in both Analog, Mixed Signal and Digital domains: Dave Cronauer, Farzin Rasteh, Fabian Delguste, Aravinda Pondury and Shankar Hemmady worked closely with me to provide an extensive description of Synopsys advanced mixed signal verification flow.

Hope to see you this summer

Shankar Hemmady

Shankar Hemmady is responsible for knowledge sharing and methodology in the Verification Group at Synopsys.  Over the past four years, Shankar took a lead in power-aware verification, and verification planning and management solutions.

Dave Cronauer

Dave worked at Boeing Aerospace creating Spice and MAST models.  He joined Analogy in 1990 doing training, support, and technical marketing for Saber. He is now working on Mixed-Signal Verification tools including CustomSim-VCS, concentrating on Verilog-AMS modeling and support.

Fabian Delguste

Fabian is a Principal CAE at Synopsys / Verification Group. He’s in charge of supporting key accounts in Europe, working on Next Generation VIPs, verification methodologies and has been involved with setting up new methodologies for mixed-AMS verification

Aravinda Ponduri

Aravinda is a Staff CAE at Synopsys, Verification Group. He has been providing the technical support to some of the key customers in North America, and working on the new methodologies for both Digital and mixed-signal verification.

Farzin Rasteh is a Staff CAE at Synopsys, in the Analog Mixed Signal Group. He has been providing  technical support to some of the key customers in North America, and working on the new methodologies for Synopsys mixed-signal verification flow.

Happy Thursday !

Since I had a post on how to improve performance using HSPICE, I am now due for a similar post for CustomSim. CustomSim being our fast spice simulator, different techniques and options can be invoked to speed up simulation and improve performance. With the collaboration of our famous corporate application engineer Tom Hsieh, we are releasing today our secrete recipes

Tom has over 9 years of experience in FastSPICE simulation technologies and applications. He has spent the last 5 years working closely with R&D, sales and marketing to mature and lead deployment of CustomSim. He is a respected expert on FastSPICE simulation of custom digital, analog and memory circuits. Tom holds Bachelor and Master’s degrees in Electronic Engineering from UCLA and Santa Clara University, respectively.

10 tips to improve performance using CustomSim :

#1 – use ‘set_synchronization_level’ cmd for memory circuits:

set_synchronization_level  1|2|3|4|5|6 | 7  (recommend to start with ‘3’)

#2 – invoke multi-threading option: -mt <number> or with the following cmd:

set_multi_core -cpu Ncpu                                                       (With CustomSim 2012.06 release)

#3 – use the new multi-rate engine

set_multi_rate_option –mode 2                                         (With CustomSim 2012.06 release)

#4 – for post-layout  netlists contained large number of coupling caps, use:

set_ccap_option –ccap_to_scap 1 –ccap_to_gcap 1e-18

#5-  re-define the usage of wildcard, especially on post-layout Netlist, use cmd

set_wildcard_rule -match* one                                         (limit the hierarchies to match)

#6- limit the output waveform file size with the following cmd:

set_probe_window [ -window ] tstart [ tstop {tstart tstop} [tstart] ]

#7- reduce simulation time by process only the measurement statement without generate the waveform file with the following cmd:

set_probe_option -netlist_probe_control 2

#8- reduce simulation time by skip simulating the instance that is completely inactive with the following cmd:

skip_circuit_block [-inst inst_name {inst_name}] [-subckt subckt_name {subckt_name} ]

#9- re-use simulation measurement data set directly and post-process data without re-running the same netlist by using the cmd :

xa <Netlist.sp> -c cmd –o output_file

include the following cmd

meas_post –waveform waveform_file

#10- reduce simulation time by stopping your simulation as soon as the last measurement is completed by specifying the following option:

.option autostop

Enjoy !

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week…Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up…your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!