Posted by Hélène Thibiéroz on 26th January 2012
Happy Thursday !
I would like to inform you of our Synopsys HSPICE Special Interest Group event. In addition to having a culinary experience and meeting great people
, you will be able to network with peers and hear what industry leaders have to say about using HSPICE in some of today’s most challenging designs. The 2012 event is being held on January 31 at the Marriott Hotel in Santa Clara and will focus on Signal and Power Integrity.
The event format is the following:
DATE:Â Â January 31, 2012
TIME:Â Â 6:00 p.m.- 8:30 p.m.
LOCATION:Â Â Â Â Santa Clara Marriott Hotel
2700 Mission College Blvd.
Santa Clara, CA 95054
map & info.
HSPICE SIG EVENT AGENDA
6:00 – 7:00 p.m.        Registration and Cocktail Hour
7:15 – 8:15 p.m.        Dinner and Technical Presentations:
Altera: “28nm MOSFET Aging Modeling and Simulation Using HSPICE MOSRA”
Cavium: “HSPICE Signal Integrity Portfolio for High-Speed SERDES Channel Design”
Micron:”Simulating IBIS 5.0 Power-aware Models using HSPICE”
8:15 – 8:30 p.m.        Q&A and Prize Draw
This event is a great opportunity for users to exchange challenges, solutions and best practices as well as to network with peers.
If you are interested, I have included our registration page below:
http://app.connect.synopsys.com/e/es.aspx?s=700&e=29779&elq=2e0672756e024505b1dfd4f2122c3374
I will post next an interview I conducted with Amir Motamedi, one of our speakers for last year event, where he shares his insights about HSPICE SIG event and Signal Integrity.
Hope to see you there !
Posted in AMS Circuits, AMS EDA tools, Device Modeling, Signal Integrity, SPICE | No Comments »
Posted by Hélène Thibiéroz on 18th January 2012
Hello!
Do you ever
- wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
- wish you had insight into the latest advances in Synopsys solutions?
- have the urge to send comments to Synopsys team, via your smart phone?
The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.
Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.
For example, you will be able to find:
- List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up…your PLL design :^), I know you are all disappointed..)
- Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
- Technical blogs, where we would go deeper on specific Custom design and AMS subjects
- Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
- Webinars, Videos showcasing advanced features and/or flows
We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!
Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification | 3 Comments »