Archive for the 'Behavioral Modeling' Category

While at SNUG, I attended our AMS technical track session. One of the presentations described an innovative flow using UVM with Verilog-AMS. Synopsys CustomSim-VCS was successfully used on AMS designs to demonstrate the performance advantages of this methodology. The title was:

“Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure” by Warren Anderson and Ravi Ram from AMD, and Vijay Akkaraju, from Synopsys.

To give you a little more insight (don’t thank me ), this paper describes specific application of RTL verification methodology for AMS designs. Given the increasing complexity of mixed-signal circuits, a larger and larger number of stimulus need to be ran  to ensure functional correctness.  Because of lengthy run times of SPICE-based simulations and limitations of Verilog only models, more sophisticated approaches are needed.  AMD presented their approach, where low-level analog blocks were modeled using Verilog-AMS, and instantiated in a System Verilog top-level testbench for mixed-signal simulations. This flow was successfully implemented using Synopsys CustomSim-VCS.

Because I am a really nice person , I have included the presentation at the end of this post.

In this interview, Warren and Vijay share their insights about this approach and their overall experience at SNUG.

Warren Anderson

Warren Anderson is currently a Fellow at AMD’s Boston Design Center, where he works on high-speed I/O and electrostatic discharge (ESD) protection design.  Warren leads a team designing I/O and ESD circuits and developing solutions for high-speed off-chip signaling on AMD’s microprocessors.  Prior to joining AMD, he worked for Intel, Hewlett Packard and Digital Equipment Corporation. Warren’s areas of expertise include I/O circuit design, I/O jitter modeling and performance prediction, ESD protection, and signal integrity.  His publications include numerous papers on ESD protection design as well as contributions to three books. Warren currently holds 11 patents on ESD protection devices, circuits, and I/O design techniques.

Vijay is an Staff Application Consultant for Synopsys’s Simulation products, supporting key strategic accounts in Silicon Valley. He has been in the semi-conductor industry for 13 years including multiple roles in Design Engineering and has been part of 17 Silicon tape-outs. Before his current role he had stints in Analog Devices, AMCC and a start up.

Q- Warren, what was your overall experience at SNUG as a speaker? Which feedback did you receive after your presentation?

A- It was a very good experience.  I particularly enjoyed the Q&A discussion after the talk.  We received many thoughtful questions, showing that the audience was highly engaged during the talk (and it’s always nice for a speaker to know that the audience stayed awake!).  The amount of time allotted for the talk and questions was just right, making for a comfortable setting and pace.  The publication submission process was well organized and easy to follow.

Q- Could you please describe your job responsibilities within AMD ? What types of circuits do you simulate and which specific  Synopsys tools/simulator do you use ?

A- I manage a design team working on custom circuits for memory I/O.  My team is responsible for the transistor-level design of the circuits discussed in the paper: drivers, receivers, amplifiers, comparators, biasing, clocking, etc.  Most of our work involves creating and tuning the transistor-level design through HSPICE.  For the Verilog-AMS modeling, we run VCS+CustomSim/XA.

Q- Can you give us some background on this paper and using Verilog-AMS in conjunction with UVM? What were you trying to achieve?

A- High-speed I/O designs use a large amount of digital logic to control analog circuits.  The increasing mixed-signal nature means more digital-analog interactions, where sequences have to be performed in the right order, control bits need to be set properly, and missing a flop on an analog control wire could completely break the design.  In fact, in our prior project, we had a couple of near misses where we caught a few such bugs late in the project by manual inspection or transistor-level co-simulation with XA.  I didn’t want to repeat that scenario.

Verilog-AMS models run faster and follow a top-down design approach, enabling earlier verification of the mixed-signal interactions.  UVM increases our coverage of mixed-signal interactions by allowing us to randomize variables, such as offsets, device-related variations, and delays, in the Verilog-AMS models.

Q-   What are the main advantages (besides performance) in using this flow? Which challenges did you encounter during implementation?

A- As I mentioned, transistor-level co-simulation with VCS+XA has to wait for the transistor design to complete before it can be run.  Verilog-AMS models enable mixed-signal verification earlier in the design process, before the transistor-level design is finished or sometimes before it even starts, catching bugs earlier when they are easier to fix.  I think of it as RTL for analog designs.

In our implementation, automatic converter insertion caused some challenges.  It took a bit for us to become educated on the converter insertion algorithm, but it made sense in the end.  In order to configure the simulation to propagate analog signals through the top-level I/O block the way we wanted, we had to edit a few models once we saw where the converters were placed.  We did find a few bugs in the simulator, but those have been fixed.  Synopsys was responsive and committed to help us meet our design completion targets.

Q- What do you see moving forward in advanced Mixed-Signal/SoC verification?

A- We want to unleash more of the power behind the mixed-signal verification models and tools.  We will add more variables to our Verilog-AMS models and tie these into UVM constraints and randomization so deeper aspects of mixed-signal interaction can be covered.  In addition, I expect to propagate the AMS methodology to other I/O interfaces within AMD.

Q- Vijay, from a Synopsys point of view, we have a very robust and highly competitive mixed –signal solution using our leading edge fast-spice solver CustomSim in conjunction with VCS. Which design/customers would benefit the most from using this flow?

Vijay Akkaraju

A- I feel most AMS designs where Mixed-signal simulations are more than just “sign-off” can benefit from this methodology. The environments  likely to get the most are the ones with a mature UVM flow with large number of constrained random testcases. Also, designs where some rtl (digital) code can only be reached in a mixed-signal context for purposes of coverage (both functional and code) can immensely benefit from adapting this. I say that since for them, waiting for availability of a finished spice netlist comes in the way of speedy coverage closure. Also, designs with a complex Analog-Digital interface where constraint randomization of stimulus can expose bugs not likely to be exposed using directed testcases only.

You can find the presentation and paper clicking on the link below. Enjoy and see you soon!

SNUG presentation:

SNUG_AMS_v6_final_presentation

SNUG Paper:

SNUG_2012_AMS13

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week…Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Hello!

Do you ever

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