Archive for the 'analog' Category

yes, an other field trip report   You may remember we held our HSPICE Special Interest Group event during DesignCon week. This event gives you an opportunity to talk with Synopsys HSPICE R&D personnel and hear what our customers have to say about using HSPICE in today’s most challenging designs.

The agenda was:

It was a great success:  we had a 27% increase in customer attendance vs. 2011 as well as 11 HIP partners exhibiting. Because I received extremely positive feedback from our audience on the format of this event and the topics we discussed, I wanted to give you more insights from an attendee/speaker angle. I therefore asked our Synopsoid Scott Wedge to share his experience as a speaker.

A little more about Scott.. He spent ten years as an analog/RF/AMS design engineer with Hughes Aircraft Company working on a variety of military and satellite communications systems. After receiving his Ph.D. from Caltech, he joined the Touchstone R&D team at EEsof (now Agilent-EEsof), where he helped pioneer many new high-frequency circuit simulation and analysis capabilities.  Scott was director of IC design tool research at Tanner EDA before joining the HSPICE R&D team at Synopsys where he has worked for the past 10 years developing new simulation approaches for noise, jitter, and signal integrity.

Q- Scott, you presented HSPICE/HPP latest features. Based on our post-mortem analysis and my discussions with multiple customers, your presentation was really well received by the audience. Could you please tell us more about the content? Which features do you consider being a differentiator for HSPICE/HPP?

A-     Thanks, Helene! Since the HSPICE SIG event coincided with DesignCon, we took the opportunity to emphasize the many capabilities in HSPICE for handling critical aspects of signal integrity analysis. There are some other good tools out there for SI, especially for linear link modeling, but HSPICE has the advantage of being the only SI simulator that is also the gold standard for chip simulation. The strengths we have for nonlinear simulation, including our multi-core HPP engine, combined with high-performance modeling for link components, set us apart. In my content I showed how we are combining these strengths to deliver our multi-edge StatEye analysis; an approach that uses the speed of statistical eye diagram methods, yet captures critical nonlinear effects, for an outstanding combination of speed and accuracy.

Q- What were the highlights of this year’s event? As an HSPICE R&D member and as an attendee, did you benefit from this event? What was your major take-away (besides having a three-course meal )?

Scott Wedge

A- What is always a highlight for me at the HSPICE SIG events is seeing and talking with all the HIP partners – the HSPICE Integrator Program members.  I get a big kick out of seeing all the ways HSPICE is combined with other excellent tools to solve a variety of problems. The science buff in me loves seeing the latest electromagnetic analysis tools, and how they are getting faster and more accurate for solving a variety of geometries – and extracting models – that are very important for circuit and system design. The EE in me loves seeing the Design Environment tools – those that run HSPICE under the hood – how they make the designer more productive, and how they handle all the data and test benches that are crucial in modern design. The mathematician and computer buff in me loves seeing the behavioral modeling solutions used with HSPICE, such as IBIS and IBIS-AMI, and how they streamline the design and verification flows. The highlight was talking with customers that use HSPICE with the HIP tools, and all the amazing engineering solutions they are coming up with.

Q- How do you think this event could be improved?

A- I had such a good time, and the event was so well put together, with such excellent food and drink, it would be hard to improve upon. One thing: it was impossible to talk with all the people I had hoped to, and it was difficult connecting with them again at DesignCon with everyone’s busy schedules. In hindsight it would have been nice to have also had a Synopsys HSPICE exhibit at DesignCon, where HSPICE users and developers could connect and share additional information informally without the time constraints necessary for the SIG event.

Q- Based on the audience, which hot topics would you select for our next event?

A- Based on questions I had afterwards, there was a lot of interest in our new transient noise analysis solutions, and how they apply to challenges in both analog design and signal integrity. With ever higher speeds, and smaller geometry technology trends, design engineers must continually contend with shrinking signal-to-noise ratios. Transient noise simulations allow them to realistically predict signal and noise combinations and interactions. This is definitely a hot topic of interest for the future!

Input well taken, I have just signed Scott for an other post on HPP transient noise…..

That’s it for this post. If you want more information (and more visual content ) , you can use the following link to our 2012 HSPICE SIG Videolog page :

www.hspice-sig.com

A bientot !

Happy Friday,

“Chose promise, chose due” – In other words, I owed you a full report on our S-parameters tutorial

As mentioned in one of my previous posts, we received a lot of interest for the AMS tutorial we created for DesignCon 2012. We managed to hold 120 persons in average for three hours talking about S-parameter modeling for SI without even locking doors . Our three Speakers (Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys) explored this topic from an intermediate to a more advanced level. Because each speaker is an expert in a different area, we were able to cover this topic from different angles and with a lot of depth. In this interview, Amir, Brad and Donald talk about their presentations and share their overall impressions (I have also listed each presentation below). We will further explore and refine this topic at next year tutorial so you’d better be there  !

Q>  I will be including each of your presentations at the end of this post. Would each of you give a few lines summary of your presentation?

Brad Brim

[Brad]  My presentation can be described as: An introduction to S-parameters with a focus on issues relevant to designers of chips/packages/boards and systems with high-speed signals. A few basic definitions are covered with the major focus being on practical issues SI engineers tend to learn and re-learn all too often.

[Amir] My presentation is titled “SPICE Simulation with Frequency Domain Models” and covers the following topics: What to learn about the channel just by observing its S-parameter and impulse response and group delay;  Correlation/Calibration the models with measurements to increase accuracy; S-parameter data interpolation/extrapolation; What to do about missing DC data, how to “interpolate”, simulate or estimate it; Requirements for transient simulation; passivity, causality; Convolution and maximizing simulator performance; Best practices at getting good S-parameters from EM solvers; Efficient EM solver data formats for SPICE simulation; Handling reference planes for S-parameter Ports; Defining high-speed link simulations in SPICE; Special cases: Power delivery systems and needed modifications to S-parameters; Nonlinear I/O modeling with IBIS and encrypted HSPICE buffers; and Adding DJ and RJ effects with SPICE Thermal noise.

[Donald] My presentation explains how to combine S-Parameters with active models to simulate high-speed serial links and assess performance using eye diagrams.  Now that S-Parameter and AMI models are flowing more freely throughout the industry it has become possible to examine and validate link behavior, pre-hardware.  I offer a full-day Seminar on this topic that shows how to use these techniques to validate a design and its compliance with the major serial standards, even though the standards still have a post-hardware bias.  There’s huge value in figuring out how to do this before you fabricate or assemble anything.

Q> It appears that this topic was really well received among DesignCon community. Which feedback did you receive from the attendees?

Amir Motamedi

[Brad]  I received positive feedback from attendees concerning the breadth of what was covered. Not from a technical or theoretical perspective but from basic concepts to detailed application for high-speed serial link systems. My choice not to focus on regurgitating basic concepts and definitions that may be found elsewhere on the web, in college texts or in commercially available training classes seemed to resonate with attendees; especially the lessons I covered for which I work with EDA tool users on a daily basis to learn and re-learn. Amir’s intuitive description of the relevance of S-parameter behaviors was also noted as a big positive by attendees. They liked the practical knowledge Amir was able to share based on his experience applying S-parameters in his designs. Donald’s presentation addressed a hot topic for DesignCon for the past few years – high speed serial links. Since a large portion of the attendees are focused on board design, his system-centric focus of bits-to-bits serial link communications through each chip/package/board was highly relevant. For all three presentations I received feedback they were received well in the tutorial nature intended; not as too detailed or too factual, but rather fun and informative.

[Donald] One attendee claimed it was the most useful session he attended.  I think the combination of the talks – all the way from matrices to Bit Error Rates – scratched where people itched.

Q> I noticed DesignCon had an increasing content of AMS/RF related papers and subjects. Have you noticed a change in DesignCon traditional venue?

[Brad]  I have observed the number of RF-related topics peak and valley over the years at DesignCon. Each year the TPC (technical program committee) does a good job of maintaining the traditional focus of DesignCon with its paper selections. In fact, notice the title of the RF-centric track is “RF/Microwave Techniques for Signal Integrity”. This is true also for the “Test and Measurement Methodology” track. Other conferences such as IEEE MTT Symposium are intended for more pure RF/microwave topics.  RF/microwave measurement conferences also exist; as I am suspect Analog IC conferences are plentiful. I believe the “mixed-signal” portion of AMS and analog-specific designs required to support high-speed signaling is very relevant to DesignCon attendees. As bandwidths increase for high-speed signals, we can expect to see a continued increase in the analog content present in topics of interest to DesignCon. For example, the coupling of analog to digital signal and power noise seems a relevant topic for DesignCon, though the design of a purely analog circuit not relevant to high speed signaling may not be.

[Donald] Higher frequencies have forced SI Engineers to increasingly borrow from RF tools and techniques.  In addition, the abundance of silicon gates has pushed things we used to solve on the PCB inside silicon causing convergence of SI, AMS, and DSP design techniques.  So yes, things are changing – they always do.

Q> which subjects would you add for our next year tutorial? Are there emerging trends/hot topics we should cover?

Donald Telian

[Brad]  We should ask ourselves what questions we ask ourselves or what questions our colleagues and customers ask us repeatedly. As authors or “faculty” as DesignCon called us this year, we sometimes forget the presentation is for the benefit of the attendee (not to hear ourselves talk). This is especially true for a tutorial forum. Even if we personally believe the issue to be trivial or covered well in other readily available media we should consider the frequency with which the issue comes up as an indicator of need for further discussion. A tutorial forum is ideal for this type of discussion, since the authors are likely accustomed to addressing the topic daily and have the skill and readily available materials to share with DesignCon attendees.
I was surprised at the high percentage of package and board designers who attended this AMS-sponsored tutorial. Seems the topic was not as well understood even by these attendees, as I had suspected it would be unfamiliar for AMS IC-centric designers.

[Donald] Emerging equalization techniques and associated IC/PCB design capabilities are the next big thing that will push interfaces faster than 10 Gbps into the mainstream.  Engineers are calling for Tutorials that help them bring these things together at the system level.

**********************

Brad’s slides:

BradBrim_TutorialSlides_final

Amir’s slides:

Amir_slides

Donald’s slides:

Donald_tutorial

Good morning ! well, since this is a technical blog, I thought I owed you some tools-related posts I am compiling below 10 tips to make your HSPICE simulation even more efficient

If you want to look into those options in more details, we conducted a webinar a few weeks ago hosted by Szekit Chan, that discussed those topics in more details. I have listed the link at the end of this post.

And as usual, feedback/comments are more than welcome !

#1 – use HSPICE runlvl to replace old options convergence parameters:

.option runlvl=1|2|3|4|5|6

#2 – invoke multi-threading option with HPP: -mt <number> -hpp

#3 – use distributed processing: -dp <number>

#4 – for post-layout  netlists, use RC reductions techniques: .option sim_la

#5-  avoid the usage of wildcard within your .probe statement, especially on post-layout netlist

Instead of .probe tran v(*) I(*) use .probe tran v(xi.*) i(xi.r*)

#6- declare port current directly

Instead of .probe tran isub(*) use .probe tran isub(xinv.vdd) isub(xinv.v*)

#7- if using .ALTER statement, reduce netlist processing and checking time with the following options: .option altcc altchk

#8- reduce simulation time by bypassing element checking and suppressing topology checking with the following options:

.option notop noelchk

#9- re-use simulation measurement data set directly and post-process data without re-running the same netlist by using the command line option:

>> hspice –i ***.tro –meas <meas_file>

#10- reduce simulation time by stopping your simulation as soon as the last measurement is completed by specifying the following option:

.option autostop

The link to the webinar is:

https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=381394&sessionid=1&key=E48E59582DA6321FCDE78BBF5BEFD169&cmp=WEBR-circ100094-HPW

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week
Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up
your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

Rather than trying to completely automate away the layout phase (as some have tried) we chose a different path. In analog designs the layout designer must have complete manual control of the layout so how do you automate that?

We chose a new path
 we decided not to enforce our automation on designers but rather give them a toolbox of powerful new features that simplify their jobs and help get it done quicker. This is the first in a series of blog entries that will feature some of the ideas our team came up with after talking to many, many layout engineers.

Today’s topic is zooming and it’s evil twin counting grids. Layout designers often spend a great deal of time zooming into a region to start a wire, then zooming out to route it followed by a zoom back in to finish aligning the end of the wire. That’s a lot of clicks and often the designer has to go back across the wire counting grids and moving segments to make sure that he hasn’t violated the rules.

What if you could wire at high-altitude and eliminate the zooms? What if you could click near a terminal or a gate and have the new wire adopt the width, snapped to and pre-aligned with the terminal and just start wiring immediately?

We call it “SmartConnect” and it does just that. Another cool feature is SmartConnect’s “Alignment Markers” that make it obvious when you are aligned with the left, center or middle of another object.

Sounds simple but these features enable very rapid wiring without forcing the layout engineer to accept somebody else’s idea of what makes a good layout.

‘Til next time, keep wiring away and stay tuned. We’ve got a lot more stuff in the pipe for our next release that I think you will really like


Fred

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

One of the Custom Designer developers  said, “That capability looks a lot like this new feature that will be released in the up coming version of Custom Designer.” We all got VERY excited when he then demonstrated the beta version of this new feature to the assembled group. It was really cool and very useful. We then asked for a minor extension of the feature and he had that up and running in a trial tcl script within the hour. Sweet. We can hardly wait for the next release.

Later that night at dinner, one of the corporate apps engineers came up to me and said, “You don’t remember do you? I visited you 7 months ago with a list of planned features for CD and you looked it over and said –  “these are all OK but what would be really nice is if you could…” and then you described this new feature. We thought it was a great idea and put it at the top of the list.” I then told him that it was no wonder I had liked the new feature so much but I also told him I was terribly disappointed. When he asked why I was upset I said “Well if I had remembered I had suggested it I could have said ‘7 months – what took you so long!’”.

So when you see the next version of Custom Designer, there is at least one really cool feature that will blow you away (I haven’t seen the other cool one yet – just heard about it). You will know which feature it is because it is so useful. You will also know how we feel to work with an analog design tool that is growing and improving DAILY with developers who listen to us – how sweet it is!

Bob Lefferts

Hi Everybody!

First my apologies for our silence over the past couple of weeks. We’ve had our head down in preparation for and the delivery of the 47th Design Automation Conference in Anaheim last week (47? Really?)

Synopsys had an outstanding DAC this year and had many announcements to go with it. In addition to our main booth, we showed Custom Designer, HSPICE and CustomSim at a number of different venues throughout the show and that kept us, ah, rather busy.

Our demo suites were jammed and we hosted numerous customers, editors, analysts, breakfasts, lunches and dinners and the transcripts of many of those will be available soon. Stay tuned.

The show is over and now that we can breath, we’ll get back on track with some new posts about some great new technology we have coming up.

Fred

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast
 One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency
) can be set independently from the y-axis (be it voltage, current
) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end




; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat 
 ***
   *** loading waveform file t1.dat    
 ***
   *** loading waveform file t2.dat    
 ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list



Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

Happily, improvements in processor technology have provided new machines with multiple processing cores on the same chip. Although HSPICE has had the ability to use these cores for several years now that hasn’t stopped us from making improvements in our multi-core processing capabilities.

Synopsys recently released a new capability in HSPICE that improves the scalability of simulations on machines with four or more cores. This new high-performance multi-processing capability is seeing great scalability on multiple core machines:

These are average speedups on top of the over 5x speed improvements on single-core HSPICE that our team has already achieved over the past few years. Many of our simulation tests on four cores are reaching even higher performance while maintaining the golden accuracy you demand from HSPICE.

I’d like to go into more detail about how this great new technology works but given that it is patent-pending, I will save that discussion for another blog entry.

Kishore