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Analog Insights: Analog/Mixed-Signal Design and Verification Blog

Archive for the 'Analog and Custom Layout' Category

Welcome Again!

Posted by HélÚne Thibiéroz on 18th January 2012

Hello!

Do you ever

  • wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
  • wish you had insight into the latest advances in Synopsys solutions?
  • have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

  • List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up
your PLL design :^), I know you are all disappointed..)
  • Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
  • Technical blogs, where we would go deeper on specific Custom design and AMS subjects
  • Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
  • Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification | 3 Comments »

NanoTime Static Timing in Custom Designer

Posted by fred sendig on 23rd July 2010

NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

We are pretty excited about this new integration and held a webinar on the topic this week. If you missed, don’t worry, it is archived on our website and you can watch it here.

Fred

Posted in Analog and Custom Layout, Custom Designer, Nanometer CMOS | No Comments »

Focus on Layout Productivity – Part 1

Posted by fred sendig on 16th July 2010

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

Rather than trying to completely automate away the layout phase (as some have tried) we chose a different path. In analog designs the layout designer must have complete manual control of the layout so how do you automate that?

We chose a new path
 we decided not to enforce our automation on designers but rather give them a toolbox of powerful new features that simplify their jobs and help get it done quicker. This is the first in a series of blog entries that will feature some of the ideas our team came up with after talking to many, many layout engineers.

Today’s topic is zooming and it’s evil twin counting grids. Layout designers often spend a great deal of time zooming into a region to start a wire, then zooming out to route it followed by a zoom back in to finish aligning the end of the wire. That’s a lot of clicks and often the designer has to go back across the wire counting grids and moving segments to make sure that he hasn’t violated the rules.

What if you could wire at high-altitude and eliminate the zooms? What if you could click near a terminal or a gate and have the new wire adopt the width, snapped to and pre-aligned with the terminal and just start wiring immediately?

We call it “SmartConnect” and it does just that. Another cool feature is SmartConnect’s “Alignment Markers” that make it obvious when you are aligned with the left, center or middle of another object.

Sounds simple but these features enable very rapid wiring without forcing the layout engineer to accept somebody else’s idea of what makes a good layout.

‘Til next time, keep wiring away and stay tuned. We’ve got a lot more stuff in the pipe for our next release that I think you will really like


Fred

Posted in AMS EDA tools, analog, Analog and Custom Layout | No Comments »