Archive for the 'Fast-SPICE' Category

While at SNUG, I attended our AMS technical track session. One of the presentations described an innovative flow using UVM with Verilog-AMS. Synopsys CustomSim-VCS was successfully used on AMS designs to demonstrate the performance advantages of this methodology. The title was:

“Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure” by Warren Anderson and Ravi Ram from AMD, and Vijay Akkaraju, from Synopsys.

To give you a little more insight (don’t thank me ), this paper describes specific application of RTL verification methodology for AMS designs. Given the increasing complexity of mixed-signal circuits, a larger and larger number of stimulus need to be ran  to ensure functional correctness.  Because of lengthy run times of SPICE-based simulations and limitations of Verilog only models, more sophisticated approaches are needed.  AMD presented their approach, where low-level analog blocks were modeled using Verilog-AMS, and instantiated in a System Verilog top-level testbench for mixed-signal simulations. This flow was successfully implemented using Synopsys CustomSim-VCS.

Because I am a really nice person , I have included the presentation at the end of this post.

In this interview, Warren and Vijay share their insights about this approach and their overall experience at SNUG.

Warren Anderson

Warren Anderson is currently a Fellow at AMD’s Boston Design Center, where he works on high-speed I/O and electrostatic discharge (ESD) protection design.  Warren leads a team designing I/O and ESD circuits and developing solutions for high-speed off-chip signaling on AMD’s microprocessors.  Prior to joining AMD, he worked for Intel, Hewlett Packard and Digital Equipment Corporation. Warren’s areas of expertise include I/O circuit design, I/O jitter modeling and performance prediction, ESD protection, and signal integrity.  His publications include numerous papers on ESD protection design as well as contributions to three books. Warren currently holds 11 patents on ESD protection devices, circuits, and I/O design techniques.

Vijay is an Staff Application Consultant for Synopsys’s Simulation products, supporting key strategic accounts in Silicon Valley. He has been in the semi-conductor industry for 13 years including multiple roles in Design Engineering and has been part of 17 Silicon tape-outs. Before his current role he had stints in Analog Devices, AMCC and a start up.

Q- Warren, what was your overall experience at SNUG as a speaker? Which feedback did you receive after your presentation?

A- It was a very good experience.  I particularly enjoyed the Q&A discussion after the talk.  We received many thoughtful questions, showing that the audience was highly engaged during the talk (and it’s always nice for a speaker to know that the audience stayed awake!).  The amount of time allotted for the talk and questions was just right, making for a comfortable setting and pace.  The publication submission process was well organized and easy to follow.

Q- Could you please describe your job responsibilities within AMD ? What types of circuits do you simulate and which specific  Synopsys tools/simulator do you use ?

A- I manage a design team working on custom circuits for memory I/O.  My team is responsible for the transistor-level design of the circuits discussed in the paper: drivers, receivers, amplifiers, comparators, biasing, clocking, etc.  Most of our work involves creating and tuning the transistor-level design through HSPICE.  For the Verilog-AMS modeling, we run VCS+CustomSim/XA.

Q- Can you give us some background on this paper and using Verilog-AMS in conjunction with UVM? What were you trying to achieve?

A- High-speed I/O designs use a large amount of digital logic to control analog circuits.  The increasing mixed-signal nature means more digital-analog interactions, where sequences have to be performed in the right order, control bits need to be set properly, and missing a flop on an analog control wire could completely break the design.  In fact, in our prior project, we had a couple of near misses where we caught a few such bugs late in the project by manual inspection or transistor-level co-simulation with XA.  I didn’t want to repeat that scenario.

Verilog-AMS models run faster and follow a top-down design approach, enabling earlier verification of the mixed-signal interactions.  UVM increases our coverage of mixed-signal interactions by allowing us to randomize variables, such as offsets, device-related variations, and delays, in the Verilog-AMS models.

Q-   What are the main advantages (besides performance) in using this flow? Which challenges did you encounter during implementation?

A- As I mentioned, transistor-level co-simulation with VCS+XA has to wait for the transistor design to complete before it can be run.  Verilog-AMS models enable mixed-signal verification earlier in the design process, before the transistor-level design is finished or sometimes before it even starts, catching bugs earlier when they are easier to fix.  I think of it as RTL for analog designs.

In our implementation, automatic converter insertion caused some challenges.  It took a bit for us to become educated on the converter insertion algorithm, but it made sense in the end.  In order to configure the simulation to propagate analog signals through the top-level I/O block the way we wanted, we had to edit a few models once we saw where the converters were placed.  We did find a few bugs in the simulator, but those have been fixed.  Synopsys was responsive and committed to help us meet our design completion targets.

Q- What do you see moving forward in advanced Mixed-Signal/SoC verification?

A- We want to unleash more of the power behind the mixed-signal verification models and tools.  We will add more variables to our Verilog-AMS models and tie these into UVM constraints and randomization so deeper aspects of mixed-signal interaction can be covered.  In addition, I expect to propagate the AMS methodology to other I/O interfaces within AMD.

Q- Vijay, from a Synopsys point of view, we have a very robust and highly competitive mixed –signal solution using our leading edge fast-spice solver CustomSim in conjunction with VCS. Which design/customers would benefit the most from using this flow?

Vijay Akkaraju

A- I feel most AMS designs where Mixed-signal simulations are more than just “sign-off” can benefit from this methodology. The environments  likely to get the most are the ones with a mature UVM flow with large number of constrained random testcases. Also, designs where some rtl (digital) code can only be reached in a mixed-signal context for purposes of coverage (both functional and code) can immensely benefit from adapting this. I say that since for them, waiting for availability of a finished spice netlist comes in the way of speedy coverage closure. Also, designs with a complex Analog-Digital interface where constraint randomization of stimulus can expose bugs not likely to be exposed using directed testcases only.

You can find the presentation and paper clicking on the link below. Enjoy and see you soon!

SNUG presentation:

SNUG_AMS_v6_final_presentation

SNUG Paper:

SNUG_2012_AMS13

If you need a very thorough refresh and/or advanced class on Analog Mixed Signal simulation, I have some good news for you ! I have been working with a team of experts to create a class on AMS verification for UCSC. I will be teaching this class this summer every Tuesday night from June 19^th to July 27^th, as part of UCSC evening classes offering. So in addition to enjoy my remarkable teaching skills , you will hear the latest on Analog Mixed signal verification, from basic simulation topics (design types, analog and digital solvers, communication interface) to more advanced features (Behavioral modeling, real number modeling, AMS verification flow). We designed this class to present some basic concepts first, and to naturally evolve to more complex elements necessary for today AMS and SOC designs. We will be using Synopsys CustomSim-VCS, Custom Designer and CustomExplorer Ultra tools to showcase Synopsys advanced mixed signal solution. Synopsys CustomSim-VCS mixed signal flow has been used successfully by many large corporations and has been chosen for performance, robustness and ease of use.

You can get more information and register using the link below:

http://course.ucsc-extension.edu/modules/shop/index.html?action=section&OfferingID=5270152&SectionID=5271225

Our development team includes experts in both Analog, Mixed Signal and Digital domains: Dave Cronauer, Farzin Rasteh, Fabian Delguste, Aravinda Pondury and Shankar Hemmady worked closely with me to provide an extensive description of Synopsys advanced mixed signal verification flow.

Hope to see you this summer

Shankar Hemmady

Shankar Hemmady is responsible for knowledge sharing and methodology in the Verification Group at Synopsys.  Over the past four years, Shankar took a lead in power-aware verification, and verification planning and management solutions.

Dave Cronauer

Dave worked at Boeing Aerospace creating Spice and MAST models.  He joined Analogy in 1990 doing training, support, and technical marketing for Saber. He is now working on Mixed-Signal Verification tools including CustomSim-VCS, concentrating on Verilog-AMS modeling and support.

Fabian Delguste

Fabian is a Principal CAE at Synopsys / Verification Group. He’s in charge of supporting key accounts in Europe, working on Next Generation VIPs, verification methodologies and has been involved with setting up new methodologies for mixed-AMS verification

Aravinda Ponduri

Aravinda is a Staff CAE at Synopsys, Verification Group. He has been providing the technical support to some of the key customers in North America, and working on the new methodologies for both Digital and mixed-signal verification.

Farzin Rasteh is a Staff CAE at Synopsys, in the Analog Mixed Signal Group. He has been providing  technical support to some of the key customers in North America, and working on the new methodologies for Synopsys mixed-signal verification flow.

Happy Thursday !

Since I had a post on how to improve performance using HSPICE, I am now due for a similar post for CustomSim. CustomSim being our fast spice simulator, different techniques and options can be invoked to speed up simulation and improve performance. With the collaboration of our famous corporate application engineer Tom Hsieh, we are releasing today our secrete recipes

Tom has over 9 years of experience in FastSPICE simulation technologies and applications. He has spent the last 5 years working closely with R&D, sales and marketing to mature and lead deployment of CustomSim. He is a respected expert on FastSPICE simulation of custom digital, analog and memory circuits. Tom holds Bachelor and Master’s degrees in Electronic Engineering from UCLA and Santa Clara University, respectively.

10 tips to improve performance using CustomSim :

#1 – use ‘set_synchronization_level’ cmd for memory circuits:

set_synchronization_level  1|2|3|4|5|6 | 7  (recommend to start with ‘3’)

#2 – invoke multi-threading option: -mt <number> or with the following cmd:

set_multi_core -cpu Ncpu                                                       (With CustomSim 2012.06 release)

#3 – use the new multi-rate engine

set_multi_rate_option –mode 2                                         (With CustomSim 2012.06 release)

#4 – for post-layout  netlists contained large number of coupling caps, use:

set_ccap_option –ccap_to_scap 1 –ccap_to_gcap 1e-18

#5-  re-define the usage of wildcard, especially on post-layout Netlist, use cmd

set_wildcard_rule -match* one                                         (limit the hierarchies to match)

#6- limit the output waveform file size with the following cmd:

set_probe_window [ -window ] tstart [ tstop {tstart tstop} [tstart] ]

#7- reduce simulation time by process only the measurement statement without generate the waveform file with the following cmd:

set_probe_option -netlist_probe_control 2

#8- reduce simulation time by skip simulating the instance that is completely inactive with the following cmd:

skip_circuit_block [-inst inst_name {inst_name}] [-subckt subckt_name {subckt_name} ]

#9- re-use simulation measurement data set directly and post-process data without re-running the same netlist by using the cmd :

xa <Netlist.sp> -c cmd –o output_file

include the following cmd

meas_post –waveform waveform_file

#10- reduce simulation time by stopping your simulation as soon as the last measurement is completed by specifying the following option:

.option autostop

Enjoy !

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week…Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up…your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast… One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency…) can be set independently from the y-axis (be it voltage, current…) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end

…

; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat … ***
   *** loading waveform file t1.dat    … ***
   *** loading waveform file t2.dat    … ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list
…

Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

We pondered how we could do this work within the tight time schedule allotted by the customer. They needed a working design in three months and we didn’t have time to start from scratch.

Enter Custom Designer. In use by hundreds of our Solutions Group analog IP designers, its open framework, features, powerful scripting capabilities and overall flexibility were to be the key to resolving this problem.

For those of you who missed my SNUG presentation, we’ve written it up and posted it on the Synopsys website:

Reverse Process Migration from 65nm to 130nm in Under Three Months

Enjoy,

Bob

Hello, and welcome to our new blog on the state of custom and AMS IC design at Synopsys. We set out some years ago to address the need for alternatives in custom and analog design software, and with the launch of Galaxy Custom Designer in 2008 we are seeing that vision realized.

Synopsys has amassed a powerful presence in the circuit simulation market. Our flagship products, HSPICE and CustomSim, form the backbone of transistor-level design and verification worldwide. Behind these products is a very talented group of individuals who are hard at work on solving some of the thorniest problems facing the EDA market.

Our own digital and analog IP design groups use these products to provide cutting-edge solutions for tough problems. Our proven AIP is used in designs worldwide and before it gets to you, it’s been through the wringer by a set of designers who have no mercy for bad chips.

I’d like to tell you what we have in store for you on this blog.

We have asked two of our most respected thought leaders in their domains to post entries on this blog:
Kishore Singhal: circuit simulation expertise
Bob Lefferts: a user’s perspective designing with Synopsys’ custom design flow
and, of course, I will continue to post my thoughts on custom design and implementation

In the coming weeks, each blogger will post entries on topics in his domains of expertise. You can expect everything from the technical background of the tools, tips and tricks to make you more productive, and ways to extend and integrate your design flows. And every now and then members of our technical teams will also share their experiences with you.

So thanks for reading this reinvigorated Analog Insights blog today. I can guarantee you—there’s a lot more to come!

Unless you’ve been living in a cave for the past year, you’ve probably heard about Twitter. It’s all the rage in the social media world, more than doubling the number of users month-to-month lately.  Traffic is what it’s all about in the internet business, so there have been plenty of rumors that Apple will buy Twitter, or Google will buy Twitter… even though they haven’t figured out how to make money yet.

You may be thinking, “what do I need Twitter for”? Yes, there is a lot of useless drivel like what I’m having for lunch, but if you look at is as a good way to stay informed in real time – it can actually be very useful.  The nice thing is that you get to choose who you want to follow.

I have found myself micro-blogging on Twitter much more, because I just don’t have the time to write full blogs as frequently. There is a growing group of EDA folks on Twitter that I follow, and I recommend you look into following them as well.  Information on my Twitter feed is now in the left sidebar here at  Analog Insights. You can follow me on Twitter through an RSS feed, or by creating your own Twitter account:

My Twitter RSS feed: http://twitter.com/statuses/user_timeline/20415938.rss

My Twitter ID: http://twitter.com/MikeDemler

FYI, now that I am not employed in EDA, my primary blogging home is The World is Analog.  If you want to keep abreast of my latest posts, wherever they are, I always put a “tweet” out so you can be immediately notified.

-Mike

If you are reading this, you may have had thoughts on blogging yourself, or perhaps you already are a blogger. One of the most valuable lessons that I have learned from writing a blog is how it can be be used for creating and publicizing my personal “brand”. Personal branding is a way to demonstrate the unique expertise and value that you can provide, to potential employers as well as to colleagues in your profession.

I was first introduced to the topic of personal branding in an article for which I was interviewed by EDN magazine; Life after layoffs: How to move forward after a job loss. Since then I have been asked to share my experience as a blogger with others, most recently at a career networking group hosted by Right Management here in Silicon Valley. My “Top 10 ways to attract subscribers to your blog” may be helpful to you in developing your own personal brand through blogging. You can view the slide show of my presentation here: Developing Your Personal Brand Through Blogging.

-Mike