Archive for the 'EDA' Category

yes, an other field trip report   You may remember we held our HSPICE Special Interest Group event during DesignCon week. This event gives you an opportunity to talk with Synopsys HSPICE R&D personnel and hear what our customers have to say about using HSPICE in today’s most challenging designs.

The agenda was:

It was a great success:  we had a 27% increase in customer attendance vs. 2011 as well as 11 HIP partners exhibiting. Because I received extremely positive feedback from our audience on the format of this event and the topics we discussed, I wanted to give you more insights from an attendee/speaker angle. I therefore asked our Synopsoid Scott Wedge to share his experience as a speaker.

A little more about Scott.. He spent ten years as an analog/RF/AMS design engineer with Hughes Aircraft Company working on a variety of military and satellite communications systems. After receiving his Ph.D. from Caltech, he joined the Touchstone R&D team at EEsof (now Agilent-EEsof), where he helped pioneer many new high-frequency circuit simulation and analysis capabilities.  Scott was director of IC design tool research at Tanner EDA before joining the HSPICE R&D team at Synopsys where he has worked for the past 10 years developing new simulation approaches for noise, jitter, and signal integrity.

Q- Scott, you presented HSPICE/HPP latest features. Based on our post-mortem analysis and my discussions with multiple customers, your presentation was really well received by the audience. Could you please tell us more about the content? Which features do you consider being a differentiator for HSPICE/HPP?

A-     Thanks, Helene! Since the HSPICE SIG event coincided with DesignCon, we took the opportunity to emphasize the many capabilities in HSPICE for handling critical aspects of signal integrity analysis. There are some other good tools out there for SI, especially for linear link modeling, but HSPICE has the advantage of being the only SI simulator that is also the gold standard for chip simulation. The strengths we have for nonlinear simulation, including our multi-core HPP engine, combined with high-performance modeling for link components, set us apart. In my content I showed how we are combining these strengths to deliver our multi-edge StatEye analysis; an approach that uses the speed of statistical eye diagram methods, yet captures critical nonlinear effects, for an outstanding combination of speed and accuracy.

Q- What were the highlights of this year’s event? As an HSPICE R&D member and as an attendee, did you benefit from this event? What was your major take-away (besides having a three-course meal )?

Scott Wedge

A- What is always a highlight for me at the HSPICE SIG events is seeing and talking with all the HIP partners – the HSPICE Integrator Program members.  I get a big kick out of seeing all the ways HSPICE is combined with other excellent tools to solve a variety of problems. The science buff in me loves seeing the latest electromagnetic analysis tools, and how they are getting faster and more accurate for solving a variety of geometries – and extracting models – that are very important for circuit and system design. The EE in me loves seeing the Design Environment tools – those that run HSPICE under the hood – how they make the designer more productive, and how they handle all the data and test benches that are crucial in modern design. The mathematician and computer buff in me loves seeing the behavioral modeling solutions used with HSPICE, such as IBIS and IBIS-AMI, and how they streamline the design and verification flows. The highlight was talking with customers that use HSPICE with the HIP tools, and all the amazing engineering solutions they are coming up with.

Q- How do you think this event could be improved?

A- I had such a good time, and the event was so well put together, with such excellent food and drink, it would be hard to improve upon. One thing: it was impossible to talk with all the people I had hoped to, and it was difficult connecting with them again at DesignCon with everyone’s busy schedules. In hindsight it would have been nice to have also had a Synopsys HSPICE exhibit at DesignCon, where HSPICE users and developers could connect and share additional information informally without the time constraints necessary for the SIG event.

Q- Based on the audience, which hot topics would you select for our next event?

A- Based on questions I had afterwards, there was a lot of interest in our new transient noise analysis solutions, and how they apply to challenges in both analog design and signal integrity. With ever higher speeds, and smaller geometry technology trends, design engineers must continually contend with shrinking signal-to-noise ratios. Transient noise simulations allow them to realistically predict signal and noise combinations and interactions. This is definitely a hot topic of interest for the future!

Input well taken, I have just signed Scott for an other post on HPP transient noise…..

That’s it for this post. If you want more information (and more visual content ) , you can use the following link to our 2012 HSPICE SIG Videolog page :

www.hspice-sig.com

A bientot !

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week
Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up
your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast
 One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency
) can be set independently from the y-axis (be it voltage, current
) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end




; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat 
 ***
   *** loading waveform file t1.dat    
 ***
   *** loading waveform file t2.dat    
 ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list



Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

Happily, improvements in processor technology have provided new machines with multiple processing cores on the same chip. Although HSPICE has had the ability to use these cores for several years now that hasn’t stopped us from making improvements in our multi-core processing capabilities.

Synopsys recently released a new capability in HSPICE that improves the scalability of simulations on machines with four or more cores. This new high-performance multi-processing capability is seeing great scalability on multiple core machines:

These are average speedups on top of the over 5x speed improvements on single-core HSPICE that our team has already achieved over the past few years. Many of our simulation tests on four cores are reaching even higher performance while maintaining the golden accuracy you demand from HSPICE.

I’d like to go into more detail about how this great new technology works but given that it is patent-pending, I will save that discussion for another blog entry.

Kishore

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

We pondered how we could do this work within the tight time schedule allotted by the customer. They needed a working design in three months and we didn’t have time to start from scratch.

Enter Custom Designer. In use by hundreds of our Solutions Group analog IP designers, its open framework, features, powerful scripting capabilities and overall flexibility were to be the key to resolving this problem.

For those of you who missed my SNUG presentation, we’ve written it up and posted it on the Synopsys website:

Reverse Process Migration from 65nm to 130nm in Under Three Months

Enjoy,

Bob

I’m new to this blog stuff. I usually spend my days with my head down working through specs, schedules and the accompanying blizzard of emails and phone calls as we work out the details of the next big release. So, again, welcome–and here we go!

When I was asked to do this blog, I thought, “What would I say?” and in that reflection I realized that I should take a short trip to the past and summarize what we’ve been up to here at Synopsys.

When I joined Synopsys, I had to tackle the immense problem of architecting a custom design solution almost from the ground up. We already had a lot of the problem solved—we had our world-class transistor-level simulators, our strong offerings in digital design and physical verification, and all of the other pieces that make Synopsys the world-class company that it is. We also had a pretty clear idea of how analog/mixed-signal design teams build their flows and use our tools, as well as the tools of many other EDA companies.

We also had access to many excellent solutions in the open-source and open-licensed software realm. We had standards like Open Access for the database, TCL for the scripting language and the myriad of other design standards that Synopsys has been proud to support because it solves a bigger problem for the industry at large.

What we needed was a solution that would tie all of this together. We knew there were problems. Essentially, EDA tool innovation for custom and analog design was stalled and we needed to solve a number of problems with modern solutions. We chose three guiding concepts:

1. Productivity
2. Openness
3. Familiarity

We picked these concepts because each of them in their own way represented a block to moving the state-of-the-art forward.

The overriding concept we focused on was improved productivity. Face it, schedules shrink and when your design slips your competitors are waiting to pounce. Without a solution that improves your productivity, you don’t have a solution.
Another key concept was openness. The complex environments that designers build  today demand an end to proprietary formats, uncooperative tools and some way to glue them together without learning yet another programming language (ah!
 another hidden productivity gain!).

Familiarity was another requirement because we wanted to increase productivity, not destroy it. Ever sit down to a new version of software and find that you need to [shudder] read the manual? We knew that no matter how cool our new tool was, no one could afford to adopt it if there was too much pain and agony involved in earning how to use it.

Fast forward to 2008, when we released Galaxy Custom Designer. It was architected to bring all of these concepts into being. Add to that our simulators, our digital tools, our physical verification tools and the fact that we make them all work together and now you’re talking are real solution!

There’s so much we can’t put in a whitepaper or a datasheet or in the formal documentation. So we’re going to use this blog to share our experts’ tips and tricks so you can get the most out of your custom design flow.

I look forward to blogging (I really do) and working with my colleagues Kishore and Bob and their teams to provide you with a place to see what we are up to. We’ve traveled a long road to get where we are, and now it’s time to show you what’s in store on the road ahead.

I hope you enjoy it!

Fred

Hello, and welcome to our new blog on the state of custom and AMS IC design at Synopsys. We set out some years ago to address the need for alternatives in custom and analog design software, and with the launch of Galaxy Custom Designer in 2008 we are seeing that vision realized.

Synopsys has amassed a powerful presence in the circuit simulation market. Our flagship products, HSPICE and CustomSim, form the backbone of transistor-level design and verification worldwide. Behind these products is a very talented group of individuals who are hard at work on solving some of the thorniest problems facing the EDA market.

Our own digital and analog IP design groups use these products to provide cutting-edge solutions for tough problems. Our proven AIP is used in designs worldwide and before it gets to you, it’s been through the wringer by a set of designers who have no mercy for bad chips.

I’d like to tell you what we have in store for you on this blog.

We have asked two of our most respected thought leaders in their domains to post entries on this blog:
Kishore Singhal: circuit simulation expertise
Bob Lefferts: a user’s perspective designing with Synopsys’ custom design flow
and, of course, I will continue to post my thoughts on custom design and implementation

In the coming weeks, each blogger will post entries on topics in his domains of expertise. You can expect everything from the technical background of the tools, tips and tricks to make you more productive, and ways to extend and integrate your design flows. And every now and then members of our technical teams will also share their experiences with you.

So thanks for reading this reinvigorated Analog Insights blog today. I can guarantee you—there’s a lot more to come!

If you are reading this, you may have had thoughts on blogging yourself, or perhaps you already are a blogger. One of the most valuable lessons that I have learned from writing a blog is how it can be be used for creating and publicizing my personal “brand”. Personal branding is a way to demonstrate the unique expertise and value that you can provide, to potential employers as well as to colleagues in your profession.

I was first introduced to the topic of personal branding in an article for which I was interviewed by EDN magazine; Life after layoffs: How to move forward after a job loss. Since then I have been asked to share my experience as a blogger with others, most recently at a career networking group hosted by Right Management here in Silicon Valley. My “Top 10 ways to attract subscribers to your blog” may be helpful to you in developing your own personal brand through blogging. You can view the slide show of my presentation here: Developing Your Personal Brand Through Blogging.

-Mike

No… I’m not referring to the infamous Denali Party at DAC. It’s really hard to be hip if you dress like those guys in Disco Inferno. No, if you really want to get HIP at DAC, you need to know about the HSPICE Integrator Program. Clever… eh?

I think we all know that SPICE simulation is the #1 day-to-day workhorse tool for circuit designers. You’ve seen me write about this before (Analog design is NOT black magic… but it is VERY hard, and More “black magic” mumbo jumbo… will it ever end?). Nevertheless, there is still a lot of whining in the press (generally not from analog designers) about how SPICE has been in use for so long… so therefore nothing new has been done in analog EDA. To which I say hogwash!. It may be true that SPICE has been around at least as long as disco, but the difference is that SPICE, and particularly HSPICE has never gone out of style.

There is a lot that’s new with HSPICE and Fast-SPICE, which you can hear about in the Synopsys DAC presentation titled “Advances In Circuit Simulation and Mixed-Signal Verification“.

Here is the description:

Come see the latest improvements in Synopsys’ transistor-level circuit simulation solution. This session will cover updates on the latest 40-nm device models, performance improvement and multi-core in HSPICE, fast and accurate transient simulation and mixed-signal verification in FastSPICE, and the best-in-class mixed-signal waveform analysis and debug capabilities.

Other simulators compare themselves to HSPICE because HSPICE is the incumbent gold standard in the industry. HSPICE has the highest level of silicon correlation in the industry, and recently Synopsys partnered with TSMC to develop the modeling interface technology that will be used for 40nm and beyond. An entire network of companies (or ecosystem in marketing speak) provide value-added solutions that employ HSPICE as the core simulation engine. To better support this HSPICE ecosystem, Synopsys recently created the HSPICE Integrator Program. Twenty-five EDA vendors composed the founding group of companies for HIP.

You can hear more about HIP when you visit DAC in Anaheim. You will see HIP members displaying the “integrated with HSPICE” stamp on their presentations.

With silicon-accuracy being such a critical issue, I would like to highlight two of the HIP members that will be showing solutions for more accurately modeling silicon variability. This goes straight to the issue I have discussed recently about how silly it is to focus on matching one SPICE simulation data point, rather than looking at the true distribution of circuit performance (Simulation accuracy… it’s the silicon, ******!).

Solido Design Automation will be presenting a technical seminar at DAC titled “Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design“. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented. You can find out more about the Solido solution for performing statistical variation analysis by clicking on the link to register for their seminar.

MunEDA will also be presenting their HIP solution at DAC in an “Automatic Flow for Library Cell Optimization with Synopsys HSPICEÂź & MunEDA WiCkeDℱ“. The MunEDA solution enables users to take into account inter- and intra-die variation and the effects on parametric performance such as leakage and timing. As an added incentive there will be a Bavarian Beer event at the MunEDA booth on Wednesday afternoon.

So… it’s too bad there is nothing new going on in analog EDA, huh?

Don’t forget to register for the Synopsys AMS breakfast at the Marriott on Tuesday morning. Our topic is AMS Verification and Moore’s Law
 solutions for 45nm and beyond.

I hope to see you in Anaheim.

-Mike
SPICE HSPICE Fast-SPICE Design Automation Conference Synopsys