Archive for the 'AMS Circuits' Category

While at SNUG, I attended our AMS technical track session. One of the presentations described an innovative flow using UVM with Verilog-AMS. Synopsys CustomSim-VCS was successfully used on AMS designs to demonstrate the performance advantages of this methodology. The title was:

“Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure” by Warren Anderson and Ravi Ram from AMD, and Vijay Akkaraju, from Synopsys.

To give you a little more insight (don’t thank me ), this paper describes specific application of RTL verification methodology for AMS designs. Given the increasing complexity of mixed-signal circuits, a larger and larger number of stimulus need to be ran  to ensure functional correctness.  Because of lengthy run times of SPICE-based simulations and limitations of Verilog only models, more sophisticated approaches are needed.  AMD presented their approach, where low-level analog blocks were modeled using Verilog-AMS, and instantiated in a System Verilog top-level testbench for mixed-signal simulations. This flow was successfully implemented using Synopsys CustomSim-VCS.

Because I am a really nice person , I have included the presentation at the end of this post.

In this interview, Warren and Vijay share their insights about this approach and their overall experience at SNUG.

Warren Anderson

Warren Anderson is currently a Fellow at AMD’s Boston Design Center, where he works on high-speed I/O and electrostatic discharge (ESD) protection design.  Warren leads a team designing I/O and ESD circuits and developing solutions for high-speed off-chip signaling on AMD’s microprocessors.  Prior to joining AMD, he worked for Intel, Hewlett Packard and Digital Equipment Corporation. Warren’s areas of expertise include I/O circuit design, I/O jitter modeling and performance prediction, ESD protection, and signal integrity.  His publications include numerous papers on ESD protection design as well as contributions to three books. Warren currently holds 11 patents on ESD protection devices, circuits, and I/O design techniques.

Vijay is an Staff Application Consultant for Synopsys’s Simulation products, supporting key strategic accounts in Silicon Valley. He has been in the semi-conductor industry for 13 years including multiple roles in Design Engineering and has been part of 17 Silicon tape-outs. Before his current role he had stints in Analog Devices, AMCC and a start up.

Q- Warren, what was your overall experience at SNUG as a speaker? Which feedback did you receive after your presentation?

A- It was a very good experience.  I particularly enjoyed the Q&A discussion after the talk.  We received many thoughtful questions, showing that the audience was highly engaged during the talk (and it’s always nice for a speaker to know that the audience stayed awake!).  The amount of time allotted for the talk and questions was just right, making for a comfortable setting and pace.  The publication submission process was well organized and easy to follow.

Q- Could you please describe your job responsibilities within AMD ? What types of circuits do you simulate and which specific  Synopsys tools/simulator do you use ?

A- I manage a design team working on custom circuits for memory I/O.  My team is responsible for the transistor-level design of the circuits discussed in the paper: drivers, receivers, amplifiers, comparators, biasing, clocking, etc.  Most of our work involves creating and tuning the transistor-level design through HSPICE.  For the Verilog-AMS modeling, we run VCS+CustomSim/XA.

Q- Can you give us some background on this paper and using Verilog-AMS in conjunction with UVM? What were you trying to achieve?

A- High-speed I/O designs use a large amount of digital logic to control analog circuits.  The increasing mixed-signal nature means more digital-analog interactions, where sequences have to be performed in the right order, control bits need to be set properly, and missing a flop on an analog control wire could completely break the design.  In fact, in our prior project, we had a couple of near misses where we caught a few such bugs late in the project by manual inspection or transistor-level co-simulation with XA.  I didn’t want to repeat that scenario.

Verilog-AMS models run faster and follow a top-down design approach, enabling earlier verification of the mixed-signal interactions.  UVM increases our coverage of mixed-signal interactions by allowing us to randomize variables, such as offsets, device-related variations, and delays, in the Verilog-AMS models.

Q-   What are the main advantages (besides performance) in using this flow? Which challenges did you encounter during implementation?

A- As I mentioned, transistor-level co-simulation with VCS+XA has to wait for the transistor design to complete before it can be run.  Verilog-AMS models enable mixed-signal verification earlier in the design process, before the transistor-level design is finished or sometimes before it even starts, catching bugs earlier when they are easier to fix.  I think of it as RTL for analog designs.

In our implementation, automatic converter insertion caused some challenges.  It took a bit for us to become educated on the converter insertion algorithm, but it made sense in the end.  In order to configure the simulation to propagate analog signals through the top-level I/O block the way we wanted, we had to edit a few models once we saw where the converters were placed.  We did find a few bugs in the simulator, but those have been fixed.  Synopsys was responsive and committed to help us meet our design completion targets.

Q- What do you see moving forward in advanced Mixed-Signal/SoC verification?

A- We want to unleash more of the power behind the mixed-signal verification models and tools.  We will add more variables to our Verilog-AMS models and tie these into UVM constraints and randomization so deeper aspects of mixed-signal interaction can be covered.  In addition, I expect to propagate the AMS methodology to other I/O interfaces within AMD.

Q- Vijay, from a Synopsys point of view, we have a very robust and highly competitive mixed –signal solution using our leading edge fast-spice solver CustomSim in conjunction with VCS. Which design/customers would benefit the most from using this flow?

Vijay Akkaraju

A- I feel most AMS designs where Mixed-signal simulations are more than just “sign-off” can benefit from this methodology. The environments  likely to get the most are the ones with a mature UVM flow with large number of constrained random testcases. Also, designs where some rtl (digital) code can only be reached in a mixed-signal context for purposes of coverage (both functional and code) can immensely benefit from adapting this. I say that since for them, waiting for availability of a finished spice netlist comes in the way of speedy coverage closure. Also, designs with a complex Analog-Digital interface where constraint randomization of stimulus can expose bugs not likely to be exposed using directed testcases only.

You can find the presentation and paper clicking on the link below. Enjoy and see you soon!

SNUG presentation:

SNUG_AMS_v6_final_presentation

SNUG Paper:

SNUG_2012_AMS13

Happy Friday,

“Chose promise, chose due” – In other words, I owed you a full report on our S-parameters tutorial

As mentioned in one of my previous posts, we received a lot of interest for the AMS tutorial we created for DesignCon 2012. We managed to hold 120 persons in average for three hours talking about S-parameter modeling for SI without even locking doors . Our three Speakers (Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys) explored this topic from an intermediate to a more advanced level. Because each speaker is an expert in a different area, we were able to cover this topic from different angles and with a lot of depth. In this interview, Amir, Brad and Donald talk about their presentations and share their overall impressions (I have also listed each presentation below). We will further explore and refine this topic at next year tutorial so you’d better be there  !

Q>  I will be including each of your presentations at the end of this post. Would each of you give a few lines summary of your presentation?

Brad Brim

[Brad]  My presentation can be described as: An introduction to S-parameters with a focus on issues relevant to designers of chips/packages/boards and systems with high-speed signals. A few basic definitions are covered with the major focus being on practical issues SI engineers tend to learn and re-learn all too often.

[Amir] My presentation is titled “SPICE Simulation with Frequency Domain Models” and covers the following topics: What to learn about the channel just by observing its S-parameter and impulse response and group delay;  Correlation/Calibration the models with measurements to increase accuracy; S-parameter data interpolation/extrapolation; What to do about missing DC data, how to “interpolate”, simulate or estimate it; Requirements for transient simulation; passivity, causality; Convolution and maximizing simulator performance; Best practices at getting good S-parameters from EM solvers; Efficient EM solver data formats for SPICE simulation; Handling reference planes for S-parameter Ports; Defining high-speed link simulations in SPICE; Special cases: Power delivery systems and needed modifications to S-parameters; Nonlinear I/O modeling with IBIS and encrypted HSPICE buffers; and Adding DJ and RJ effects with SPICE Thermal noise.

[Donald] My presentation explains how to combine S-Parameters with active models to simulate high-speed serial links and assess performance using eye diagrams.  Now that S-Parameter and AMI models are flowing more freely throughout the industry it has become possible to examine and validate link behavior, pre-hardware.  I offer a full-day Seminar on this topic that shows how to use these techniques to validate a design and its compliance with the major serial standards, even though the standards still have a post-hardware bias.  There’s huge value in figuring out how to do this before you fabricate or assemble anything.

Q> It appears that this topic was really well received among DesignCon community. Which feedback did you receive from the attendees?

Amir Motamedi

[Brad]  I received positive feedback from attendees concerning the breadth of what was covered. Not from a technical or theoretical perspective but from basic concepts to detailed application for high-speed serial link systems. My choice not to focus on regurgitating basic concepts and definitions that may be found elsewhere on the web, in college texts or in commercially available training classes seemed to resonate with attendees; especially the lessons I covered for which I work with EDA tool users on a daily basis to learn and re-learn. Amir’s intuitive description of the relevance of S-parameter behaviors was also noted as a big positive by attendees. They liked the practical knowledge Amir was able to share based on his experience applying S-parameters in his designs. Donald’s presentation addressed a hot topic for DesignCon for the past few years – high speed serial links. Since a large portion of the attendees are focused on board design, his system-centric focus of bits-to-bits serial link communications through each chip/package/board was highly relevant. For all three presentations I received feedback they were received well in the tutorial nature intended; not as too detailed or too factual, but rather fun and informative.

[Donald] One attendee claimed it was the most useful session he attended.  I think the combination of the talks – all the way from matrices to Bit Error Rates – scratched where people itched.

Q> I noticed DesignCon had an increasing content of AMS/RF related papers and subjects. Have you noticed a change in DesignCon traditional venue?

[Brad]  I have observed the number of RF-related topics peak and valley over the years at DesignCon. Each year the TPC (technical program committee) does a good job of maintaining the traditional focus of DesignCon with its paper selections. In fact, notice the title of the RF-centric track is “RF/Microwave Techniques for Signal Integrity”. This is true also for the “Test and Measurement Methodology” track. Other conferences such as IEEE MTT Symposium are intended for more pure RF/microwave topics.  RF/microwave measurement conferences also exist; as I am suspect Analog IC conferences are plentiful. I believe the “mixed-signal” portion of AMS and analog-specific designs required to support high-speed signaling is very relevant to DesignCon attendees. As bandwidths increase for high-speed signals, we can expect to see a continued increase in the analog content present in topics of interest to DesignCon. For example, the coupling of analog to digital signal and power noise seems a relevant topic for DesignCon, though the design of a purely analog circuit not relevant to high speed signaling may not be.

[Donald] Higher frequencies have forced SI Engineers to increasingly borrow from RF tools and techniques.  In addition, the abundance of silicon gates has pushed things we used to solve on the PCB inside silicon causing convergence of SI, AMS, and DSP design techniques.  So yes, things are changing – they always do.

Q> which subjects would you add for our next year tutorial? Are there emerging trends/hot topics we should cover?

Donald Telian

[Brad]  We should ask ourselves what questions we ask ourselves or what questions our colleagues and customers ask us repeatedly. As authors or “faculty” as DesignCon called us this year, we sometimes forget the presentation is for the benefit of the attendee (not to hear ourselves talk). This is especially true for a tutorial forum. Even if we personally believe the issue to be trivial or covered well in other readily available media we should consider the frequency with which the issue comes up as an indicator of need for further discussion. A tutorial forum is ideal for this type of discussion, since the authors are likely accustomed to addressing the topic daily and have the skill and readily available materials to share with DesignCon attendees.
I was surprised at the high percentage of package and board designers who attended this AMS-sponsored tutorial. Seems the topic was not as well understood even by these attendees, as I had suspected it would be unfamiliar for AMS IC-centric designers.

[Donald] Emerging equalization techniques and associated IC/PCB design capabilities are the next big thing that will push interfaces faster than 10 Gbps into the mainstream.  Engineers are calling for Tutorials that help them bring these things together at the system level.

**********************

Brad’s slides:

BradBrim_TutorialSlides_final

Amir’s slides:

Amir_slides

Donald’s slides:

Donald_tutorial

Happy Thursday !

Since I had a post on how to improve performance using HSPICE, I am now due for a similar post for CustomSim. CustomSim being our fast spice simulator, different techniques and options can be invoked to speed up simulation and improve performance. With the collaboration of our famous corporate application engineer Tom Hsieh, we are releasing today our secrete recipes

Tom has over 9 years of experience in FastSPICE simulation technologies and applications. He has spent the last 5 years working closely with R&D, sales and marketing to mature and lead deployment of CustomSim. He is a respected expert on FastSPICE simulation of custom digital, analog and memory circuits. Tom holds Bachelor and Master’s degrees in Electronic Engineering from UCLA and Santa Clara University, respectively.

10 tips to improve performance using CustomSim :

#1 – use ‘set_synchronization_level’ cmd for memory circuits:

set_synchronization_level  1|2|3|4|5|6 | 7  (recommend to start with ‘3’)

#2 – invoke multi-threading option: -mt <number> or with the following cmd:

set_multi_core -cpu Ncpu                                                       (With CustomSim 2012.06 release)

#3 – use the new multi-rate engine

set_multi_rate_option –mode 2                                         (With CustomSim 2012.06 release)

#4 – for post-layout  netlists contained large number of coupling caps, use:

set_ccap_option –ccap_to_scap 1 –ccap_to_gcap 1e-18

#5-  re-define the usage of wildcard, especially on post-layout Netlist, use cmd

set_wildcard_rule -match* one                                         (limit the hierarchies to match)

#6- limit the output waveform file size with the following cmd:

set_probe_window [ -window ] tstart [ tstop {tstart tstop} [tstart] ]

#7- reduce simulation time by process only the measurement statement without generate the waveform file with the following cmd:

set_probe_option -netlist_probe_control 2

#8- reduce simulation time by skip simulating the instance that is completely inactive with the following cmd:

skip_circuit_block [-inst inst_name {inst_name}] [-subckt subckt_name {subckt_name} ]

#9- re-use simulation measurement data set directly and post-process data without re-running the same netlist by using the cmd :

xa <Netlist.sp> -c cmd –o output_file

include the following cmd

meas_post –waveform waveform_file

#10- reduce simulation time by stopping your simulation as soon as the last measurement is completed by specifying the following option:

.option autostop

Enjoy !

Good morning ! well, since this is a technical blog, I thought I owed you some tools-related posts I am compiling below 10 tips to make your HSPICE simulation even more efficient

If you want to look into those options in more details, we conducted a webinar a few weeks ago hosted by Szekit Chan, that discussed those topics in more details. I have listed the link at the end of this post.

And as usual, feedback/comments are more than welcome !

#1 – use HSPICE runlvl to replace old options convergence parameters:

.option runlvl=1|2|3|4|5|6

#2 – invoke multi-threading option with HPP: -mt <number> -hpp

#3 – use distributed processing: -dp <number>

#4 – for post-layout  netlists, use RC reductions techniques: .option sim_la

#5-  avoid the usage of wildcard within your .probe statement, especially on post-layout netlist

Instead of .probe tran v(*) I(*) use .probe tran v(xi.*) i(xi.r*)

#6- declare port current directly

Instead of .probe tran isub(*) use .probe tran isub(xinv.vdd) isub(xinv.v*)

#7- if using .ALTER statement, reduce netlist processing and checking time with the following options: .option altcc altchk

#8- reduce simulation time by bypassing element checking and suppressing topology checking with the following options:

.option notop noelchk

#9- re-use simulation measurement data set directly and post-process data without re-running the same netlist by using the command line option:

>> hspice –i ***.tro –meas <meas_file>

#10- reduce simulation time by stopping your simulation as soon as the last measurement is completed by specifying the following option:

.option autostop

The link to the webinar is:

https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=381394&sessionid=1&key=E48E59582DA6321FCDE78BBF5BEFD169&cmp=WEBR-circ100094-HPW

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

The tutorial we created for DesignCon AMS track was very well received, we had an average of 120 people over 3 hours. I will have a following post where I discussed the content and format with the three speakers and post their presentations, as multiple attendees asked for it. I received really positive feedback from the audience, as it bridged Signal Integrity with Spice simulators. The tutorial also provided various aspects of S-parameter modeling for Signal Integrity. We will probably extend more on this theme next year, with an increased focus on addressing passivity or causality problems while dealing with S-parameters.

As a chairman of the AMS track, it is actually interesting to notice that AMS is on the raise. In addition to an extremely well attended tutorial, we received more papers this year and even had a specific panel on Analog. Focus for the AMS papers were mostly on PLLs, I am hoping to expand it next year to mixed-signal design and simulation challenges as well as behavioral modeling. So if you have any ideas, feel free to send it my way.

The panel “Is Analog making a comeback?” moderated by Brain Bailey included experts in different areas (and yes, we did have our famous Synopsoid Navraj Nandra in the panel). Personally, I don’t think Analog ever left (which is good, it means job security for me). There was in this regard not a really definitive answer to this question, as the complexity and challenges of new mixed-signal designs and advanced process nodes makes it hard to measure. However, an emerging trend, confirmed by both SYNOPSYS and CYPRESS, seems to be that Analog is now finding its way into digital periphery products and other generic digital processing ICs.

SYNOPSYS also had its HSPICE SIG event during that week…Great event, DesignCon committee should definitively use the same catering services for next year . We had more than 120 customers and packed HIP exhibit hall.  I will also talk about this event in more details in a following post, as we had a good crowd and really good technical content from our four speakers.

That’s it for now. ..Until my next post !  A bientot

Happy Thursday !

I would like to inform you of our Synopsys HSPICE Special Interest Group event. In addition to having a culinary experience and meeting great people , you will be able to network with peers and hear what industry leaders have to say about using HSPICE in some of today’s most challenging designs. The 2012 event is being held on January 31 at the Marriott Hotel in Santa Clara and will focus on Signal and Power Integrity.

The event format is the following:
DATE:    January 31, 2012
TIME:    6:00 p.m.- 8:30 p.m.
LOCATION:        Santa Clara Marriott Hotel
2700 Mission College Blvd.
Santa Clara, CA 95054
map & info.

HSPICE SIG EVENT AGENDA
6:00 – 7:00 p.m.                Registration and Cocktail Hour
7:15 – 8:15 p.m.                Dinner and Technical Presentations:
Altera: “28nm MOSFET Aging Modeling and Simulation Using HSPICE MOSRA”
Cavium: “HSPICE Signal Integrity Portfolio for High-Speed SERDES Channel Design”
Micron:”Simulating IBIS 5.0 Power-aware Models using HSPICE”
8:15 – 8:30 p.m.                Q&A and Prize Draw

This event is a great opportunity for users to exchange challenges, solutions and best practices as well as to network with peers.
If you are interested, I have included our registration page below:

http://app.connect.synopsys.com/e/es.aspx?s=700&e=29779&elq=2e0672756e024505b1dfd4f2122c3374

I will post next an interview I conducted with Amir Motamedi, one of our speakers for last year event, where he shares his insights about  HSPICE SIG event and Signal Integrity.

Hope to see you there !

Hello!

Do you ever

• wonder what the latest news is for Synopsys Custom and AMS solution? how others are using Synopsys solutions?
• wish you had insight into the latest advances in Synopsys solutions?
• have the urge to send comments to Synopsys team, via your smart phone?

The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.

Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.

For example, you will be able to find:

• List blogs where we would provide tricks and tips to improve simulator performance and convergence (for example “5 tips to spice up…your PLL design :^), I know you are all disappointed..)
• Interview blogs with CAD, design, verification, and modeling engineers to get more insight on their work and their best practices using Synopsys AMS tools
• Technical blogs, where we would go deeper on specific Custom design and AMS subjects
• Industry analysis blogs, where we would capture incoming hot trends in technologies and describe Synopsys solutions
• Webinars, Videos showcasing advanced features and/or flows

We of course welcome your inputs and suggestions on how to improve our blog, as we want it to be innovative, instructive and interactive. I hope you would appreciate and use this blog. See you at our next blog!

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

One of the Custom Designer developers  said, “That capability looks a lot like this new feature that will be released in the up coming version of Custom Designer.” We all got VERY excited when he then demonstrated the beta version of this new feature to the assembled group. It was really cool and very useful. We then asked for a minor extension of the feature and he had that up and running in a trial tcl script within the hour. Sweet. We can hardly wait for the next release.

Later that night at dinner, one of the corporate apps engineers came up to me and said, “You don’t remember do you? I visited you 7 months ago with a list of planned features for CD and you looked it over and said –  “these are all OK but what would be really nice is if you could…” and then you described this new feature. We thought it was a great idea and put it at the top of the list.” I then told him that it was no wonder I had liked the new feature so much but I also told him I was terribly disappointed. When he asked why I was upset I said “Well if I had remembered I had suggested it I could have said ‘7 months – what took you so long!’”.

So when you see the next version of Custom Designer, there is at least one really cool feature that will blow you away (I haven’t seen the other cool one yet – just heard about it). You will know which feature it is because it is so useful. You will also know how we feel to work with an analog design tool that is growing and improving DAILY with developers who listen to us – how sweet it is!

Bob Lefferts

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast… One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency…) can be set independently from the y-axis (be it voltage, current…) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end

…

; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat … ***
   *** loading waveform file t1.dat    … ***
   *** loading waveform file t2.dat    … ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list
…

Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

Happily, improvements in processor technology have provided new machines with multiple processing cores on the same chip. Although HSPICE has had the ability to use these cores for several years now that hasn’t stopped us from making improvements in our multi-core processing capabilities.

Synopsys recently released a new capability in HSPICE that improves the scalability of simulations on machines with four or more cores. This new high-performance multi-processing capability is seeing great scalability on multiple core machines:

These are average speedups on top of the over 5x speed improvements on single-core HSPICE that our team has already achieved over the past few years. Many of our simulation tests on four cores are reaching even higher performance while maintaining the golden accuracy you demand from HSPICE.

I’d like to go into more detail about how this great new technology works but given that it is patent-pending, I will save that discussion for another blog entry.

Kishore