DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level
Posted by Hélène Thibiéroz on May 22nd, 2013
Well DAC 2013 is around the corner, so I guess it is time to blog about it, especially since this is in Austin
And no, I am not going to tell you about the best BBQ joints or sushi places (yes I did say sushi in Texas) since I lived there for almost 15 years, but I’m going to tell you about our DAC AMS lunch event.
We wanted this year to present some of the challenges Synopsys customers face to ensure successful AMS design validation for advanced process nodes. Consequently, our topics vary from low power and reliability to mixed-signal verification and memory characterization.
Our speakers are industry experts coming from various sectors (SoC, Mobile, Memory, SRAM, etc.) so they will present a very exhaustive landscape of those challenges as well as Synopsys latest flows and features to further tune your current AMS methodologies for performance and accuracy. Now, I am listing below companies, titles and abstracts, that would probably convince you more than a long marketing speech
Our speakers are (in chronological order):
Micron – Off-Chip and On-Chip Power Delivery Modeling with HSPICE
Abstract: Power delivery for a part (be it memory, logic, or otherwise) is of paramount importance, requiring the need to design a Power Delivery Network system which is optimized for the various models of die demand, at the least risk of resonances. Hspice and Finesim are used to characterize the various block models, to spot potential problems and finally to run transient sims to validate AC optimization.
ARM – Overcoming Challenges of FinFET Memory IP using FineSim
Abstract: FinFET process technology offers significant improvements in performance and power efficiency of ARM-based SoCs. Along with these improvements come many challenges in the design, margin analysis and model generation for advanced embedded memory. During this luncheon ARM will discuss some of the key challenges of FinFET memory development and how Synopsys’ FineSim fast SPICE simulator is used to provide full-featured, high-quality ARM Artisan® memory IP for mobile, network storage and server applications.
STE- Improve IC-level verification coverage by using assertions with CustomSim-VCS multi-thread real number flow
Abstract: Time and resources to ensure a good coverage for IC-level functional verifications are growing year after year with design complexity. There is, therefore, a need to reduce simulation setup and analysis. Discovery-AMS with VHDL Real Number approach permits to maximize and accelerate verification coverage by creating easily co-simulation setup and taking advantage of FastSPICE multithreading.
Broadcom- Advanced Memory characterization using FineSim for performance and accuracy
Abstract: Broadcom has developed a complex internal flow to create and characterize compiled memories that are used throughout their production chips. This flow highly leverages Synopsys’ flagship simulators FineSimPro and FineSimSpice. The simulators are used to characterize the memory for three distinct needs, timing, power and leakage. BRCM fine tunes FineSim technology to give the required accuracy/performance needed for each area of characterization.
ST : Aging model implementation using MOSRA API flow from HSPICE to CustomSim
Abstract: An innovative platform of reliability simulation including all front-end wear-out mechanisms is presented. Customized physics-based models of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are implemented in MOSRA. The aging models are developed for HSPICE simulator and extended to FastSPICE CustomSim. Aging simulation with CustomSim is a promising solution enabling the robustness assessment of large circuit and providing both accuracy and speed.
Because we wanted to offer a depth and breadth of understanding of verification challenges and related solutions, this AMS lunch-on should be extremely valuable to anyone involved with advanced AMS verification.