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Synopsys Invited FinFET talk at WMED: Q&A on FinFET variability and its impact on digital and analog circuits

Posted by Hélène Thibiéroz on March 28th, 2013

If you have been following my blog, you may have noticed a couple of posts on FinFET technology, mostly on the modeling side. I recently worked with the WMED committee to look at innovative subjects (especially for those spots after lunch time :) ). One topic we selected was the challenges faced by analog and digital designers when using a FinFET based process.

 

WMED stands for IEEE Workshop on Microelectronics and Electron Devices and will occur on April 12, 2013, at Boise State University, Boise, Idaho.

http://www.ewh.ieee.org/r6/boise/wmed2013/WMED2013.html

In this post, I am interviewing Victor Moroz about his guest talk at WMED on FinFET variability and its impact on digital and analog circuits.

Dr. Victor Moroz is a Synopsys Scientist, engaged in a variety of projects on modeling 3D ICs, transistor scaling, FinFETs, stress engineering, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters and over 100 technical papers, invited presentations, and patents. He has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, and ESSDERC.

Q- Victor, you are deeply involved with SYNOPSYS and major foundries/semiconductor companies in our FinFET initiative. Can you describe SYNOPSYS leading role in this area?

Synopsys is involved in three different stages of FinFET chip development: a) providing tools and services for modeling and optimizing FinFET technology, b) providing tools and services for synthesizing, routing, and simulating FinFET circuits, and c) creating FinFET circuit IP for digital and analog chips. The FinFETs bring a number of benefits, but also several FinFET-specific issues that need to be carefully managed to achieve a good combination of performance, cost, manufacturability, and reliability. Early engagement with the major foundries/semiconductor companies ensures a smooth transition from planar MOSFETs to the FinFETs.

Q- Your talk is about FinFET variability and its impact on analog and digital designs. Can you tell us a little more about it? How is SYNOPSYS addressing those as a leading EDA provider?



Transistor variability is a key factor standing in the way of reducing power consumption in mobile devices. Typical three sigma Vt value for a narrow 28 nm planar MOSFET exceeds 150 mV. The circuit has to be able to handle the entire transistor population, ranging from the leaky transistors with low Vt to the hard-to-turn-on transistors with the high threshold. The low threshold side of the distribution is defined to meet the static power consumption spec and the high threshold side of the distribution defines the minimum possible power supply voltage Vdd. Any reduction in the threshold distribution width directly translates into reduction of Vdd, which affects dynamic power consumption as Vdd^2.

The dominant threshold variability mechanism for planar MOSFETs is random dopant fluctuations (RDF). For the first generation of FinFETs with doped channel, the RDF is still present, but at significantly suppressed level due to the tighter gate control. However, several new FinFET-specific variability mechanisms enter the picture. Subsequent FinFET generations with undoped channel will experience rise and fall of the major variability mechanisms, notably those related to geometry and patterning fidelity. The dominant RDF variability that you see in the planar MOSFETs is inevitable, because it is impossible to control positions of all the dopant ions in the channel. Therefore, it was imposed on the entire industry in a very similar way as there is not much you can do about it. On the contrary, the geometry-related variability mechanisms that are dominant in FinFETs, can be continuously tightened by perfecting the semiconductor manufacturing equipment, such as etching, deposition, lithography, epitaxy, and other critical process steps that define the shape and the size of the FinFETs.

The impacts of FinFET variations on the digital and analog circuits are substantially different. These differences define the distinct approaches in handling variability in analog and digital circuit design.

Q- Synopsys is currently working with major design houses. Moving forward, do you see a large deployment and use of FinFET technology for low power designs and advanced process nodes? What are the main compelling factors?

Yes, we definitely see a big role of the FinFET technology for low power designs. The main compelling factors are the reduced random variability and the improved short channel effects leading to better scaling potential w.r.t. the planar MOSFETs. There is a significant hurdle to develop the FinFET manufacturing process that requires a huge effort. Once the hurdle is cleared, the FinFETs will enable scaling for the next several technology nodes.

Hope you enjoy Victor’s interview!  If you would like more information, I am listing below the link to WMED conference technical track:

http://www.ewh.ieee.org/r6/boise/wmed2013/Technicalprogram.html

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