Archive for 2010

NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

We are pretty excited about this new integration and held a webinar on the topic this week. If you missed, don’t worry, it is archived on our website and you can watch it here.

Fred

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

Rather than trying to completely automate away the layout phase (as some have tried) we chose a different path. In analog designs the layout designer must have complete manual control of the layout so how do you automate that?

We chose a new path
 we decided not to enforce our automation on designers but rather give them a toolbox of powerful new features that simplify their jobs and help get it done quicker. This is the first in a series of blog entries that will feature some of the ideas our team came up with after talking to many, many layout engineers.

Today’s topic is zooming and it’s evil twin counting grids. Layout designers often spend a great deal of time zooming into a region to start a wire, then zooming out to route it followed by a zoom back in to finish aligning the end of the wire. That’s a lot of clicks and often the designer has to go back across the wire counting grids and moving segments to make sure that he hasn’t violated the rules.

What if you could wire at high-altitude and eliminate the zooms? What if you could click near a terminal or a gate and have the new wire adopt the width, snapped to and pre-aligned with the terminal and just start wiring immediately?

We call it “SmartConnect” and it does just that. Another cool feature is SmartConnect’s “Alignment Markers” that make it obvious when you are aligned with the left, center or middle of another object.

Sounds simple but these features enable very rapid wiring without forcing the layout engineer to accept somebody else’s idea of what makes a good layout.

‘Til next time, keep wiring away and stay tuned. We’ve got a lot more stuff in the pipe for our next release that I think you will really like


Fred

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

One of the Custom Designer developers  said, “That capability looks a lot like this new feature that will be released in the up coming version of Custom Designer.” We all got VERY excited when he then demonstrated the beta version of this new feature to the assembled group. It was really cool and very useful. We then asked for a minor extension of the feature and he had that up and running in a trial tcl script within the hour. Sweet. We can hardly wait for the next release.

Later that night at dinner, one of the corporate apps engineers came up to me and said, “You don’t remember do you? I visited you 7 months ago with a list of planned features for CD and you looked it over and said –  “these are all OK but what would be really nice is if you could…” and then you described this new feature. We thought it was a great idea and put it at the top of the list.” I then told him that it was no wonder I had liked the new feature so much but I also told him I was terribly disappointed. When he asked why I was upset I said “Well if I had remembered I had suggested it I could have said ‘7 months – what took you so long!’”.

So when you see the next version of Custom Designer, there is at least one really cool feature that will blow you away (I haven’t seen the other cool one yet – just heard about it). You will know which feature it is because it is so useful. You will also know how we feel to work with an analog design tool that is growing and improving DAILY with developers who listen to us – how sweet it is!

Bob Lefferts

Hi Everybody!

First my apologies for our silence over the past couple of weeks. We’ve had our head down in preparation for and the delivery of the 47th Design Automation Conference in Anaheim last week (47? Really?)

Synopsys had an outstanding DAC this year and had many announcements to go with it. In addition to our main booth, we showed Custom Designer, HSPICE and CustomSim at a number of different venues throughout the show and that kept us, ah, rather busy.

Our demo suites were jammed and we hosted numerous customers, editors, analysts, breakfasts, lunches and dinners and the transcripts of many of those will be available soon. Stay tuned.

The show is over and now that we can breath, we’ll get back on track with some new posts about some great new technology we have coming up.

Fred

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast
 One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency
) can be set independently from the y-axis (be it voltage, current
) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end




; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat 
 ***
   *** loading waveform file t1.dat    
 ***
   *** loading waveform file t2.dat    
 ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list



Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

Happily, improvements in processor technology have provided new machines with multiple processing cores on the same chip. Although HSPICE has had the ability to use these cores for several years now that hasn’t stopped us from making improvements in our multi-core processing capabilities.

Synopsys recently released a new capability in HSPICE that improves the scalability of simulations on machines with four or more cores. This new high-performance multi-processing capability is seeing great scalability on multiple core machines:

These are average speedups on top of the over 5x speed improvements on single-core HSPICE that our team has already achieved over the past few years. Many of our simulation tests on four cores are reaching even higher performance while maintaining the golden accuracy you demand from HSPICE.

I’d like to go into more detail about how this great new technology works but given that it is patent-pending, I will save that discussion for another blog entry.

Kishore

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

We pondered how we could do this work within the tight time schedule allotted by the customer. They needed a working design in three months and we didn’t have time to start from scratch.

Enter Custom Designer. In use by hundreds of our Solutions Group analog IP designers, its open framework, features, powerful scripting capabilities and overall flexibility were to be the key to resolving this problem.

For those of you who missed my SNUG presentation, we’ve written it up and posted it on the Synopsys website:

Reverse Process Migration from 65nm to 130nm in Under Three Months

Enjoy,

Bob

I’m new to this blog stuff. I usually spend my days with my head down working through specs, schedules and the accompanying blizzard of emails and phone calls as we work out the details of the next big release. So, again, welcome–and here we go!

When I was asked to do this blog, I thought, “What would I say?” and in that reflection I realized that I should take a short trip to the past and summarize what we’ve been up to here at Synopsys.

When I joined Synopsys, I had to tackle the immense problem of architecting a custom design solution almost from the ground up. We already had a lot of the problem solved—we had our world-class transistor-level simulators, our strong offerings in digital design and physical verification, and all of the other pieces that make Synopsys the world-class company that it is. We also had a pretty clear idea of how analog/mixed-signal design teams build their flows and use our tools, as well as the tools of many other EDA companies.

We also had access to many excellent solutions in the open-source and open-licensed software realm. We had standards like Open Access for the database, TCL for the scripting language and the myriad of other design standards that Synopsys has been proud to support because it solves a bigger problem for the industry at large.

What we needed was a solution that would tie all of this together. We knew there were problems. Essentially, EDA tool innovation for custom and analog design was stalled and we needed to solve a number of problems with modern solutions. We chose three guiding concepts:

1. Productivity
2. Openness
3. Familiarity

We picked these concepts because each of them in their own way represented a block to moving the state-of-the-art forward.

The overriding concept we focused on was improved productivity. Face it, schedules shrink and when your design slips your competitors are waiting to pounce. Without a solution that improves your productivity, you don’t have a solution.
Another key concept was openness. The complex environments that designers build  today demand an end to proprietary formats, uncooperative tools and some way to glue them together without learning yet another programming language (ah!
 another hidden productivity gain!).

Familiarity was another requirement because we wanted to increase productivity, not destroy it. Ever sit down to a new version of software and find that you need to [shudder] read the manual? We knew that no matter how cool our new tool was, no one could afford to adopt it if there was too much pain and agony involved in earning how to use it.

Fast forward to 2008, when we released Galaxy Custom Designer. It was architected to bring all of these concepts into being. Add to that our simulators, our digital tools, our physical verification tools and the fact that we make them all work together and now you’re talking are real solution!

There’s so much we can’t put in a whitepaper or a datasheet or in the formal documentation. So we’re going to use this blog to share our experts’ tips and tricks so you can get the most out of your custom design flow.

I look forward to blogging (I really do) and working with my colleagues Kishore and Bob and their teams to provide you with a place to see what we are up to. We’ve traveled a long road to get where we are, and now it’s time to show you what’s in store on the road ahead.

I hope you enjoy it!

Fred

Hello, and welcome to our new blog on the state of custom and AMS IC design at Synopsys. We set out some years ago to address the need for alternatives in custom and analog design software, and with the launch of Galaxy Custom Designer in 2008 we are seeing that vision realized.

Synopsys has amassed a powerful presence in the circuit simulation market. Our flagship products, HSPICE and CustomSim, form the backbone of transistor-level design and verification worldwide. Behind these products is a very talented group of individuals who are hard at work on solving some of the thorniest problems facing the EDA market.

Our own digital and analog IP design groups use these products to provide cutting-edge solutions for tough problems. Our proven AIP is used in designs worldwide and before it gets to you, it’s been through the wringer by a set of designers who have no mercy for bad chips.

I’d like to tell you what we have in store for you on this blog.

We have asked two of our most respected thought leaders in their domains to post entries on this blog:
Kishore Singhal: circuit simulation expertise
Bob Lefferts: a user’s perspective designing with Synopsys’ custom design flow
and, of course, I will continue to post my thoughts on custom design and implementation

In the coming weeks, each blogger will post entries on topics in his domains of expertise. You can expect everything from the technical background of the tools, tips and tricks to make you more productive, and ways to extend and integrate your design flows. And every now and then members of our technical teams will also share their experiences with you.

So thanks for reading this reinvigorated Analog Insights blog today. I can guarantee you—there’s a lot more to come!